1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
11 #include <linux/kernel.h>
13 u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
14 enum rate_section RateSection)
16 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
19 if (RfPath >= RF_PATH_MAX)
22 switch (RateSection) {
24 value = pHalData->TxPwrByRateBase2_4G[RfPath][0];
27 value = pHalData->TxPwrByRateBase2_4G[RfPath][1];
30 value = pHalData->TxPwrByRateBase2_4G[RfPath][2];
40 phy_SetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
41 enum rate_section RateSection, u8 Value)
43 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
45 if (RfPath >= RF_PATH_MAX)
48 switch (RateSection) {
50 pHalData->TxPwrByRateBase2_4G[RfPath][0] = Value;
53 pHalData->TxPwrByRateBase2_4G[RfPath][1] = Value;
56 pHalData->TxPwrByRateBase2_4G[RfPath][2] = Value;
64 phy_StoreTxPowerByRateBase(
65 struct adapter *padapter
70 for (path = RF_PATH_A; path <= RF_PATH_B; ++path) {
71 base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
72 phy_SetTxPowerByRateBase(padapter, path, CCK, base);
74 base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
75 phy_SetTxPowerByRateBase(padapter, path, OFDM, base);
77 base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
78 phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, base);
82 u8 PHY_GetRateSectionIndexOfTxPowerByRate(
83 struct adapter *padapter, u32 RegAddr, u32 BitMask
86 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
87 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
90 if (pDM_Odm->PhyRegPgVersion == 0) {
92 case rTxAGC_A_Rate18_06:
95 case rTxAGC_A_Rate54_24:
98 case rTxAGC_A_CCK1_Mcs32:
101 case rTxAGC_B_CCK11_A_CCK2_11:
102 if (BitMask == bMaskH3Bytes)
104 else if (BitMask == 0x000000ff)
108 case rTxAGC_A_Mcs03_Mcs00:
111 case rTxAGC_A_Mcs07_Mcs04:
114 case rTxAGC_B_Rate18_06:
117 case rTxAGC_B_Rate54_24:
120 case rTxAGC_B_CCK1_55_Mcs32:
123 case rTxAGC_B_Mcs03_Mcs00:
126 case rTxAGC_B_Mcs07_Mcs04:
138 PHY_GetRateValuesOfTxPowerByRate(
139 struct adapter *padapter,
151 case rTxAGC_A_Rate18_06:
152 case rTxAGC_B_Rate18_06:
153 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
154 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
155 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
156 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
157 for (i = 0; i < 4; ++i) {
158 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
159 ((Value >> (i * 8)) & 0xF));
164 case rTxAGC_A_Rate54_24:
165 case rTxAGC_B_Rate54_24:
166 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
167 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
168 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
169 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
170 for (i = 0; i < 4; ++i) {
171 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
172 ((Value >> (i * 8)) & 0xF));
177 case rTxAGC_A_CCK1_Mcs32:
178 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
179 PwrByRateVal[0] = (s8) ((((Value >> (8 + 4)) & 0xF)) * 10 +
180 ((Value >> 8) & 0xF));
184 case rTxAGC_B_CCK11_A_CCK2_11:
185 if (BitMask == 0xffffff00) {
186 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
187 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
188 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
189 for (i = 1; i < 4; ++i) {
190 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
191 ((Value >> (i * 8)) & 0xF));
194 } else if (BitMask == 0x000000ff) {
195 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
196 PwrByRateVal[0] = (s8) ((((Value >> 4) & 0xF)) * 10 + (Value & 0xF));
201 case rTxAGC_A_Mcs03_Mcs00:
202 case rTxAGC_B_Mcs03_Mcs00:
203 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
204 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
205 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
206 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
207 for (i = 0; i < 4; ++i) {
208 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
209 ((Value >> (i * 8)) & 0xF));
214 case rTxAGC_A_Mcs07_Mcs04:
215 case rTxAGC_B_Mcs07_Mcs04:
216 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
217 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
218 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
219 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
220 for (i = 0; i < 4; ++i) {
221 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
222 ((Value >> (i * 8)) & 0xF));
227 case rTxAGC_B_CCK1_55_Mcs32:
228 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
229 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
230 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
231 for (i = 1; i < 4; ++i) {
232 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
233 ((Value >> (i * 8)) & 0xF));
242 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
243 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
244 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
245 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
246 for (i = 0; i < 4; ++i) {
247 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
248 ((Value >> (i * 8)) & 0xF));
257 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
258 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
259 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
260 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
261 for (i = 0; i < 4; ++i) {
262 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
263 ((Value >> (i * 8)) & 0xF));
272 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
273 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
274 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
275 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
276 for (i = 0; i < 4; ++i) {
277 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
278 ((Value >> (i * 8)) & 0xF));
287 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
288 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
289 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
290 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
291 for (i = 0; i < 4; ++i) {
292 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
293 ((Value >> (i * 8)) & 0xF));
302 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
303 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
304 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
305 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
306 for (i = 0; i < 4; ++i) {
307 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
308 ((Value >> (i * 8)) & 0xF));
318 static void PHY_StoreTxPowerByRateNew(struct adapter *padapter, u32 RfPath,
319 u32 RegAddr, u32 BitMask, u32 Data)
321 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
322 u8 i = 0, rateIndex[4] = {0}, rateNum = 0;
323 s8 PwrByRateVal[4] = {0};
325 PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum);
327 if (RfPath >= RF_PATH_MAX)
330 for (i = 0; i < rateNum; ++i) {
331 pHalData->TxPwrByRateOffset[RfPath][rateIndex[i]] = PwrByRateVal[i];
335 static void PHY_StoreTxPowerByRateOld(
336 struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data
339 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
340 u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(padapter, RegAddr, BitMask);
342 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data;
345 void PHY_InitTxPowerByRate(struct adapter *padapter)
347 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
350 for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath)
351 for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
352 pHalData->TxPwrByRateOffset[rfPath][rate] = 0;
355 void PHY_StoreTxPowerByRate(
356 struct adapter *padapter,
363 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
364 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
366 if (pDM_Odm->PhyRegPgVersion > 0)
367 PHY_StoreTxPowerByRateNew(padapter, RfPath, RegAddr, BitMask, Data);
368 else if (pDM_Odm->PhyRegPgVersion == 0) {
369 PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data);
374 phy_ConvertTxPowerByRateInDbmToRelativeValues(
375 struct adapter *padapter
378 u8 base = 0, i = 0, value = 0, path = 0;
380 MGN_1M, MGN_2M, MGN_5_5M, MGN_11M
383 MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M
385 u8 mcs0_7Rates[8] = {
386 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7
388 for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) {
390 base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
391 for (i = 0; i < ARRAY_SIZE(cckRates); ++i) {
392 value = PHY_GetTxPowerByRate(padapter, path, cckRates[i]);
393 PHY_SetTxPowerByRate(padapter, path, cckRates[i], value - base);
397 base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
398 for (i = 0; i < sizeof(ofdmRates); ++i) {
399 value = PHY_GetTxPowerByRate(padapter, path, ofdmRates[i]);
400 PHY_SetTxPowerByRate(padapter, path, ofdmRates[i], value - base);
404 base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
405 for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
406 value = PHY_GetTxPowerByRate(padapter, path, mcs0_7Rates[i]);
407 PHY_SetTxPowerByRate(padapter, path, mcs0_7Rates[i], value - base);
413 * This function must be called if the value in the PHY_REG_PG.txt(or header)
414 * is exact dBm values
416 void PHY_TxPowerByRateConfiguration(struct adapter *padapter)
418 phy_StoreTxPowerByRateBase(padapter);
419 phy_ConvertTxPowerByRateInDbmToRelativeValues(padapter);
422 void PHY_SetTxPowerIndexByRateSection(
423 struct adapter *padapter, u8 RFPath, u8 Channel, u8 RateSection
426 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
428 if (RateSection == CCK) {
429 u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
430 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
431 pHalData->CurrentChannelBW,
433 ARRAY_SIZE(cckRates));
435 } else if (RateSection == OFDM) {
436 u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
437 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
438 pHalData->CurrentChannelBW,
440 ARRAY_SIZE(ofdmRates));
442 } else if (RateSection == HT_MCS0_MCS7) {
443 u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
444 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
445 pHalData->CurrentChannelBW,
447 ARRAY_SIZE(htRates1T));
452 u8 PHY_GetTxPowerIndexBase(
453 struct adapter *padapter,
456 enum channel_width BandWidth,
460 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
462 u8 chnlIdx = (Channel-1);
464 if (HAL_IsLegalChannel(padapter, Channel) == false)
467 if (IS_CCK_RATE(Rate))
468 txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
469 else if (MGN_6M <= Rate)
470 txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
473 if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate))
474 txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S];
476 if (BandWidth == CHANNEL_WIDTH_20) { /* BW20-1S, BW20-2S */
477 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
478 txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S];
479 } else if (BandWidth == CHANNEL_WIDTH_40) { /* BW40-1S, BW40-2S */
480 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
481 txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
487 s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 RFPath, u8 Rate)
489 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
490 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
493 if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == false)
496 if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M))
497 offset = pDM_Odm->Remnant_CCKSwingIdx;
499 offset = pDM_Odm->Remnant_OFDMSwingIdx[RFPath];
504 u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate)
574 s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate)
576 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
578 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
580 if ((padapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) ||
581 padapter->registrypriv.RegEnableTxPowerByRate == 0)
584 if (RFPath >= RF_PATH_MAX)
587 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
590 return pHalData->TxPwrByRateOffset[RFPath][rateIndex];
594 void PHY_SetTxPowerByRate(
595 struct adapter *padapter,
601 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
602 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
604 if (RFPath >= RF_PATH_MAX)
607 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
610 pHalData->TxPwrByRateOffset[RFPath][rateIndex] = Value;
613 void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path)
615 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK);
617 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM);
618 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7);
621 void PHY_SetTxPowerIndexByRateArray(
622 struct adapter *padapter,
624 enum channel_width BandWidth,
633 for (i = 0; i < RateArraySize; ++i) {
634 powerIndex = PHY_GetTxPowerIndex(padapter, RFPath, Rates[i], BandWidth, Channel);
635 PHY_SetTxPowerIndex(padapter, powerIndex, RFPath, Rates[i]);
639 static s8 phy_GetWorldWideLimit(s8 *LimitTable)
641 s8 min = LimitTable[0];
644 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
645 if (LimitTable[i] < min)
652 static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Channel)
657 static s16 get_bandwidth_idx(const enum channel_width bandwidth)
660 case CHANNEL_WIDTH_20:
662 case CHANNEL_WIDTH_40:
669 static s16 get_rate_sctn_idx(const u8 rate)
672 case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M:
674 case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M:
675 case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M:
677 case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3:
678 case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7:
685 s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 reg_pwr_tbl_sel,
686 enum channel_width bandwidth,
687 u8 rf_path, u8 data_rate, u8 channel)
689 s16 idx_regulation = -1;
690 s16 idx_bandwidth = -1;
691 s16 idx_rate_sctn = -1;
692 s16 idx_channel = -1;
693 s8 pwr_lmt = MAX_POWER_INDEX;
694 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
695 s8 limits[10] = {0}; u8 i = 0;
697 if (((adapter->registrypriv.RegEnableTxPowerLimit == 2) &&
698 (hal_data->EEPROMRegulatory != 1)) ||
699 (adapter->registrypriv.RegEnableTxPowerLimit == 0))
700 return MAX_POWER_INDEX;
702 switch (adapter->registrypriv.RegPwrTblSel) {
704 idx_regulation = TXPWR_LMT_ETSI;
707 idx_regulation = TXPWR_LMT_MKK;
710 idx_regulation = TXPWR_LMT_FCC;
713 idx_regulation = TXPWR_LMT_WW;
716 idx_regulation = hal_data->Regulation2_4G;
720 idx_bandwidth = get_bandwidth_idx(bandwidth);
721 idx_rate_sctn = get_rate_sctn_idx(data_rate);
723 /* workaround for wrong index combination to obtain tx power limit, */
724 /* OFDM only exists in BW 20M */
725 /* CCK table will only be given in BW 20M */
726 /* HT on 80M will reference to HT on 40M */
727 if (idx_rate_sctn == 0 || idx_rate_sctn == 1)
730 channel = phy_GetChannelIndexOfTxPowerLimit(channel);
732 if (idx_regulation == -1 || idx_bandwidth == -1 ||
733 idx_rate_sctn == -1 || idx_channel == -1)
734 return MAX_POWER_INDEX;
737 for (i = 0; i < MAX_REGULATION_NUM; i++)
738 limits[i] = hal_data->TxPwrLimit_2_4G[i]
744 pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ?
745 phy_GetWorldWideLimit(limits) :
746 hal_data->TxPwrLimit_2_4G[idx_regulation]
755 void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter)
757 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
758 u8 BW40PwrBasedBm2_4G = 0x2E;
759 u8 regulation, bw, channel, rateSection;
760 s8 tempValue = 0, tempPwrLmt = 0;
763 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
764 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
765 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
766 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
767 tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A];
769 for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) {
770 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
771 if (rateSection == 2) /* HT 1T */
772 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, HT_MCS0_MCS7);
773 else if (rateSection == 1) /* OFDM */
774 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, OFDM);
775 else if (rateSection == 0) /* CCK */
776 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, CCK);
778 BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2;
780 if (tempPwrLmt != MAX_POWER_INDEX) {
781 tempValue = tempPwrLmt - BW40PwrBasedBm2_4G;
782 pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
791 void PHY_InitTxPowerLimit(struct adapter *Adapter)
793 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
796 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
797 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
798 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
799 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
800 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
801 pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
805 void PHY_SetTxPowerLimit(
806 struct adapter *Adapter,
815 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
816 u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
817 s8 powerLimit = 0, prevPowerLimit, channelIndex;
819 GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel);
820 GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit);
822 powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
824 if (eqNByte(Regulation, (u8 *)("FCC"), 3))
826 else if (eqNByte(Regulation, (u8 *)("MKK"), 3))
828 else if (eqNByte(Regulation, (u8 *)("ETSI"), 4))
830 else if (eqNByte(Regulation, (u8 *)("WW13"), 4))
833 if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
835 else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2))
837 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2))
842 if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
844 else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
847 channelIndex = phy_GetChannelIndexOfTxPowerLimit(channel);
849 if (channelIndex == -1)
852 prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A];
854 if (powerLimit < prevPowerLimit)
855 pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit;
858 void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan)
860 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
861 pHalData->Regulation2_4G = TXPWR_LMT_WW;
863 switch (ChannelPlan) {
864 case RT_CHANNEL_DOMAIN_WORLD_NULL:
865 pHalData->Regulation2_4G = TXPWR_LMT_WW;
867 case RT_CHANNEL_DOMAIN_ETSI1_NULL:
868 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
870 case RT_CHANNEL_DOMAIN_FCC1_NULL:
871 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
873 case RT_CHANNEL_DOMAIN_MKK1_NULL:
874 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
876 case RT_CHANNEL_DOMAIN_ETSI2_NULL:
877 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
879 case RT_CHANNEL_DOMAIN_FCC1_FCC1:
880 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
882 case RT_CHANNEL_DOMAIN_WORLD_ETSI1:
883 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
885 case RT_CHANNEL_DOMAIN_MKK1_MKK1:
886 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
888 case RT_CHANNEL_DOMAIN_WORLD_KCC1:
889 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
891 case RT_CHANNEL_DOMAIN_WORLD_FCC2:
892 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
894 case RT_CHANNEL_DOMAIN_WORLD_FCC3:
895 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
897 case RT_CHANNEL_DOMAIN_WORLD_FCC4:
898 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
900 case RT_CHANNEL_DOMAIN_WORLD_FCC5:
901 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
903 case RT_CHANNEL_DOMAIN_WORLD_FCC6:
904 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
906 case RT_CHANNEL_DOMAIN_FCC1_FCC7:
907 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
909 case RT_CHANNEL_DOMAIN_WORLD_ETSI2:
910 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
912 case RT_CHANNEL_DOMAIN_WORLD_ETSI3:
913 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
915 case RT_CHANNEL_DOMAIN_MKK1_MKK2:
916 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
918 case RT_CHANNEL_DOMAIN_MKK1_MKK3:
919 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
921 case RT_CHANNEL_DOMAIN_FCC1_NCC1:
922 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
924 case RT_CHANNEL_DOMAIN_FCC1_NCC2:
925 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
927 case RT_CHANNEL_DOMAIN_GLOBAL_NULL:
928 pHalData->Regulation2_4G = TXPWR_LMT_WW;
930 case RT_CHANNEL_DOMAIN_ETSI1_ETSI4:
931 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
933 case RT_CHANNEL_DOMAIN_FCC1_FCC2:
934 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
936 case RT_CHANNEL_DOMAIN_FCC1_NCC3:
937 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
939 case RT_CHANNEL_DOMAIN_WORLD_ETSI5:
940 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
942 case RT_CHANNEL_DOMAIN_FCC1_FCC8:
943 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
945 case RT_CHANNEL_DOMAIN_WORLD_ETSI6:
946 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
948 case RT_CHANNEL_DOMAIN_WORLD_ETSI7:
949 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
951 case RT_CHANNEL_DOMAIN_WORLD_ETSI8:
952 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
954 case RT_CHANNEL_DOMAIN_WORLD_ETSI9:
955 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
957 case RT_CHANNEL_DOMAIN_WORLD_ETSI10:
958 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
960 case RT_CHANNEL_DOMAIN_WORLD_ETSI11:
961 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
963 case RT_CHANNEL_DOMAIN_FCC1_NCC4:
964 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
966 case RT_CHANNEL_DOMAIN_WORLD_ETSI12:
967 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
969 case RT_CHANNEL_DOMAIN_FCC1_FCC9:
970 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
972 case RT_CHANNEL_DOMAIN_WORLD_ETSI13:
973 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
975 case RT_CHANNEL_DOMAIN_FCC1_FCC10:
976 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
978 case RT_CHANNEL_DOMAIN_REALTEK_DEFINE: /* Realtek Reserve */
979 pHalData->Regulation2_4G = TXPWR_LMT_WW;