1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
16 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
22 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
26 ---------- --------------- -------------------------------
27 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
28 2011-07-07 Roger Create.
31 #include <drv_types.h>
32 #include <rtw_debug.h>
33 #include <HalPwrSeqCmd.h>
38 /* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
41 /* We should follow specific format which was released from HW SD. */
43 /* 2011.07.07, added by Roger. */
45 u8 HalPwrSeqCmdParsing(
46 struct adapter *padapter,
50 WLAN_PWR_CFG PwrSeqCmd[]
53 WLAN_PWR_CFG PwrCfgCmd = {0};
54 u8 bPollingBit = false;
58 u32 pollingCount = 0; /* polling autoload done. */
59 u32 maxPollingCnt = 5000;
62 PwrCfgCmd = PwrSeqCmd[AryIdx];
68 "HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
69 GET_PWR_CFG_OFFSET(PwrCfgCmd),
70 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
71 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
72 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
73 GET_PWR_CFG_BASE(PwrCfgCmd),
74 GET_PWR_CFG_CMD(PwrCfgCmd),
75 GET_PWR_CFG_MASK(PwrCfgCmd),
76 GET_PWR_CFG_VALUE(PwrCfgCmd)
80 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
82 (GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
83 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
84 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)
86 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
91 ("HalPwrSeqCmdParsing: PWR_CMD_READ\n")
99 ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")
101 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
104 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
107 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
108 /* Read Back SDIO Local value */
109 value = SdioLocalCmd52Read1Byte(padapter, offset);
111 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
113 GET_PWR_CFG_VALUE(PwrCfgCmd) &
114 GET_PWR_CFG_MASK(PwrCfgCmd)
117 /* Write Back SDIO Local value */
118 SdioLocalCmd52Write1Byte(padapter, offset, value);
120 /* Read the value from system register */
121 value = rtw_read8(padapter, offset);
123 value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
125 GET_PWR_CFG_VALUE(PwrCfgCmd)
126 &GET_PWR_CFG_MASK(PwrCfgCmd)
129 /* Write the value back to sytem register */
130 rtw_write8(padapter, offset, value);
134 case PWR_CMD_POLLING:
138 ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")
142 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
144 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
145 value = SdioLocalCmd52Read1Byte(padapter, offset);
147 value = rtw_read8(padapter, offset);
149 value = value&GET_PWR_CFG_MASK(PwrCfgCmd);
151 value == (GET_PWR_CFG_VALUE(PwrCfgCmd) &
152 GET_PWR_CFG_MASK(PwrCfgCmd))
158 if (pollingCount++ > maxPollingCnt) {
160 "Fail to polling Offset[%#x]=%02x\n",
166 } while (!bPollingBit);
174 ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")
176 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
177 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
179 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
183 /* When this command is parsed, end the process */
187 ("HalPwrSeqCmdParsing: PWR_CMD_END\n")
195 ("HalPwrSeqCmdParsing: Unknown CMD!!\n")
201 AryIdx++;/* Add Array Index */