1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
8 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
14 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
18 ---------- --------------- -------------------------------
19 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
20 2011-07-07 Roger Create.
23 #include <drv_types.h>
24 #include <rtw_debug.h>
25 #include <HalPwrSeqCmd.h>
30 /* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
33 /* We should follow specific format which was released from HW SD. */
35 /* 2011.07.07, added by Roger. */
37 u8 HalPwrSeqCmdParsing(
38 struct adapter *padapter,
42 struct wlan_pwr_cfg PwrSeqCmd[]
45 struct wlan_pwr_cfg PwrCfgCmd;
46 u8 bPollingBit = false;
50 u32 pollingCount = 0; /* polling autoload done. */
51 u32 maxPollingCnt = 5000;
54 PwrCfgCmd = PwrSeqCmd[AryIdx];
56 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
58 (GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
59 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
60 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)
62 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
67 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
70 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
73 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
74 /* Read Back SDIO Local value */
75 value = SdioLocalCmd52Read1Byte(padapter, offset);
77 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
79 GET_PWR_CFG_VALUE(PwrCfgCmd) &
80 GET_PWR_CFG_MASK(PwrCfgCmd)
83 /* Write Back SDIO Local value */
84 SdioLocalCmd52Write1Byte(padapter, offset, value);
86 /* Read the value from system register */
87 value = rtw_read8(padapter, offset);
89 value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
91 GET_PWR_CFG_VALUE(PwrCfgCmd)
92 &GET_PWR_CFG_MASK(PwrCfgCmd)
95 /* Write the value back to system register */
96 rtw_write8(padapter, offset, value);
100 case PWR_CMD_POLLING:
103 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
105 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
106 value = SdioLocalCmd52Read1Byte(padapter, offset);
108 value = rtw_read8(padapter, offset);
110 value = value&GET_PWR_CFG_MASK(PwrCfgCmd);
112 value == (GET_PWR_CFG_VALUE(PwrCfgCmd) &
113 GET_PWR_CFG_MASK(PwrCfgCmd))
119 if (pollingCount++ > maxPollingCnt)
122 } while (!bPollingBit);
127 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
128 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
130 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
134 /* When this command is parsed, end the process */
142 AryIdx++;/* Add Array Index */