drivers/staging/rtl8723bs/core/rtw_odm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2013 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7
   8 #include <drv_types.h>
   9 #include <rtw_debug.h>
  10 #include <rtw_odm.h>
  11 #include <hal_data.h>
  12
  13 static const char * const odm_comp_str[] = {
  14         /* BIT0 */"ODM_COMP_DIG",
  15         /* BIT1 */"ODM_COMP_RA_MASK",
  16         /* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
  17         /* BIT3 */"ODM_COMP_FA_CNT",
  18         /* BIT4 */"ODM_COMP_RSSI_MONITOR",
  19         /* BIT5 */"ODM_COMP_CCK_PD",
  20         /* BIT6 */"ODM_COMP_ANT_DIV",
  21         /* BIT7 */"ODM_COMP_PWR_SAVE",
  22         /* BIT8 */"ODM_COMP_PWR_TRAIN",
  23         /* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
  24         /* BIT10 */"ODM_COMP_PATH_DIV",
  25         /* BIT11 */"ODM_COMP_PSD",
  26         /* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
  27         /* BIT13 */"ODM_COMP_RXHP",
  28         /* BIT14 */"ODM_COMP_MP",
  29         /* BIT15 */"ODM_COMP_DYNAMIC_ATC",
  30         /* BIT16 */"ODM_COMP_EDCA_TURBO",
  31         /* BIT17 */"ODM_COMP_EARLY_MODE",
  32         /* BIT18 */NULL,
  33         /* BIT19 */NULL,
  34         /* BIT20 */NULL,
  35         /* BIT21 */NULL,
  36         /* BIT22 */NULL,
  37         /* BIT23 */NULL,
  38         /* BIT24 */"ODM_COMP_TX_PWR_TRACK",
  39         /* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
  40         /* BIT26 */"ODM_COMP_CALIBRATION",
  41         /* BIT27 */NULL,
  42         /* BIT28 */NULL,
  43         /* BIT29 */NULL,
  44         /* BIT30 */"ODM_COMP_COMMON",
  45         /* BIT31 */"ODM_COMP_INIT",
  46 };
  47
  48 #define RTW_ODM_COMP_MAX 32
  49
  50 static const char * const odm_ability_str[] = {
  51         /* BIT0 */"ODM_BB_DIG",
  52         /* BIT1 */"ODM_BB_RA_MASK",
  53         /* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
  54         /* BIT3 */"ODM_BB_FA_CNT",
  55         /* BIT4 */"ODM_BB_RSSI_MONITOR",
  56         /* BIT5 */"ODM_BB_CCK_PD",
  57         /* BIT6 */"ODM_BB_ANT_DIV",
  58         /* BIT7 */"ODM_BB_PWR_SAVE",
  59         /* BIT8 */"ODM_BB_PWR_TRAIN",
  60         /* BIT9 */"ODM_BB_RATE_ADAPTIVE",
  61         /* BIT10 */"ODM_BB_PATH_DIV",
  62         /* BIT11 */"ODM_BB_PSD",
  63         /* BIT12 */"ODM_BB_RXHP",
  64         /* BIT13 */"ODM_BB_ADAPTIVITY",
  65         /* BIT14 */"ODM_BB_DYNAMIC_ATC",
  66         /* BIT15 */NULL,
  67         /* BIT16 */"ODM_MAC_EDCA_TURBO",
  68         /* BIT17 */"ODM_MAC_EARLY_MODE",
  69         /* BIT18 */NULL,
  70         /* BIT19 */NULL,
  71         /* BIT20 */NULL,
  72         /* BIT21 */NULL,
  73         /* BIT22 */NULL,
  74         /* BIT23 */NULL,
  75         /* BIT24 */"ODM_RF_TX_PWR_TRACK",
  76         /* BIT25 */"ODM_RF_RX_GAIN_TRACK",
  77         /* BIT26 */"ODM_RF_CALIBRATION",
  78 };
  79
  80 #define RTW_ODM_ABILITY_MAX 27
  81
  82 static const char * const odm_dbg_level_str[] = {
  83         NULL,
  84         "ODM_DBG_OFF",
  85         "ODM_DBG_SERIOUS",
  86         "ODM_DBG_WARNING",
  87         "ODM_DBG_LOUD",
  88         "ODM_DBG_TRACE",
  89 };
  90
  91 #define RTW_ODM_DBG_LEVEL_NUM 6
  92
  93 void rtw_odm_dbg_comp_msg(void *sel, struct adapter *adapter)
  94 {
  95         u64 dbg_comp;
  96         int i;
  97
  98         rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
  99         DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
 100         for (i = 0; i < RTW_ODM_COMP_MAX; i++) {
 101                 if (odm_comp_str[i])
 102                         DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
 103                                         (BIT0 << i) & dbg_comp ? '+' : ' ',
 104                                         i, odm_comp_str[i]);
 105         }
 106 }
 107
 108 inline void rtw_odm_dbg_comp_set(struct adapter *adapter, u64 comps)
 109 {
 110         rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
 111 }
 112
 113 void rtw_odm_dbg_level_msg(void *sel, struct adapter *adapter)
 114 {
 115         u32 dbg_level;
 116         int i;
 117
 118         rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
 119         DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
 120         for (i = 0; i < RTW_ODM_DBG_LEVEL_NUM; i++) {
 121                 if (odm_dbg_level_str[i])
 122                         DBG_871X_SEL_NL(sel, "%u %s\n",
 123                                         i, odm_dbg_level_str[i]);
 124         }
 125 }
 126
 127 inline void rtw_odm_dbg_level_set(struct adapter *adapter, u32 level)
 128 {
 129         rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
 130 }
 131
 132 void rtw_odm_ability_msg(void *sel, struct adapter *adapter)
 133 {
 134         u32 ability = 0;
 135         int i;
 136
 137         rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8 *)&ability);
 138         DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
 139         for (i = 0; i < RTW_ODM_ABILITY_MAX; i++) {
 140                 if (odm_ability_str[i])
 141                         DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
 142                                         (BIT0 << i) & ability ? '+' : ' ', i,
 143                                         odm_ability_str[i]);
 144         }
 145 }
 146
 147 inline void rtw_odm_ability_set(struct adapter *adapter, u32 ability)
 148 {
 149         rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8 *)&ability);
 150 }
 151
 152 void rtw_odm_adaptivity_parm_msg(void *sel, struct adapter *adapter)
 153 {
 154         struct hal_com_data *pHalData = GET_HAL_DATA(adapter);
 155         DM_ODM_T *odm = &pHalData->odmpriv;
 156
 157         DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n",
 158                         "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base",
 159                         "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
 160         DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n",
 161                         (u8)odm->TH_L2H_ini,
 162                         odm->TH_EDCCA_HL_diff,
 163                         odm->IGI_Base,
 164                         odm->ForceEDCCA,
 165                         odm->AdapEn_RSSI,
 166                         odm->IGI_LowerBound
 167         );
 168 }
 169
 170 void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini,
 171                                  s8 TH_EDCCA_HL_diff, s8 IGI_Base,
 172                                  bool ForceEDCCA, u8 AdapEn_RSSI,
 173                                  u8 IGI_LowerBound)
 174 {
 175         struct hal_com_data *pHalData = GET_HAL_DATA(adapter);
 176         DM_ODM_T *odm = &pHalData->odmpriv;
 177
 178         odm->TH_L2H_ini = TH_L2H_ini;
 179         odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
 180         odm->IGI_Base = IGI_Base;
 181         odm->ForceEDCCA = ForceEDCCA;
 182         odm->AdapEn_RSSI = AdapEn_RSSI;
 183         odm->IGI_LowerBound = IGI_LowerBound;
 184 }
 185
 186 void rtw_odm_get_perpkt_rssi(void *sel, struct adapter *adapter)
 187 {
 188         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
 189         DM_ODM_T *odm = &hal_data->odmpriv;
 190
 191         DBG_871X_SEL_NL(sel, "RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
 192                         HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
 193 }