1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
17 #ifndef __HALHWOUTSRC_H__
18 #define __HALHWOUTSRC_H__
20 #include <Hal8723APhyCfg.h>
27 /* CCK Rates, TxHT = 0 */
28 #define DESC92C_RATE1M 0x00
29 #define DESC92C_RATE2M 0x01
30 #define DESC92C_RATE5_5M 0x02
31 #define DESC92C_RATE11M 0x03
33 /* OFDM Rates, TxHT = 0 */
34 #define DESC92C_RATE6M 0x04
35 #define DESC92C_RATE9M 0x05
36 #define DESC92C_RATE12M 0x06
37 #define DESC92C_RATE18M 0x07
38 #define DESC92C_RATE24M 0x08
39 #define DESC92C_RATE36M 0x09
40 #define DESC92C_RATE48M 0x0a
41 #define DESC92C_RATE54M 0x0b
43 /* MCS Rates, TxHT = 1 */
44 #define DESC92C_RATEMCS0 0x0c
45 #define DESC92C_RATEMCS1 0x0d
46 #define DESC92C_RATEMCS2 0x0e
47 #define DESC92C_RATEMCS3 0x0f
48 #define DESC92C_RATEMCS4 0x10
49 #define DESC92C_RATEMCS5 0x11
50 #define DESC92C_RATEMCS6 0x12
51 #define DESC92C_RATEMCS7 0x13
52 #define DESC92C_RATEMCS8 0x14
53 #define DESC92C_RATEMCS9 0x15
54 #define DESC92C_RATEMCS10 0x16
55 #define DESC92C_RATEMCS11 0x17
56 #define DESC92C_RATEMCS12 0x18
57 #define DESC92C_RATEMCS13 0x19
58 #define DESC92C_RATEMCS14 0x1a
59 #define DESC92C_RATEMCS15 0x1b
60 #define DESC92C_RATEMCS15_SG 0x1c
61 #define DESC92C_RATEMCS32 0x20
65 /* structure and define */
68 struct phy_rx_agc_info {
69 #ifdef __LITTLE_ENDIAN
76 struct phy_status_rpt {
77 struct phy_rx_agc_info path_agc[RF_PATH_MAX];
78 u8 ch_corr[RF_PATH_MAX];
79 u8 cck_sig_qual_ofdm_pwdb_all;
80 u8 cck_agc_rpt_ofdm_cfosho_a;
81 u8 cck_rpt_b_ofdm_cfosho_b;
82 u8 rsvd_1;/* ch_corr_msb; */
83 u8 noise_power_db_msb;
84 u8 path_cfotail[RF_PATH_MAX];
85 u8 pcts_mask[RF_PATH_MAX];
86 s8 stream_rxevm[RF_PATH_MAX];
87 u8 path_rxsnr[RF_PATH_MAX];
88 u8 noise_power_db_lsb;
90 u8 stream_csi[RF_PATH_MAX];
91 u8 stream_target_csi[RF_PATH_MAX];
95 #ifdef __LITTLE_ENDIAN
96 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
103 #else /* _BIG_ENDIAN_ */
110 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
115 struct phy_status_rpt_8195 {
116 struct phy_rx_agc_info path_agc[2];
118 u8 cck_sig_qual_ofdm_pwdb_all;
119 u8 cck_agc_rpt_ofdm_cfosho_a;
120 u8 cck_bb_pwr_ofdm_cfosho_b;
121 u8 cck_rx_path; /* CCK_RX_PATH [3:0] (with regA07[3:0] definition) */
133 #ifdef __LITTLE_ENDIAN
137 #else /* _BIG_ENDIAN_ */
145 void odm_Init_RSSIForDM23a(struct dm_odm_t *pDM_Odm);
148 ODM_PhyStatusQuery23a(
149 struct dm_odm_t *pDM_Odm,
150 struct phy_info *pPhyInfo,
152 struct odm_packet_info *pPktinfo