1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
15 /******************************************************************************
18 * Module: rtl8192c_rf6052.c (Source C File)
20 * Note: Provide RF 6052 series relative API.
31 * 09/25/2008 MHC Create initial version.
32 * 11/05/2008 MHC Add API for tw power setting.
35 ******************************************************************************/
37 #define _RTL8723A_RF6052_C_
39 #include <osdep_service.h>
40 #include <drv_types.h>
42 #include <rtl8723a_hal.h>
43 #include <usb_ops_linux.h>
45 /*-----------------------------------------------------------------------------
46 * Function: PHY_RF6052SetBandwidth()
48 * Overview: This function is called by SetBWMode23aCallback8190Pci() only
50 * Input: struct rtw_adapter * Adapter
51 * WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
57 * Note: For RF type 0222D
58 *---------------------------------------------------------------------------*/
59 void rtl8723a_phy_rf6052set_bw(struct rtw_adapter *Adapter,
60 enum ht_channel_width Bandwidth) /* 20M or 40M */
62 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
65 case HT_CHANNEL_WIDTH_20:
66 pHalData->RfRegChnlVal[0] =
67 (pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400;
68 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
69 pHalData->RfRegChnlVal[0]);
71 case HT_CHANNEL_WIDTH_40:
72 pHalData->RfRegChnlVal[0] =
73 (pHalData->RfRegChnlVal[0] & 0xfffff3ff);
74 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
75 pHalData->RfRegChnlVal[0]);
82 /*-----------------------------------------------------------------------------
83 * Function: PHY_RF6052SetCckTxPower
95 * 11/05/2008 MHC Simulate 8192series..
97 *---------------------------------------------------------------------------*/
99 void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter,
102 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
103 struct dm_priv *pdmpriv = &pHalData->dmpriv;
104 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
105 u32 TxAGC[2] = {0, 0}, tmpval = 0;
109 if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
110 TxAGC[RF_PATH_A] = 0x3f3f3f3f;
111 TxAGC[RF_PATH_B] = 0x3f3f3f3f;
113 for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
114 TxAGC[idx1] = pPowerlevel[idx1] |
115 (pPowerlevel[idx1] << 8) |
116 (pPowerlevel[idx1] << 16) |
117 (pPowerlevel[idx1] << 24);
119 * 2010/10/18 MH For external PA module. We need
120 * to limit power index to be less than 0x20.
122 if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
126 /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx
127 * power. It shall be determined by power training mechanism. */
128 /* Currently, we cannot fully disable driver dynamic tx power
129 * mechanism because it is referenced by BT coexist mechanism. */
130 /* In the future, two mechanism shall be separated from each other
131 * and maintained independently. Thanks for Lanhsin's reminder. */
132 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
133 TxAGC[RF_PATH_A] = 0x10101010;
134 TxAGC[RF_PATH_B] = 0x10101010;
135 } else if (pdmpriv->DynamicTxHighPowerLvl ==
136 TxHighPwrLevel_Level2) {
137 TxAGC[RF_PATH_A] = 0x00000000;
138 TxAGC[RF_PATH_B] = 0x00000000;
140 for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
141 TxAGC[idx1] = pPowerlevel[idx1] |
142 (pPowerlevel[idx1] << 8) |
143 (pPowerlevel[idx1] << 16) |
144 (pPowerlevel[idx1] << 24);
147 if (pHalData->EEPROMRegulatory == 0) {
148 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
149 (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
150 TxAGC[RF_PATH_A] += tmpval;
152 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
153 (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
154 TxAGC[RF_PATH_B] += tmpval;
159 for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
160 ptr = (u8 *)(&TxAGC[idx1]);
161 for (idx2 = 0; idx2 < 4; idx2++) {
162 if (*ptr > RF6052_MAX_TX_PWR)
163 *ptr = RF6052_MAX_TX_PWR;
168 /* rf-A cck tx power */
169 tmpval = TxAGC[RF_PATH_A] & 0xff;
170 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
171 tmpval = TxAGC[RF_PATH_A] >> 8;
172 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
174 /* rf-B cck tx power */
175 tmpval = TxAGC[RF_PATH_B] >> 24;
176 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
177 tmpval = TxAGC[RF_PATH_B] & 0x00ffffff;
178 PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
179 } /* PHY_RF6052SetCckTxPower */
181 /* powerbase0 for OFDM rates */
182 /* powerbase1 for HT MCS rates */
183 static void getPowerBase(struct rtw_adapter *Adapter, u8 *pPowerLevel,
184 u8 Channel, u32 *OfdmBase, u32 *MCSBase)
186 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
188 u8 Legacy_pwrdiff = 0;
192 for (i = 0; i < 2; i++) {
193 powerlevel[i] = pPowerLevel[i];
194 Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
195 ofdm = powerlevel[i] + Legacy_pwrdiff;
197 ofdm = ofdm << 24 | ofdm << 16 | ofdm << 8 | ofdm;
198 *(OfdmBase + i) = ofdm;
201 for (i = 0; i < 2; i++) {
202 /* Check HT20 to HT40 diff */
203 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) {
204 HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
205 powerlevel[i] += HT20_pwrdiff;
208 mcs = mcs << 24 | mcs << 16 | mcs << 8 | mcs;
209 *(MCSBase + i) = mcs;
214 getTxPowerWriteValByRegulatory(struct rtw_adapter *Adapter, u8 Channel,
215 u8 index, u32 *powerBase0, u32 *powerBase1,
218 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
219 struct dm_priv *pdmpriv = &pHalData->dmpriv;
220 u8 i, chnlGroup = 0, pwr_diff_limit[4];
221 u32 writeVal, customer_limit, rf;
223 /* Index 0 & 1 = legacy OFDM, 2-5 = HT_MCS rate */
224 for (rf = 0; rf < 2; rf++) {
225 switch (pHalData->EEPROMRegulatory) {
226 case 0: /* Realtek better performance */
227 /* increase power diff defined by Realtek for
230 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
231 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
233 case 1: /* Realtek regulatory */
234 /* increase power diff defined by Realtek for
236 if (pHalData->pwrGroupCnt == 1)
238 if (pHalData->pwrGroupCnt >= 3) {
241 else if (Channel >= 4 && Channel <= 9)
243 else if (Channel > 9)
246 if (pHalData->CurrentChannelBW ==
252 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
253 ((index < 2) ? powerBase0[rf] :
256 case 2: /* Better regulatory */
257 /* don't increase any power diff */
258 writeVal = (index < 2) ? powerBase0[rf] :
261 case 3: /* Customer defined power diff. */
264 for (i = 0; i < 4; i++) {
265 pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index +
266 (rf ? 8 : 0)]&(0x7f << (i*8))) >> (i*8));
267 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
268 if (pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
269 pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
271 if (pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
272 pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
275 customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
276 (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
277 writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
281 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
282 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
286 /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power.
287 It shall be determined by power training mechanism. */
288 /* Currently, we cannot fully disable driver dynamic tx power mechanism
289 because it is referenced by BT coexist mechanism. */
290 /* In the future, two mechanism shall be separated from each other and
291 maintained independently. Thanks for Lanhsin's reminder. */
293 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
294 writeVal = 0x14141414;
295 else if (pdmpriv->DynamicTxHighPowerLvl ==
296 TxHighPwrLevel_Level2)
297 writeVal = 0x00000000;
299 /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
300 /* This mechanism is only applied when
301 Driver-Highpower-Mechanism is OFF. */
302 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
303 writeVal = writeVal - 0x06060606;
304 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
306 *(pOutWriteVal + rf) = writeVal;
310 static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index,
313 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
314 u16 RegOffset_A[6] = {
315 rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
316 rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
317 rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12
319 u16 RegOffset_B[6] = {
320 rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
321 rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
322 rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12
324 u8 i, rf, pwr_val[4];
328 for (rf = 0; rf < 2; rf++) {
329 writeVal = pValue[rf];
330 for (i = 0; i < 4; i++) {
331 pwr_val[i] = (u8)((writeVal &
332 (0x7f << (i * 8))) >> (i * 8));
333 if (pwr_val[i] > RF6052_MAX_TX_PWR)
334 pwr_val[i] = RF6052_MAX_TX_PWR;
336 writeVal = pwr_val[3] << 24 | pwr_val[2] << 16 |
337 pwr_val[1] << 8 | pwr_val[0];
340 RegOffset = RegOffset_A[index];
342 RegOffset = RegOffset_B[index];
344 rtl8723au_write32(Adapter, RegOffset, writeVal);
346 /* 201005115 Joseph: Set Tx Power diff for Tx power
347 training mechanism. */
348 if (((pHalData->rf_type == RF_2T2R) &&
349 (RegOffset == rTxAGC_A_Mcs15_Mcs12 ||
350 RegOffset == rTxAGC_B_Mcs15_Mcs12)) ||
351 ((pHalData->rf_type != RF_2T2R) &&
352 (RegOffset == rTxAGC_A_Mcs07_Mcs04 ||
353 RegOffset == rTxAGC_B_Mcs07_Mcs04))) {
354 writeVal = pwr_val[3];
355 if (RegOffset == rTxAGC_A_Mcs15_Mcs12 ||
356 RegOffset == rTxAGC_A_Mcs07_Mcs04)
358 if (RegOffset == rTxAGC_B_Mcs15_Mcs12 ||
359 RegOffset == rTxAGC_B_Mcs07_Mcs04)
361 for (i = 0; i < 3; i++) {
363 writeVal = (writeVal > 8) ?
366 writeVal = (writeVal > 6) ?
368 rtl8723au_write8(Adapter, RegOffset + i,
374 /*-----------------------------------------------------------------------------
375 * Function: PHY_RF6052SetOFDMTxPower
377 * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
378 * different channel and read original value in TX power
379 * register area from 0xe00. We increase offset and
380 * original value to be correct tx pwr.
390 * 11/05/2008 MHC Simulate 8192 series method.
391 * 01/06/2009 MHC 1. Prevent Path B tx power overflow or
392 * underflow dure to A/B pwr difference or
393 * legacy/HT pwr diff.
394 * 2. We concern with path B legacy/HT OFDM difference.
395 * 01/22/2009 MHC Support new EPRO format from SD3.
397 *---------------------------------------------------------------------------*/
398 void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter,
399 u8 *pPowerLevel, u8 Channel)
401 u32 writeVal[2], powerBase0[2], powerBase1[2];
404 getPowerBase(Adapter, pPowerLevel, Channel,
405 &powerBase0[0], &powerBase1[0]);
407 for (index = 0; index < 6; index++) {
408 getTxPowerWriteValByRegulatory(Adapter, Channel, index,
409 &powerBase0[0], &powerBase1[0], &writeVal[0]);
411 writeOFDMPowerReg(Adapter, index, &writeVal[0]);
415 static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
419 struct bb_reg_define *pPhyReg;
420 int rtStatus = _SUCCESS;
421 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
423 /* 3----------------------------------------------------------------- */
424 /* 3 <2> Initialize RF */
425 /* 3----------------------------------------------------------------- */
426 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
428 pPhyReg = &pHalData->PHYRegDef[eRFPath];
430 /*----Store original RFENV control type----*/
433 u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs,
437 u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs,
442 /*----Set RF_ENV enable----*/
443 PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
444 udelay(1);/* PlatformStallExecution(1); */
446 /*----Set RF_ENV output high----*/
447 PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
448 udelay(1);/* PlatformStallExecution(1); */
450 /* Set bit number of Address and Data for RF register */
451 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength,
452 0x0); /* Set 1 to 4 bits for 8255 */
453 udelay(1);/* PlatformStallExecution(1); */
455 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength,
456 0x0); /* Set 0 to 12 bits for 8255 */
457 udelay(1);/* PlatformStallExecution(1); */
459 /*----Initialize RF fom connfiguration file----*/
462 ODM_ReadAndConfig_RadioA_1T_8723A(&pHalData->odmpriv);
468 /*----Restore RFENV control type----*/;
471 PHY_SetBBReg(Adapter, pPhyReg->rfintfs,
472 bRFSI_RFENV, u4RegValue);
475 PHY_SetBBReg(Adapter, pPhyReg->rfintfs,
476 bRFSI_RFENV << 16, u4RegValue);
480 if (rtStatus != _SUCCESS) {
481 goto phy_RF6052_Config_ParaFile_Fail;
484 phy_RF6052_Config_ParaFile_Fail:
488 int PHY_RF6052_Config8723A(struct rtw_adapter *Adapter)
490 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
492 /* Initialize general global value */
493 /* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
494 if (pHalData->rf_type == RF_1T1R)
495 pHalData->NumTotalRFPath = 1;
497 pHalData->NumTotalRFPath = 2;
499 /* Config BB and RF */
500 return phy_RF6052_Config_ParaFile(Adapter);
503 /* End of HalRf6052.c */