1 /******************************************************************************
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
17 #include <linux/firmware.h>
18 #include <drv_types.h>
19 #include <rtw_efuse.h>
21 #include <rtl8723a_hal.h>
22 #include <usb_ops_linux.h>
24 static void _FWDownloadEnable(struct rtw_adapter *padapter, bool enable)
30 tmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
31 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
33 /* MCU firmware download enable. */
34 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
35 rtl8723au_write8(padapter, REG_MCUFWDL, tmp | 0x01);
38 tmp = rtl8723au_read8(padapter, REG_MCUFWDL + 2);
39 rtl8723au_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
41 /* MCU firmware download disable. */
42 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
43 rtl8723au_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
45 /* Reserved for fw extension. */
46 rtl8723au_write8(padapter, REG_MCUFWDL + 1, 0x00);
51 _PageWrite(struct rtw_adapter *padapter, u32 page, void *buffer, u32 size)
54 u8 u8Page = (u8) (page & 0x07);
56 if (size > MAX_PAGE_SIZE)
59 value8 = (rtl8723au_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
60 rtl8723au_write8(padapter, REG_MCUFWDL + 2, value8);
62 return rtl8723au_writeN(padapter, FW_8723A_START_ADDRESS, size, buffer);
65 static int _WriteFW(struct rtw_adapter *padapter, void *buffer, u32 size)
67 /* Since we need dynamic decide method of dwonload fw, so we
68 call this function to get chip version. */
69 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
71 u32 pageNums, remainSize;
73 u8 *bufferPtr = (u8 *) buffer;
75 pageNums = size / MAX_PAGE_SIZE;
76 /* RT_ASSERT((pageNums <= 4),
77 ("Page numbers should not greater then 4 \n")); */
78 remainSize = size % MAX_PAGE_SIZE;
80 for (page = 0; page < pageNums; page++) {
81 offset = page * MAX_PAGE_SIZE;
82 ret = _PageWrite(padapter, page, bufferPtr + offset,
89 offset = pageNums * MAX_PAGE_SIZE;
91 ret = _PageWrite(padapter, page, bufferPtr + offset,
97 RT_TRACE(_module_hal_init_c_, _drv_info_,
98 "_WriteFW Done- for Normal chip.\n");
104 static int _FWFreeToGo(struct rtw_adapter *padapter)
109 /* polling CheckSum report */
111 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
112 if (value32 & FWDL_ChkSum_rpt)
114 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
116 if (counter >= POLLING_READY_TIMEOUT_COUNT) {
117 RT_TRACE(_module_hal_init_c_, _drv_err_,
118 "%s: chksum report fail! REG_MCUFWDL:0x%08x\n",
122 RT_TRACE(_module_hal_init_c_, _drv_info_,
123 "%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__,
126 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
127 value32 |= MCUFWDL_RDY;
128 value32 &= ~WINTINI_RDY;
129 rtl8723au_write32(padapter, REG_MCUFWDL, value32);
131 /* polling for FW ready */
134 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
135 if (value32 & WINTINI_RDY) {
136 RT_TRACE(_module_hal_init_c_, _drv_info_,
137 "%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n",
142 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
144 RT_TRACE(_module_hal_init_c_, _drv_err_,
145 "%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
150 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
152 void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter)
154 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
158 if (!(IS_FW_81xxC(padapter) &&
159 ((pHalData->FirmwareVersion < 0x21) ||
160 (pHalData->FirmwareVersion == 0x21 &&
161 pHalData->FirmwareSubVersion < 0x01)))) {
162 /* after 88C Fw v33.1 */
163 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
164 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
166 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
167 while (u1bTmp & BIT(2)) {
172 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
174 RT_TRACE(_module_hal_init_c_, _drv_info_,
175 "-%s: 8051 reset success (%d)\n", __func__,
179 /* force firmware reset */
180 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
181 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1,
189 /* Download 8192C firmware code. */
192 int rtl8723a_FirmwareDownload(struct rtw_adapter *padapter)
194 int rtStatus = _SUCCESS;
195 u8 writeFW_retry = 0;
196 unsigned long fwdl_start_time;
197 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
198 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
199 struct device *device = dvobj_to_dev(dvobj);
200 struct rt_8723a_firmware_hdr *pFwHdr = NULL;
201 const struct firmware *fw;
203 u8 *firmware_buf = NULL;
206 static int log_version;
208 RT_TRACE(_module_hal_init_c_, _drv_info_, "+%s\n", __func__);
210 if (IS_8723A_A_CUT(pHalData->VersionID)) {
211 fw_name = "/*(DEBLOBBED)*/";
212 RT_TRACE(_module_hal_init_c_, _drv_info_,
213 "rtl8723a_FirmwareDownload: R8723FwImageArray_UMC for RTL8723A A CUT\n");
214 } else if (IS_8723A_B_CUT(pHalData->VersionID)) {
216 if (padapter->registrypriv.wifi_spec == 1) {
217 fw_name = "/*(DEBLOBBED)*/";
218 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithoutBT for "
221 if (rtl8723a_BT_coexist(padapter)) {
222 fw_name = "/*(DEBLOBBED)*/";
223 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithBT "
224 "for RTL8723A B CUT\n");
226 fw_name = "/*(DEBLOBBED)*/";
227 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithout "
228 "BT for RTL8723A B CUT\n");
232 /* <Roger_TODO> We should download proper RAM Code here
233 to match the ROM code. */
234 RT_TRACE(_module_hal_init_c_, _drv_err_,
235 "%s: unknown version!\n", __func__);
240 pr_info("rtl8723au: Loading firmware %s\n", fw_name);
241 if (reject_firmware(&fw, fw_name, device)) {
242 pr_err("rtl8723au: request_firmware load failed\n");
247 pr_err("rtl8723au: Firmware %s not available\n", fw_name);
251 firmware_buf = kmemdup(fw->data, fw->size, GFP_KERNEL);
253 release_firmware(fw);
260 /* To Check Fw header. Added by tynli. 2009.12.04. */
261 pFwHdr = (struct rt_8723a_firmware_hdr *)firmware_buf;
263 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
264 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
265 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
267 DBG_8723A("%s: fw_ver =%d fw_subver =%d sig = 0x%x\n",
268 __func__, pHalData->FirmwareVersion,
269 pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
272 pr_info("%sFirmware Version %d, SubVersion %d, Signature "
273 "0x%x\n", DRIVER_PREFIX, pHalData->FirmwareVersion,
274 pHalData->FirmwareSubVersion,
275 pHalData->FirmwareSignature);
277 if (IS_FW_HEADER_EXIST(pFwHdr)) {
278 /* Shift 32 bytes for FW header */
280 fw_size = fw_size - 32;
283 /* Suggested by Filen. If 8051 is running in RAM code, driver should
284 inform Fw to reset by itself, */
285 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
286 if (rtl8723au_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
288 rtl8723a_FirmwareSelfReset(padapter);
289 rtl8723au_write8(padapter, REG_MCUFWDL, 0x00);
292 _FWDownloadEnable(padapter, true);
293 fwdl_start_time = jiffies;
295 /* reset the FWDL chksum */
296 rtl8723au_write8(padapter, REG_MCUFWDL,
297 rtl8723au_read8(padapter, REG_MCUFWDL) |
300 rtStatus = _WriteFW(padapter, buf, fw_size);
302 if (rtStatus == _SUCCESS ||
303 (jiffies_to_msecs(jiffies - fwdl_start_time) > 500 &&
304 writeFW_retry++ >= 3))
307 DBG_8723A("%s writeFW_retry:%u, time after fwdl_start_time:"
308 "%ums\n", __func__, writeFW_retry,
309 jiffies_to_msecs(jiffies - fwdl_start_time));
311 _FWDownloadEnable(padapter, false);
312 if (_SUCCESS != rtStatus) {
313 DBG_8723A("DL Firmware failed!\n");
317 rtStatus = _FWFreeToGo(padapter);
318 if (_SUCCESS != rtStatus) {
319 RT_TRACE(_module_hal_init_c_, _drv_err_,
320 "DL Firmware failed!\n");
323 RT_TRACE(_module_hal_init_c_, _drv_info_,
324 "Firmware is ready to run!\n");
331 void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter)
333 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
335 /* Init Fw LPS related. */
336 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
338 /* Init H2C counter. by tynli. 2009.12.09. */
339 pHalData->LastHMEBoxNum = 0;
343 /* Efuse related code */
346 hal_EfuseSwitchToBank(struct rtw_adapter *padapter, u8 bank)
351 DBG_8723A("%s: Efuse switch bank to %d\n", __func__, bank);
352 value32 = rtl8723au_read32(padapter, EFUSE_TEST);
356 value32 = (value32 & ~EFUSE_SEL_MASK) |
357 EFUSE_SEL(EFUSE_WIFI_SEL_0);
360 value32 = (value32 & ~EFUSE_SEL_MASK) |
361 EFUSE_SEL(EFUSE_BT_SEL_0);
364 value32 = (value32 & ~EFUSE_SEL_MASK) |
365 EFUSE_SEL(EFUSE_BT_SEL_1);
368 value32 = (value32 & ~EFUSE_SEL_MASK) |
369 EFUSE_SEL(EFUSE_BT_SEL_2);
372 value32 = (value32 & ~EFUSE_SEL_MASK) |
373 EFUSE_SEL(EFUSE_WIFI_SEL_0);
377 rtl8723au_write32(padapter, EFUSE_TEST, value32);
383 hal_ReadEFuse_WiFi(struct rtw_adapter *padapter,
384 u16 _offset, u16 _size_byte, u8 *pbuf)
389 u8 efuseHeader, efuseExtHdr, efuseData;
391 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
393 /* Do NOT excess total size of EFuse table.
394 Added by Roger, 2008.11.10. */
395 if ((_offset + _size_byte) > EFUSE_MAP_LEN_8723A) {
396 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
397 __func__, _offset, _size_byte);
401 efuseTbl = kmalloc(EFUSE_MAP_LEN_8723A, GFP_KERNEL);
402 if (efuseTbl == NULL) {
403 DBG_8723A("%s: alloc efuseTbl fail!\n", __func__);
406 /* 0xff will be efuse default value instead of 0x00. */
407 memset(efuseTbl, 0xFF, EFUSE_MAP_LEN_8723A);
409 /* switch bank back to bank 0 for later BT and wifi use. */
410 hal_EfuseSwitchToBank(padapter, 0);
412 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
413 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
414 if (efuseHeader == 0xFF) {
415 DBG_8723A("%s: data end at address =%#x\n", __func__,
420 /* Check PG header for section num. */
421 if (EXT_HEADER(efuseHeader)) { /* extended header */
422 offset = GET_HDR_OFFSET_2_0(efuseHeader);
424 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseExtHdr);
425 if (ALL_WORDS_DISABLED(efuseExtHdr))
428 offset |= ((efuseExtHdr & 0xF0) >> 1);
429 wden = efuseExtHdr & 0x0F;
431 offset = (efuseHeader >> 4) & 0x0f;
432 wden = efuseHeader & 0x0f;
435 if (offset < EFUSE_MAX_SECTION_8723A) {
437 /* Get word enable value from PG header */
439 addr = offset * PGPKT_DATA_SIZE;
440 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
441 /* Check word enable condition in the section */
442 if (!(wden & (0x01 << i))) {
443 ReadEFuseByte23a(padapter, eFuse_Addr++,
445 efuseTbl[addr] = efuseData;
447 ReadEFuseByte23a(padapter, eFuse_Addr++,
449 efuseTbl[addr + 1] = efuseData;
454 DBG_8723A(KERN_ERR "%s: offset(%d) is illegal!!\n",
456 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
460 /* Copy from Efuse map to output pointer memory!!! */
461 for (i = 0; i < _size_byte; i++)
462 pbuf[i] = efuseTbl[_offset + i];
464 /* Calculate Efuse utilization */
465 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
466 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
467 used = eFuse_Addr - 1;
468 pHalData->EfuseUsedBytes = used;
474 hal_ReadEFuse_BT(struct rtw_adapter *padapter,
475 u16 _offset, u16 _size_byte, u8 *pbuf)
480 u8 efuseHeader, efuseExtHdr, efuseData;
483 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
485 /* Do NOT excess total size of EFuse table.
486 Added by Roger, 2008.11.10. */
487 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
488 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
489 __func__, _offset, _size_byte);
493 efuseTbl = kmalloc(EFUSE_BT_MAP_LEN, GFP_KERNEL);
494 if (efuseTbl == NULL) {
495 DBG_8723A("%s: efuseTbl malloc fail!\n", __func__);
498 /* 0xff will be efuse default value instead of 0x00. */
499 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
501 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
502 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total);
504 for (bank = 1; bank < EFUSE_MAX_BANK; bank++) {
505 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
506 DBG_8723A("%s: hal_EfuseSwitchToBank Fail!!\n",
513 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
514 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
515 if (efuseHeader == 0xFF)
518 /* Check PG header for section num. */
519 if (EXT_HEADER(efuseHeader)) { /* extended header */
520 offset = GET_HDR_OFFSET_2_0(efuseHeader);
522 ReadEFuseByte23a(padapter, eFuse_Addr++,
524 if (ALL_WORDS_DISABLED(efuseExtHdr))
527 offset |= ((efuseExtHdr & 0xF0) >> 1);
528 wden = efuseExtHdr & 0x0F;
530 offset = (efuseHeader >> 4) & 0x0f;
531 wden = efuseHeader & 0x0f;
534 if (offset < EFUSE_BT_MAX_SECTION) {
537 /* Get word enable value from PG header */
539 addr = offset * PGPKT_DATA_SIZE;
540 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
541 /* Check word enable condition in
543 if (!(wden & (0x01 << i))) {
544 ReadEFuseByte23a(padapter,
547 efuseTbl[addr] = efuseData;
549 ReadEFuseByte23a(padapter,
552 efuseTbl[addr + 1] = efuseData;
558 "%s: offset(%d) is illegal!!\n",
560 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
564 if ((eFuse_Addr - 1) < total) {
565 DBG_8723A("%s: bank(%d) data end at %#x\n",
566 __func__, bank, eFuse_Addr - 1);
571 /* switch bank back to bank 0 for later BT and wifi use. */
572 hal_EfuseSwitchToBank(padapter, 0);
574 /* Copy from Efuse map to output pointer memory!!! */
575 for (i = 0; i < _size_byte; i++)
576 pbuf[i] = efuseTbl[_offset + i];
579 /* Calculate Efuse utilization. */
581 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
582 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
583 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
584 pHalData->BTEfuseUsedBytes = used;
591 rtl8723a_readefuse(struct rtw_adapter *padapter,
592 u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf)
594 if (efuseType == EFUSE_WIFI)
595 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf);
597 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf);
600 u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter)
603 u8 hoffset = 0, hworden = 0;
604 u8 efuse_data, word_cnts = 0;
605 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
607 efuse_addr = pHalData->EfuseUsedBytes;
609 DBG_8723A("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);
611 /* switch bank back to bank 0 for later BT and wifi use. */
612 hal_EfuseSwitchToBank(padapter, 0);
614 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
615 if (efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data) ==
617 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail! "
618 "addr = 0x%X !!\n", __func__, efuse_addr);
622 if (efuse_data == 0xFF)
625 if (EXT_HEADER(efuse_data)) {
626 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
628 efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data);
629 if (ALL_WORDS_DISABLED(efuse_data))
632 hoffset |= ((efuse_data & 0xF0) >> 1);
633 hworden = efuse_data & 0x0F;
635 hoffset = (efuse_data >> 4) & 0x0F;
636 hworden = efuse_data & 0x0F;
639 word_cnts = Efuse_CalculateWordCnts23a(hworden);
640 efuse_addr += (word_cnts * 2) + 1;
643 pHalData->EfuseUsedBytes = efuse_addr;
645 DBG_8723A("%s: CurrentSize =%d\n", __func__, efuse_addr);
650 u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter)
655 u8 hoffset = 0, hworden = 0;
656 u8 efuse_data, word_cnts = 0;
658 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
660 btusedbytes = pHalData->BTEfuseUsedBytes;
662 efuse_addr = (u16) ((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
663 startBank = (u8) (1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
665 DBG_8723A("%s: start from bank =%d addr = 0x%X\n", __func__, startBank,
668 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
669 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2);
671 for (bank = startBank; bank < EFUSE_MAX_BANK; bank++) {
672 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
673 DBG_8723A(KERN_ERR "%s: switch bank(%d) Fail!!\n",
675 bank = EFUSE_MAX_BANK;
679 /* only when bank is switched we have to reset
681 if (bank != startBank)
684 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
685 if (efuse_OneByteRead23a(padapter, efuse_addr,
686 &efuse_data) == _FAIL) {
687 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail!"
689 __func__, efuse_addr);
690 bank = EFUSE_MAX_BANK;
694 if (efuse_data == 0xFF)
697 if (EXT_HEADER(efuse_data)) {
698 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
700 efuse_OneByteRead23a(padapter, efuse_addr,
702 if (ALL_WORDS_DISABLED(efuse_data)) {
707 hoffset |= ((efuse_data & 0xF0) >> 1);
708 hworden = efuse_data & 0x0F;
710 hoffset = (efuse_data >> 4) & 0x0F;
711 hworden = efuse_data & 0x0F;
713 word_cnts = Efuse_CalculateWordCnts23a(hworden);
714 /* read next header */
715 efuse_addr += (word_cnts * 2) + 1;
718 /* Check if we need to check next bank efuse */
719 if (efuse_addr < retU2)
720 break; /* don't need to check next bank. */
723 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
724 pHalData->BTEfuseUsedBytes = retU2;
726 DBG_8723A("%s: CurrentSize =%d\n", __func__, retU2);
730 void rtl8723a_read_chip_version(struct rtw_adapter *padapter)
733 struct hal_version ChipVersion;
734 struct hal_data_8723a *pHalData;
736 pHalData = GET_HAL_DATA(padapter);
738 value32 = rtl8723au_read32(padapter, REG_SYS_CFG);
739 ChipVersion.ICType = CHIP_8723A;
740 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
741 pHalData->rf_type = RF_1T1R;
742 ChipVersion.VendorType =
743 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
744 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
746 /* For regulator mode. by tynli. 2011.01.14 */
747 pHalData->RegulatorMode = ((value32 & SPS_SEL) ?
748 RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
750 value32 = rtl8723au_read32(padapter, REG_GPIO_OUTSTS);
751 /* ROM code version. */
752 ChipVersion.ROMVer = (value32 & RF_RL_ID) >> 20;
754 /* For multi-function consideration. Added by Roger, 2010.10.06. */
755 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
756 value32 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
757 pHalData->MultiFunc |=
758 ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
759 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
760 pHalData->MultiFunc |=
761 ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
762 pHalData->PolarityCtl =
763 ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT :
764 RT_POLARITY_LOW_ACT);
765 pHalData->VersionID = ChipVersion;
767 MSG_8723A("RF_Type is %x!!\n", pHalData->rf_type);
772 /* 20100209 Joseph: */
773 /* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
774 /* We just reserve the value of the register in variable
775 pHalData->RegBcnCtrlVal and then operate */
776 /* the value of the register via atomic operation. */
777 /* This prevents from race condition when setting this register. */
778 /* The value of pHalData->RegBcnCtrlVal is initialized in
779 HwConfigureRTL8192CE() function. */
781 void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits)
785 val8 = rtl8723au_read8(padapter, REG_BCN_CTRL);
789 rtl8723au_write8(padapter, REG_BCN_CTRL, val8);
792 void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter)
794 rtl8723au_write16(padapter, REG_BCN_CTRL, 0x1010);
796 /* TODO: Remove these magic number */
797 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0x6404); /* ms */
798 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
799 /* so don't set this register on STA mode. */
800 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
801 rtl8723au_write8(padapter, REG_DRVERLYINT,
802 DRIVER_EARLY_INT_TIME);
804 rtl8723au_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
806 /* Suggested by designer timchen. Change beacon AIFS to the
807 largest number beacause test chip does not contension before
808 sending beacon. by tynli. 2009.11.03 */
809 rtl8723au_write16(padapter, REG_BCNTCFG, 0x660F);
812 static void ResumeTxBeacon(struct rtw_adapter *padapter)
814 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
816 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
817 we record the value */
818 /* which should be read from register to a global variable. */
820 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, "+ResumeTxBeacon\n");
822 pHalData->RegFwHwTxQCtrl |= BIT(6);
823 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
824 pHalData->RegFwHwTxQCtrl);
825 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
826 pHalData->RegReg542 |= BIT(0);
827 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
830 static void StopTxBeacon(struct rtw_adapter *padapter)
832 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
834 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
835 we record the value */
836 /* which should be read from register to a global variable. */
838 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, "+StopTxBeacon\n");
840 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
841 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
842 pHalData->RegFwHwTxQCtrl);
843 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
844 pHalData->RegReg542 &= ~BIT(0);
845 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
848 static void _BeaconFunctionEnable(struct rtw_adapter *padapter, u8 Enable,
851 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB,
853 rtl8723au_write8(padapter, REG_RD_CTRL + 1, 0x6F);
856 void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter)
859 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
860 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
862 /* reset TSF, enable update TSF, correcting TSF On Beacon */
864 /* REG_BCN_INTERVAL */
867 /* REG_TBTT_PROHIBIT */
869 /* REG_BCN_MAX_ERR */
870 /* REG_BCNTCFG (0x510) */
871 /* REG_DUAL_TSF_RST */
872 /* REG_BCN_CTRL (0x550) */
877 rtl8723au_write16(padapter, REG_ATIMWND, 2);
880 /* Beacon interval (in unit of TU). */
882 rtl8723au_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
884 rtl8723a_InitBeaconParameters(padapter);
886 rtl8723au_write8(padapter, REG_SLOT, 0x09);
889 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
891 value32 = rtl8723au_read32(padapter, REG_TCR);
893 rtl8723au_write32(padapter, REG_TCR, value32);
896 rtl8723au_write32(padapter, REG_TCR, value32);
898 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
899 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE |
900 WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == true) {
901 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
902 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
905 _BeaconFunctionEnable(padapter, true, true);
907 ResumeTxBeacon(padapter);
908 SetBcnCtrlReg23a(padapter, DIS_BCNQ_SUB, 0);
911 void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
912 enum hal_odm_variable eVariable,
913 void *pValue1, bool bSet)
915 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
916 struct dm_odm_t *podmpriv = &pHalData->odmpriv;
918 case HAL_ODM_STA_INFO:
920 struct sta_info *psta = (struct sta_info *)pValue1;
923 DBG_8723A("Set STA_(%d) info\n", psta->mac_id);
924 ODM_CmnInfoPtrArrayHook23a(podmpriv,
925 ODM_CMNINFO_STA_STATUS,
928 DBG_8723A("Clean STA_(%d) info\n", psta->mac_id);
929 ODM_CmnInfoPtrArrayHook23a(podmpriv,
930 ODM_CMNINFO_STA_STATUS,
935 case HAL_ODM_P2P_STATE:
936 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
938 case HAL_ODM_WIFI_DISPLAY_STATE:
939 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
946 void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable)
949 DBG_8723A("Enable notch filter\n");
950 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
951 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) |
954 DBG_8723A("Disable notch filter\n");
955 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
956 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) &
961 bool c2h_id_filter_ccx_8723a(u8 id)
964 if (id == C2H_CCX_TX_RPT)
970 int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt)
975 if (c2h_evt == NULL) {
976 DBG_8723A("%s c2h_evt is NULL\n", __func__);
981 switch (c2h_evt->id) {
983 RT_TRACE(_module_hal_init_c_, _drv_info_,
984 "C2HCommandHandler: %s\n", c2h_evt->payload);
988 handle_txrpt_ccx_8723a(padapter, c2h_evt->payload);
992 case C2H_HW_INFO_EXCH:
993 RT_TRACE(_module_hal_init_c_, _drv_info_,
994 "[BT], C2H_HW_INFO_EXCH\n");
995 for (i = 0; i < c2h_evt->plen; i++) {
996 RT_TRACE(_module_hal_init_c_, _drv_info_,
997 "[BT], tmpBuf[%d]= 0x%x\n", i,
998 c2h_evt->payload[i]);
1002 case C2H_C2H_H2C_TEST:
1003 RT_TRACE(_module_hal_init_c_, _drv_info_,
1004 "[BT], C2H_H2C_TEST\n");
1005 RT_TRACE(_module_hal_init_c_, _drv_info_,
1006 "[BT], tmpBuf[0]/[1]/[2]/[3]/[4]= 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x\n",
1007 c2h_evt->payload[0],
1008 c2h_evt->payload[1], c2h_evt->payload[2],
1009 c2h_evt->payload[3], c2h_evt->payload[4]);
1013 DBG_8723A("%s , Got C2H_BT_INFO \n", __func__);
1014 rtl8723a_fw_c2h_BT_info(padapter,
1015 c2h_evt->payload, c2h_evt->plen);
1027 void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf)
1029 struct txrpt_ccx_8723a *txrpt_ccx = buf;
1030 struct submit_ctx *pack_tx_ops = &adapter->xmitpriv.ack_tx_ops;
1032 if (txrpt_ccx->int_ccx && adapter->xmitpriv.ack_tx) {
1033 if (txrpt_ccx->pkt_ok)
1034 rtw23a_sctx_done_err(&pack_tx_ops,
1035 RTW_SCTX_DONE_SUCCESS);
1037 rtw23a_sctx_done_err(&pack_tx_ops,
1038 RTW_SCTX_DONE_CCX_PKT_FAIL);
1042 void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter)
1046 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1047 /* Let 8051 take control antenna settting */
1048 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1049 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1052 void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter)
1056 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1057 /* Let 8051 take control antenna settting */
1058 if (!(val & BIT(7))) {
1059 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1060 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1064 void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter)
1068 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1069 /* Let 8051 take control antenna settting */
1070 val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
1071 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1074 void rtl8723a_init_default_value(struct rtw_adapter *padapter)
1076 struct hal_data_8723a *pHalData;
1077 struct dm_priv *pdmpriv;
1080 pHalData = GET_HAL_DATA(padapter);
1081 pdmpriv = &pHalData->dmpriv;
1083 /* init default value */
1084 pHalData->bIQKInitialized = false;
1085 if (!padapter->pwrctrlpriv.bkeepfwalive)
1086 pHalData->LastHMEBoxNum = 0;
1088 pHalData->bIQKInitialized = false;
1090 /* init dm default value */
1091 pdmpriv->TM_Trigger = 0; /* for IQK */
1092 /* pdmpriv->binitialized = false; */
1093 /* pdmpriv->prv_traffic_idx = 3; */
1094 /* pdmpriv->initialize = 0; */
1096 pdmpriv->ThermalValue_HP_index = 0;
1097 for (i = 0; i < HP_THERMAL_NUM; i++)
1098 pdmpriv->ThermalValue_HP[i] = 0;
1100 /* init Efuse variables */
1101 pHalData->EfuseUsedBytes = 0;
1102 pHalData->BTEfuseUsedBytes = 0;
1105 u8 GetEEPROMSize8723A(struct rtw_adapter *padapter)
1110 cr = rtl8723au_read16(padapter, REG_9346CR);
1111 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1112 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1114 MSG_8723A("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
1121 /* LLT R/W/Init function */
1124 static int _LLTWrite(struct rtw_adapter *padapter, u32 address, u32 data)
1126 int status = _SUCCESS;
1128 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
1129 _LLT_OP(_LLT_WRITE_ACCESS);
1130 u16 LLTReg = REG_LLT_INIT;
1132 rtl8723au_write32(padapter, LLTReg, value);
1136 value = rtl8723au_read32(padapter, LLTReg);
1137 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
1140 if (count > POLLING_LLT_THRESHOLD) {
1141 RT_TRACE(_module_hal_init_c_, _drv_err_,
1142 "Failed to polling write LLT done at address %d!\n",
1152 int InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary)
1154 int status = _SUCCESS;
1156 u32 txpktbuf_bndy = boundary;
1157 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1159 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
1160 status = _LLTWrite(padapter, i, i + 1);
1161 if (status != _SUCCESS)
1166 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1167 if (status != _SUCCESS)
1170 /* Make the other pages as ring buffer */
1171 /* This ring buffer is used as beacon buffer if we config this
1172 MAC as two MAC transfer. */
1173 /* Otherwise used as local loopback buffer. */
1174 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
1175 status = _LLTWrite(padapter, i, (i + 1));
1176 if (_SUCCESS != status)
1180 /* Let last entry point to the start entry of ring buffer */
1181 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1182 if (status != _SUCCESS)
1188 static void _DisableGPIO(struct rtw_adapter *padapter)
1190 /***************************************
1191 j. GPIO_PIN_CTRL 0x44[31:0]= 0x000
1192 k.Value = GPIO_PIN_CTRL[7:0]
1193 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
1194 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1195 n. LEDCFG 0x4C[15:0] = 0x8080
1196 ***************************************/
1200 /* 1. Disable GPIO[7:0] */
1201 rtl8723au_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
1202 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1203 u4bTmp = value32 & 0x000000FF;
1204 value32 |= ((u4bTmp << 8) | 0x00FF0000);
1205 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL, value32);
1208 /* <Roger_Notes> For RTL8723u multi-function configuration which
1209 was autoload from Efuse offset 0x0a and 0x0b, */
1210 /* WLAN HW GPIO[9], GPS HW GPIO[10] and BT HW GPIO[11]. */
1211 /* Added by Roger, 2010.10.07. */
1213 /* 2. Disable GPIO[8] and GPIO[12] */
1215 /* Configure all pins as input mode. */
1216 rtl8723au_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
1217 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL_2) & 0xFFFF001F;
1218 u4bTmp = value32 & 0x0000001F;
1219 /* Set pin 8, 10, 11 and pin 12 to output mode. */
1220 value32 |= ((u4bTmp << 8) | 0x001D0000);
1221 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
1223 /* 3. Disable LED0 & 1 */
1224 rtl8723au_write16(padapter, REG_LEDCFG0, 0x8080);
1225 } /* end of _DisableGPIO() */
1227 static void _DisableRFAFEAndResetBB8192C(struct rtw_adapter *padapter)
1229 /**************************************
1230 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1231 b. RF path 0 offset 0x00 = 0x00 disable RF
1232 c. APSD_CTRL 0x600[7:0] = 0x40
1233 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1234 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1235 ***************************************/
1238 rtl8723au_write8(padapter, REG_TXPAUSE, 0xFF);
1240 PHY_SetRFReg(padapter, RF_PATH_A, 0x0, bMaskByte0, 0x0);
1243 rtl8723au_write8(padapter, REG_APSD_CTRL, value8); /* 0x40 */
1245 /* Set BB reset at first */
1246 value8 = FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn;
1247 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
1249 /* Set global reset. */
1250 value8 &= ~FEN_BB_GLB_RSTn;
1251 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
1253 /* 2010/08/12 MH We need to set BB/GLBAL reset to save power
1257 static void _ResetDigitalProcedure1_92C(struct rtw_adapter *padapter,
1260 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1262 if (IS_FW_81xxC(padapter) && (pHalData->FirmwareVersion <= 0x20)) {
1263 /*****************************
1264 f. MCUFWDL 0x80[7:0]= 0 reset MCU ready status
1265 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset)
1266 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE
1267 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register,
1269 ******************************/
1271 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1273 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1274 /* reset MCU , 8051 */
1275 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1276 valu16 & ~FEN_CPUEN);
1278 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
1280 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1281 valu16 | FEN_HWPDN | FEN_ELDR);
1283 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1284 /* enable MCU , 8051 */
1285 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1286 valu16 | FEN_CPUEN);
1291 val8 = rtl8723au_read8(padapter, REG_MCUFWDL);
1293 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we
1294 are trying to enter IPS/HW&SW radio off. For
1295 S3/S4/S5/Disable, we can stop 8051 because */
1296 /* we will init FW when power on again. */
1297 /* If we want to SS mode, we can not reset 8051. */
1298 if ((val8 & BIT(1)) && padapter->bFWReady) {
1299 /* IF fw in RAM code, do reset */
1300 /* 2010/08/25 MH Accordign to RD alfred's
1301 suggestion, we need to disable other */
1302 /* HRCV INT to influence 8051 reset. */
1303 rtl8723au_write8(padapter, REG_FWIMR, 0x20);
1304 /* 2011/02/15 MH According to Alex's
1305 suggestion, close mask to prevent
1306 incorrect FW write operation. */
1307 rtl8723au_write8(padapter, REG_FTIMR, 0x00);
1308 rtl8723au_write8(padapter, REG_FSIMR, 0x00);
1310 /* 8051 reset by self */
1311 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
1313 while ((retry_cnts++ < 100) &&
1314 (rtl8723au_read16(padapter, REG_SYS_FUNC_EN) &
1316 udelay(50); /* us */
1319 if (retry_cnts >= 100) {
1320 /* Reset MAC and Enable 8051 */
1321 rtl8723au_write8(padapter,
1322 REG_SYS_FUNC_EN + 1, 0x50);
1326 /* Reset MAC and Enable 8051 */
1327 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
1328 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1332 /*****************************
1333 Without HW auto state machine
1334 g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1335 h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1336 i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1337 j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1338 ******************************/
1339 /* modify to 0x70A3 by Scott. */
1340 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70A3);
1341 rtl8723au_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
1342 rtl8723au_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
1343 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
1345 /* Disable all RF/BB power */
1346 rtl8723au_write8(padapter, REG_RF_CTRL, 0x00);
1350 static void _ResetDigitalProcedure2(struct rtw_adapter *padapter)
1352 /*****************************
1353 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1354 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1355 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1356 ******************************/
1357 /* modify to 0x70a3 by Scott. */
1358 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70a3);
1359 /* modify to 0x82 by Scott. */
1360 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
1363 static void _DisableAnalog(struct rtw_adapter *padapter, bool bWithoutHWSM)
1365 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1370 /*****************************
1371 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1372 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1373 r. When driver call disable, the ASIC will turn off remaining
1375 ******************************/
1377 rtl8723au_write8(padapter, REG_LDOA15_CTRL, 0x04);
1378 /* rtl8723au_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
1380 value8 = rtl8723au_read8(padapter, REG_LDOV12D_CTRL);
1381 value8 &= ~LDV12_EN;
1382 rtl8723au_write8(padapter, REG_LDOV12D_CTRL, value8);
1385 /*****************************
1386 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1387 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1388 ******************************/
1390 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1393 rtl8723au_write8(padapter, REG_SPS0_CTRL, value8);
1396 /* value16 |= (APDM_HOST | FSM_HSUS |/PFM_ALDN); */
1397 /* 2010/08/31 According to Filen description, we need to
1398 use HW to shut down 8051 automatically. */
1399 /* Because suspend operation need the asistance of 8051
1401 value16 = APDM_HOST | AFSM_HSUS | PFM_ALDN;
1403 value16 = APDM_HOST | AFSM_HSUS | PFM_ALDN;
1406 rtl8723au_write16(padapter, REG_APS_FSMCO, value16); /* 0x4802 */
1408 rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0e);
1411 /* HW Auto state machine */
1412 int CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU)
1414 if (padapter->bSurpriseRemoved)
1417 /* RF Off Sequence ==== */
1418 _DisableRFAFEAndResetBB8192C(padapter);
1420 /* ==== Reset digital sequence ====== */
1421 _ResetDigitalProcedure1_92C(padapter, false);
1423 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1424 _DisableGPIO(padapter);
1426 /* ==== Disable analog sequence === */
1427 _DisableAnalog(padapter, false);
1429 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1430 "======> Card disable finished.\n");
1435 /* without HW Auto state machine */
1436 int CardDisableWithoutHWSM(struct rtw_adapter *padapter)
1438 if (padapter->bSurpriseRemoved)
1441 /* RF Off Sequence ==== */
1442 _DisableRFAFEAndResetBB8192C(padapter);
1444 /* ==== Reset digital sequence ====== */
1445 _ResetDigitalProcedure1_92C(padapter, true);
1447 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1448 _DisableGPIO(padapter);
1450 /* ==== Reset digital sequence ====== */
1451 _ResetDigitalProcedure2(padapter);
1453 /* ==== Disable analog sequence === */
1454 _DisableAnalog(padapter, true);
1459 void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent)
1461 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1463 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1464 if (!pEEPROM->EepromOrEfuse) {
1465 /* Read EFUSE real map to shadow. */
1466 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1467 memcpy(PROMContent, pEEPROM->efuse_eeprom_data,
1471 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1472 "AutoLoad Fail reported from CR9346!!\n");
1473 /* update to default value 0xFF */
1474 if (!pEEPROM->EepromOrEfuse)
1475 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1476 memcpy(PROMContent, pEEPROM->efuse_eeprom_data,
1481 void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo)
1483 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1484 /* struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); */
1487 /* Checl 0x8129 again for making sure autoload status!! */
1488 EEPROMId = le16_to_cpu(*((__le16 *) hwinfo));
1489 if (EEPROMId != RTL_EEPROM_ID) {
1490 DBG_8723A("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
1491 pEEPROM->bautoload_fail_flag = true;
1493 pEEPROM->bautoload_fail_flag = false;
1496 RT_TRACE(_module_hal_init_c_, _drv_info_,
1497 "EEPROM ID = 0x%04x\n", EEPROMId);
1501 Hal_ReadPowerValueFromPROM_8723A(struct txpowerinfo *pwrInfo,
1502 u8 *PROMContent, bool AutoLoadFail)
1504 u32 rfPath, eeAddr, group, rfPathMax = 1;
1506 memset(pwrInfo, 0, sizeof(*pwrInfo));
1509 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1510 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1511 pwrInfo->CCKIndex[rfPath][group] =
1512 EEPROM_Default_TxPowerLevel;
1513 pwrInfo->HT40_1SIndex[rfPath][group] =
1514 EEPROM_Default_TxPowerLevel;
1515 pwrInfo->HT40_2SIndexDiff[rfPath][group] =
1516 EEPROM_Default_HT40_2SDiff;
1517 pwrInfo->HT20IndexDiff[rfPath][group] =
1518 EEPROM_Default_HT20_Diff;
1519 pwrInfo->OFDMIndexDiff[rfPath][group] =
1520 EEPROM_Default_LegacyHTTxPowerDiff;
1521 pwrInfo->HT40MaxOffset[rfPath][group] =
1522 EEPROM_Default_HT40_PwrMaxOffset;
1523 pwrInfo->HT20MaxOffset[rfPath][group] =
1524 EEPROM_Default_HT20_PwrMaxOffset;
1527 pwrInfo->TSSI_A[0] = EEPROM_Default_TSSI;
1531 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1532 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1534 EEPROM_CCK_TX_PWR_INX_8723A + (rfPath * 3) + group;
1536 pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
1537 if (pwrInfo->CCKIndex[rfPath][group] > 63)
1538 pwrInfo->CCKIndex[rfPath][group] =
1539 EEPROM_Default_TxPowerLevel;
1541 eeAddr = EEPROM_HT40_1S_TX_PWR_INX_8723A +
1542 (rfPath * 3) + group;
1543 pwrInfo->HT40_1SIndex[rfPath][group] =
1544 PROMContent[eeAddr];
1545 if (pwrInfo->HT40_1SIndex[rfPath][group] > 63)
1546 pwrInfo->HT40_1SIndex[rfPath][group] =
1547 EEPROM_Default_TxPowerLevel;
1551 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1552 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1553 pwrInfo->HT40_2SIndexDiff[rfPath][group] = 0;
1554 pwrInfo->HT20IndexDiff[rfPath][group] =
1556 [EEPROM_HT20_TX_PWR_INX_DIFF_8723A +
1557 group] >> (rfPath * 4)) & 0xF;
1558 /* 4bit sign number to 8 bit sign number */
1559 if (pwrInfo->HT20IndexDiff[rfPath][group] & BIT(3))
1560 pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
1562 pwrInfo->OFDMIndexDiff[rfPath][group] =
1563 (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF_8723A +
1564 group] >> (rfPath * 4)) & 0xF;
1566 pwrInfo->HT40MaxOffset[rfPath][group] =
1567 (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET_8723A +
1568 group] >> (rfPath * 4)) & 0xF;
1570 pwrInfo->HT20MaxOffset[rfPath][group] =
1571 (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET_8723A +
1572 group] >> (rfPath * 4)) & 0xF;
1576 pwrInfo->TSSI_A[0] = PROMContent[EEPROM_TSSI_A_8723A];
1579 static u8 Hal_GetChnlGroup(u8 chnl)
1583 if (chnl < 3) /* Cjanel 1-3 */
1585 else if (chnl < 9) /* Channel 4-9 */
1587 else /* Channel 10-14 */
1594 Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter,
1595 u8 *PROMContent, bool AutoLoadFail)
1597 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1598 struct txpowerinfo pwrInfo;
1599 u8 rfPath, ch, group, rfPathMax = 1;
1602 Hal_ReadPowerValueFromPROM_8723A(&pwrInfo, PROMContent, AutoLoadFail);
1603 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1604 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1605 group = Hal_GetChnlGroup(ch);
1607 pHalData->TxPwrLevelCck[rfPath][ch] =
1608 pwrInfo.CCKIndex[rfPath][group];
1609 pHalData->TxPwrLevelHT40_1S[rfPath][ch] =
1610 pwrInfo.HT40_1SIndex[rfPath][group];
1612 pHalData->TxPwrHt20Diff[rfPath][ch] =
1613 pwrInfo.HT20IndexDiff[rfPath][group];
1614 pHalData->TxPwrLegacyHtDiff[rfPath][ch] =
1615 pwrInfo.OFDMIndexDiff[rfPath][group];
1616 pHalData->PwrGroupHT20[rfPath][ch] =
1617 pwrInfo.HT20MaxOffset[rfPath][group];
1618 pHalData->PwrGroupHT40[rfPath][ch] =
1619 pwrInfo.HT40MaxOffset[rfPath][group];
1621 pwr = pwrInfo.HT40_1SIndex[rfPath][group];
1622 diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
1624 pHalData->TxPwrLevelHT40_2S[rfPath][ch] =
1625 (pwr > diff) ? (pwr - diff) : 0;
1628 for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
1629 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1630 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1631 "RF(%u)-Ch(%u) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1633 pHalData->TxPwrLevelCck[rfPath][ch],
1634 pHalData->TxPwrLevelHT40_1S[rfPath][ch],
1635 pHalData->TxPwrLevelHT40_2S[rfPath][ch]);
1639 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1640 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1641 "RF-A Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1642 pHalData->TxPwrHt20Diff[RF_PATH_A][ch],
1643 pHalData->TxPwrHt20Diff[RF_PATH_A][ch]);
1645 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1646 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1647 "RF-A Legacy to Ht40 Diff[%u] = 0x%x\n", ch,
1648 pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]);
1649 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1650 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1651 "RF-B Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1652 pHalData->TxPwrHt20Diff[RF_PATH_B][ch],
1653 pHalData->TxPwrHt20Diff[RF_PATH_B][ch]);
1655 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1656 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1657 "RF-B Legacy to HT40 Diff[%u] = 0x%x\n", ch,
1658 pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]);
1659 if (!AutoLoadFail) {
1660 struct registry_priv *registry_par = &padapter->registrypriv;
1661 if (registry_par->regulatory_tid == 0xff) {
1662 if (PROMContent[RF_OPTION1_8723A] == 0xff)
1663 pHalData->EEPROMRegulatory = 0;
1665 pHalData->EEPROMRegulatory =
1666 PROMContent[RF_OPTION1_8723A] & 0x7;
1668 pHalData->EEPROMRegulatory =
1669 registry_par->regulatory_tid;
1672 pHalData->EEPROMRegulatory = 0;
1674 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1675 "EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
1678 pHalData->bTXPowerDataReadFromEEPORM = true;
1682 Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter,
1683 u8 *hwinfo, bool AutoLoadFail)
1685 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1689 if (!AutoLoadFail) {
1690 tmpu4 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
1691 if (tmpu4 & BT_FUNC_EN)
1692 pHalData->EEPROMBluetoothCoexist = 1;
1694 pHalData->EEPROMBluetoothCoexist = 0;
1695 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1697 /* The following need to be checked with newer version of */
1699 tempval = hwinfo[RF_OPTION4_8723A];
1700 pHalData->EEPROMBluetoothAntNum = (tempval & 0x1);
1701 pHalData->EEPROMBluetoothAntIsolation = (tempval & 0x10) >> 4;
1702 pHalData->EEPROMBluetoothRadioShared = (tempval & 0x20) >> 5;
1704 pHalData->EEPROMBluetoothCoexist = 0;
1705 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1706 pHalData->EEPROMBluetoothAntNum = Ant_x2;
1707 pHalData->EEPROMBluetoothAntIsolation = 0;
1708 pHalData->EEPROMBluetoothRadioShared = BT_Radio_Shared;
1711 rtl8723a_BT_init_hal_vars(padapter);
1715 Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter,
1716 u8 *hwinfo, bool AutoLoadFail)
1718 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1721 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723A];
1723 pHalData->EEPROMVersion = 1;
1724 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1725 "Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
1726 pHalData->EEPROMVersion);
1730 rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter,
1731 u8 *hwinfo, bool AutoLoadFail)
1733 padapter->mlmepriv.ChannelPlan =
1734 hal_com_get_channel_plan23a(padapter, hwinfo ?
1735 hwinfo[EEPROM_ChannelPlan_8723A]:0xFF,
1736 padapter->registrypriv.channel_plan,
1737 RT_CHANNEL_DOMAIN_WORLD_WIDE_13,
1740 DBG_8723A("mlmepriv.ChannelPlan = 0x%02x\n",
1741 padapter->mlmepriv.ChannelPlan);
1745 Hal_EfuseParseCustomerID(struct rtw_adapter *padapter,
1746 u8 *hwinfo, bool AutoLoadFail)
1748 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1750 if (!AutoLoadFail) {
1751 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723A];
1752 pHalData->EEPROMSubCustomerID =
1753 hwinfo[EEPROM_SubCustomID_8723A];
1755 pHalData->EEPROMCustomerID = 0;
1756 pHalData->EEPROMSubCustomerID = 0;
1758 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1759 "EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
1760 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1761 "EEPROM SubCustomer ID: 0x%02x\n",
1762 pHalData->EEPROMSubCustomerID);
1766 Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter,
1767 u8 *hwinfo, bool AutoLoadFail)
1772 Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter,
1773 u8 *hwinfo, bool AutoLoadFail)
1778 Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter,
1779 u8 *hwinfo, u8 AutoLoadFail)
1781 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1783 if (!AutoLoadFail) {
1784 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_K_8723A];
1785 if (pHalData->CrystalCap == 0xFF)
1786 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1788 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1790 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1791 "%s: CrystalCap = 0x%2x\n", __func__,
1792 pHalData->CrystalCap);
1796 Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter,
1797 u8 *PROMContent, bool AutoloadFail)
1799 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1802 /* ThermalMeter from EEPROM */
1805 pHalData->EEPROMThermalMeter =
1806 PROMContent[EEPROM_THERMAL_METER_8723A];
1808 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1810 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoloadFail) {
1811 pHalData->bAPKThermalMeterIgnore = true;
1812 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1815 DBG_8723A("%s: ThermalMeter = 0x%x\n", __func__,
1816 pHalData->EEPROMThermalMeter);
1819 static void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc)
1821 __le16 *usPtr = (__le16 *)ptxdesc;
1822 u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
1827 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
1829 for (index = 0; index < count; index++)
1830 checksum ^= le16_to_cpu(usPtr[index]);
1832 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
1836 * Description: In normal chip, we should send some packet to Hw which
1837 * will be used by Fw in FW LPS mode. The function is to fill the Tx
1838 * descriptor of this packets, then
1840 /* Fw can tell Hw to send these packet derectly. */
1841 /* Added by tynli. 2009.10.15. */
1843 void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc,
1844 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull)
1846 struct tx_desc *ptxdesc;
1848 /* Clear all status */
1849 ptxdesc = (struct tx_desc *)pDesc;
1850 memset(pDesc, 0, TXDESC_SIZE);
1853 /* own, bFirstSeg, bLastSeg; */
1854 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1856 /* 32 bytes for TX Desc */
1857 ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) <<
1858 OFFSET_SHT) & 0x00ff0000);
1860 /* Buffer size + command header */
1861 ptxdesc->txdw0 |= cpu_to_le32(BufferLen & 0x0000ffff);
1864 /* Fixed queue of Mgnt queue */
1865 ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT << QSEL_SHT) & 0x00001f00);
1867 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed
1868 to error vlaue by Hw. */
1870 ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
1872 /* Hw set sequence number */
1873 ptxdesc->txdw4 |= cpu_to_le32(BIT(7));
1874 /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
1875 ptxdesc->txdw3 |= cpu_to_le32((8 << 28));
1878 if (true == IsBTQosNull)
1879 ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
1882 ptxdesc->txdw4 |= cpu_to_le32(BIT(8)); /* driver uses rate */
1884 /* USB interface drop packet if the checksum of descriptor isn't
1886 /* Using this checksum can let hardware recovery from packet bulk
1887 out error (e.g. Cancel URC, Bulk out error.). */
1888 rtl8723a_cal_txdesc_chksum(ptxdesc);
1891 void hw_var_set_opmode(struct rtw_adapter *padapter, u8 mode)
1895 if (mode == MSR_INFRA || mode == MSR_NOLINK) {
1896 StopTxBeacon(padapter);
1898 /* disable atim wnd */
1899 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM;
1900 SetBcnCtrlReg23a(padapter, val8, ~val8);
1901 } else if (mode == MSR_ADHOC) {
1902 ResumeTxBeacon(padapter);
1904 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB;
1905 SetBcnCtrlReg23a(padapter, val8, ~val8);
1906 } else if (mode == MSR_AP) {
1907 /* add NULL Data and BT NULL Data Packets to FW RSVD Page */
1908 rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(padapter);
1910 ResumeTxBeacon(padapter);
1912 val8 = DIS_TSF_UDT | DIS_BCNQ_SUB;
1913 SetBcnCtrlReg23a(padapter, val8, ~val8);
1916 /* rtl8723au_write32(padapter, REG_RCR, 0x70002a8e);
1917 CBSSID_DATA must set to 0 */
1918 /* CBSSID_DATA must set to 0 */
1919 rtl8723au_write32(padapter, REG_RCR, 0x7000228e);
1920 /* enable to rx data frame */
1921 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
1922 /* enable to rx ps-poll */
1923 rtl8723au_write16(padapter, REG_RXFLTMAP1, 0x0400);
1925 /* Beacon Control related register for first time */
1927 rtl8723au_write8(padapter, REG_BCNDMATIM, 0x02);
1929 rtl8723au_write8(padapter, REG_DRVERLYINT, 0x05);
1930 /* 10ms for port0 */
1931 rtl8723au_write8(padapter, REG_ATIMWND, 0x0a);
1932 rtl8723au_write16(padapter, REG_BCNTCFG, 0x00);
1933 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
1934 /* +32767 (~32ms) */
1935 rtl8723au_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
1938 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
1940 /* enable BCN Function */
1941 /* don't enable update TSF (due to TSF update when
1942 beacon/probe rsp are received) */
1943 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION |
1944 EN_TXBCN_RPT | DIS_BCNQ_SUB;
1945 SetBcnCtrlReg23a(padapter, val8, ~val8);
1948 val8 = rtl8723au_read8(padapter, MSR);
1949 val8 = (val8 & 0xC) | mode;
1950 rtl8723au_write8(padapter, MSR, val8);
1953 void hw_var_set_macaddr(struct rtw_adapter *padapter, u8 *val)
1958 reg_macid = REG_MACID;
1960 for (idx = 0; idx < 6; idx++)
1961 rtl8723au_write8(padapter, (reg_macid + idx), val[idx]);
1964 void hw_var_set_bssid(struct rtw_adapter *padapter, u8 *val)
1969 reg_bssid = REG_BSSID;
1971 for (idx = 0; idx < 6; idx++)
1972 rtl8723au_write8(padapter, (reg_bssid + idx), val[idx]);
1975 void hw_var_set_correct_tsf(struct rtw_adapter *padapter)
1979 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1980 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1982 /* tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue %
1983 (pmlmeinfo->bcn_interval*1024)) - 1024; us */
1984 tsf = pmlmeext->TSFValue -
1985 do_div(pmlmeext->TSFValue,
1986 (pmlmeinfo->bcn_interval * 1024)) - 1024; /* us */
1988 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
1989 ((pmlmeinfo->state & 0x03) == MSR_AP)) {
1990 /* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */
1991 /* rtl8723au_write8(padapter, REG_TXPAUSE,
1992 (rtl8723au_read8(Adapter, REG_TXPAUSE)|BIT(6))); */
1993 StopTxBeacon(padapter);
1996 reg_tsftr = REG_TSFTR;
1998 /* disable related TSF function */
1999 SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION);
2001 rtl8723au_write32(padapter, reg_tsftr, tsf);
2002 rtl8723au_write32(padapter, reg_tsftr + 4, tsf >> 32);
2004 /* enable related TSF function */
2005 SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION, 0);
2007 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
2008 ((pmlmeinfo->state & 0x03) == MSR_AP))
2009 ResumeTxBeacon(padapter);
2012 void hw_var_set_mlme_disconnect(struct rtw_adapter *padapter)
2014 /* reject all data frames */
2015 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2018 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2020 /* disable update TSF */
2021 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
2024 void hw_var_set_mlme_join(struct rtw_adapter *padapter, u8 type)
2026 u8 RetryLimit = 0x30;
2028 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
2029 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
2031 if (type == 0) { /* prepare to join */
2034 /* enable to rx data frame.Accept all data frame */
2035 /* rtl8723au_write32(padapter, REG_RCR,
2036 rtl8723au_read32(padapter, REG_RCR)|RCR_ADF); */
2037 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2039 v32 = rtl8723au_read32(padapter, REG_RCR);
2040 v32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
2041 rtl8723au_write32(padapter, REG_RCR, v32);
2043 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
2045 (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
2046 else /* Ad-hoc Mode */
2048 } else if (type == 1) { /* joinbss_event callback when join res < 0 */
2049 /* config RCR to receive different BSSID & not to
2050 receive data frame during linking */
2051 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2052 } else if (type == 2) { /* sta add event callback */
2053 /* enable update TSF */
2054 SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
2056 if (check_fwstate(pmlmepriv,
2057 WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2058 /* fixed beacon issue for 8191su........... */
2059 rtl8723au_write8(padapter, 0x542, 0x02);
2064 rtl8723au_write16(padapter, REG_RL,
2065 RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit <<
2066 RETRY_LIMIT_LONG_SHIFT);
2070 /* prepare to join */
2071 rtl8723a_BT_wifiassociate_notify(padapter, true);
2074 /* joinbss_event callback when join res < 0 */
2075 rtl8723a_BT_wifiassociate_notify(padapter, false);
2078 /* sta add event callback */
2079 /* BT_WifiMediaStatusNotify(padapter, RT_MEDIA_CONNECT); */