drivers/staging/rtl8192u/r819xU_phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "r8192U.h"
   3 #include "r8192U_hw.h"
   4 #include "r819xU_phy.h"
   5 #include "r819xU_phyreg.h"
   6 #include "r8190_rtl8256.h"
   7 #include "r8192U_dm.h"
   8 #include "r819xU_firmware_img.h"
   9
  10 #include "ieee80211/dot11d.h"
  11 #include <linux/bitops.h>
  12
  13 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  14         0,
  15         0x085c, /* 2412 1  */
  16         0x08dc, /* 2417 2  */
  17         0x095c, /* 2422 3  */
  18         0x09dc, /* 2427 4  */
  19         0x0a5c, /* 2432 5  */
  20         0x0adc, /* 2437 6  */
  21         0x0b5c, /* 2442 7  */
  22         0x0bdc, /* 2447 8  */
  23         0x0c5c, /* 2452 9  */
  24         0x0cdc, /* 2457 10 */
  25         0x0d5c, /* 2462 11 */
  26         0x0ddc, /* 2467 12 */
  27         0x0e5c, /* 2472 13 */
  28         0x0f72, /* 2484    */
  29 };
  30
  31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  32
  33 /******************************************************************************
  34  * function:  This function checks different RF type to execute legal judgement.
  35  *            If RF Path is illegal, we will return false.
  36  * input:     net_device         *dev
  37  *            u32                e_rfpath
  38  * output:    none
  39  * return:    0(illegal, false), 1(legal, true)
  40  *****************************************************************************/
  41 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 e_rfpath)
  42 {
  43         u8 ret = 1;
  44         struct r8192_priv *priv = ieee80211_priv(dev);
  45
  46         if (priv->rf_type == RF_2T4R) {
  47                 ret = 0;
  48         } else if (priv->rf_type == RF_1T2R) {
  49                 if (e_rfpath == RF90_PATH_A || e_rfpath == RF90_PATH_B)
  50                         ret = 1;
  51                 else if (e_rfpath == RF90_PATH_C || e_rfpath == RF90_PATH_D)
  52                         ret = 0;
  53         }
  54         return ret;
  55 }
  56
  57 /******************************************************************************
  58  * function:  This function sets specific bits to BB register
  59  * input:     net_device *dev
  60  *            u32        reg_addr   //target addr to be modified
  61  *            u32        bitmask    //taget bit pos to be modified
  62  *            u32        data       //value to be write
  63  * output:    none
  64  * return:    none
  65  * notice:
  66  ******************************************************************************/
  67 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  68                       u32 data)
  69 {
  70         u32 reg, bitshift;
  71
  72         if (bitmask != bMaskDWord) {
  73                 read_nic_dword(dev, reg_addr, &reg);
  74                 bitshift = ffs(bitmask) - 1;
  75                 reg &= ~bitmask;
  76                 reg |= data << bitshift;
  77                 write_nic_dword(dev, reg_addr, reg);
  78         } else {
  79                 write_nic_dword(dev, reg_addr, data);
  80         }
  81 }
  82
  83 /******************************************************************************
  84  * function:  This function reads specific bits from BB register
  85  * input:     net_device        *dev
  86  *            u32               reg_addr   //target addr to be readback
  87  *            u32               bitmask    //taget bit pos to be readback
  88  * output:    none
  89  * return:    u32               data       //the readback register value
  90  * notice:
  91  ******************************************************************************/
  92 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
  93 {
  94         u32 reg, bitshift;
  95
  96         read_nic_dword(dev, reg_addr, &reg);
  97         bitshift = ffs(bitmask) - 1;
  98
  99         return (reg & bitmask) >> bitshift;
 100 }
 101
 102 static u32 phy_FwRFSerialRead(struct net_device *dev,
 103                               enum rf90_radio_path_e e_rfpath,
 104                               u32 offset);
 105
 106 static void phy_FwRFSerialWrite(struct net_device *dev,
 107                                 enum rf90_radio_path_e e_rfpath,
 108                                 u32  offset,
 109                                 u32  data);
 110
 111 /******************************************************************************
 112  * function:  This function reads register from RF chip
 113  * input:     net_device        *dev
 114  *            rf90_radio_path_e e_rfpath    //radio path of A/B/C/D
 115  *            u32               offset     //target address to be read
 116  * output:    none
 117  * return:    u32               readback value
 118  * notice:    There are three types of serial operations:
 119  *            (1) Software serial write.
 120  *            (2)Hardware LSSI-Low Speed Serial Interface.
 121  *            (3)Hardware HSSI-High speed serial write.
 122  *            Driver here need to implement (1) and (2)
 123  *            ---need more spec for this information.
 124  ******************************************************************************/
 125 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
 126                                     enum rf90_radio_path_e e_rfpath, u32 offset)
 127 {
 128         struct r8192_priv *priv = ieee80211_priv(dev);
 129         u32 ret = 0;
 130         u32 new_offset = 0;
 131         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath];
 132
 133         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 134         /* Make sure RF register offset is correct */
 135         offset &= 0x3f;
 136
 137         /* Switch page for 8256 RF IC */
 138         if (priv->rf_chip == RF_8256) {
 139                 if (offset >= 31) {
 140                         priv->RfReg0Value[e_rfpath] |= 0x140;
 141                         /* Switch to Reg_Mode2 for Reg 31-45 */
 142                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 143                                          bMaskDWord,
 144                                          priv->RfReg0Value[e_rfpath]<<16);
 145                         /* Modify offset */
 146                         new_offset = offset - 30;
 147                 } else if (offset >= 16) {
 148                         priv->RfReg0Value[e_rfpath] |= 0x100;
 149                         priv->RfReg0Value[e_rfpath] &= (~0x40);
 150                         /* Switch to Reg_Mode1 for Reg16-30 */
 151                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 152                                          bMaskDWord,
 153                                          priv->RfReg0Value[e_rfpath]<<16);
 154
 155                         new_offset = offset - 15;
 156                 } else {
 157                         new_offset = offset;
 158                 }
 159         } else {
 160                 RT_TRACE((COMP_PHY|COMP_ERR),
 161                          "check RF type here, need to be 8256\n");
 162                 new_offset = offset;
 163         }
 164         /* Put desired read addr to LSSI control Register */
 165         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 166                          new_offset);
 167         /* Issue a posedge trigger */
 168         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 169         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 170
 171         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 172         usleep_range(1000, 1000);
 173
 174         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 175                                  bLSSIReadBackData);
 176
 177         /* Switch back to Reg_Mode0 */
 178         if (priv->rf_chip == RF_8256) {
 179                 priv->RfReg0Value[e_rfpath] &= 0xebf;
 180
 181                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 182                                  priv->RfReg0Value[e_rfpath] << 16);
 183         }
 184
 185         return ret;
 186 }
 187
 188 /******************************************************************************
 189  * function:  This function writes data to RF register
 190  * input:     net_device        *dev
 191  *            rf90_radio_path_e e_rfpath  //radio path of A/B/C/D
 192  *            u32               offset   //target address to be written
 193  *            u32               data     //the new register data to be written
 194  * output:    none
 195  * return:    none
 196  * notice:    For RF8256 only.
 197  * ===========================================================================
 198  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 199  *              (Reg00[12])     (Reg00[10])
 200  * ===========================================================================
 201  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 202  * ---------------------------------------------------------------------------
 203  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 204  * ---------------------------------------------------------------------------
 205  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 206  * ---------------------------------------------------------------------------
 207  *****************************************************************************/
 208 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 209                                       enum rf90_radio_path_e e_rfpath,
 210                                       u32 offset,
 211                                       u32 data)
 212 {
 213         struct r8192_priv *priv = ieee80211_priv(dev);
 214         u32 DataAndAddr = 0, new_offset = 0;
 215         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[e_rfpath];
 216
 217         offset &= 0x3f;
 218         if (priv->rf_chip == RF_8256) {
 219                 if (offset >= 31) {
 220                         priv->RfReg0Value[e_rfpath] |= 0x140;
 221                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 222                                          bMaskDWord,
 223                                          priv->RfReg0Value[e_rfpath] << 16);
 224                         new_offset = offset - 30;
 225                 } else if (offset >= 16) {
 226                         priv->RfReg0Value[e_rfpath] |= 0x100;
 227                         priv->RfReg0Value[e_rfpath] &= (~0x40);
 228                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 229                                          bMaskDWord,
 230                                          priv->RfReg0Value[e_rfpath]<<16);
 231                         new_offset = offset - 15;
 232                 } else {
 233                         new_offset = offset;
 234                 }
 235         } else {
 236                 RT_TRACE((COMP_PHY|COMP_ERR),
 237                          "check RF type here, need to be 8256\n");
 238                 new_offset = offset;
 239         }
 240
 241         /* Put write addr in [5:0] and write data in [31:16] */
 242         DataAndAddr = (data<<16) | (new_offset&0x3f);
 243
 244         /* Write operation */
 245         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 246
 247         if (offset == 0x0)
 248                 priv->RfReg0Value[e_rfpath] = data;
 249
 250         /* Switch back to Reg_Mode0 */
 251         if (priv->rf_chip == RF_8256) {
 252                 if (offset != 0) {
 253                         priv->RfReg0Value[e_rfpath] &= 0xebf;
 254                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 255                                          bMaskDWord,
 256                                          priv->RfReg0Value[e_rfpath] << 16);
 257                 }
 258         }
 259 }
 260
 261 /******************************************************************************
 262  * function:  This function set specific bits to RF register
 263  * input:     net_device        dev
 264  *            rf90_radio_path_e e_rfpath  //radio path of A/B/C/D
 265  *            u32               reg_addr //target addr to be modified
 266  *            u32               bitmask  //taget bit pos to be modified
 267  *            u32               data     //value to be written
 268  * output:    none
 269  * return:    none
 270  * notice:
 271  *****************************************************************************/
 272 void rtl8192_phy_SetRFReg(struct net_device *dev,
 273                           enum rf90_radio_path_e e_rfpath,
 274                           u32 reg_addr, u32 bitmask, u32 data)
 275 {
 276         struct r8192_priv *priv = ieee80211_priv(dev);
 277         u32 reg, bitshift;
 278
 279         if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
 280                 return;
 281
 282         if (priv->Rf_Mode == RF_OP_By_FW) {
 283                 if (bitmask != bMask12Bits) {
 284                         /* RF data is 12 bits only */
 285                         reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
 286                         bitshift =  ffs(bitmask) - 1;
 287                         reg &= ~bitmask;
 288                         reg |= data << bitshift;
 289
 290                         phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg);
 291                 } else {
 292                         phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, data);
 293                 }
 294
 295                 udelay(200);
 296
 297         } else {
 298                 if (bitmask != bMask12Bits) {
 299                         /* RF data is 12 bits only */
 300                         reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
 301                         bitshift =  ffs(bitmask) - 1;
 302                         reg &= ~bitmask;
 303                         reg |= data << bitshift;
 304
 305                         rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg);
 306                 } else {
 307                         rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, data);
 308                 }
 309         }
 310 }
 311
 312 /******************************************************************************
 313  * function:  This function reads specific bits from RF register
 314  * input:     net_device        *dev
 315  *            u32               reg_addr //target addr to be readback
 316  *            u32               bitmask  //taget bit pos to be readback
 317  * output:    none
 318  * return:    u32               data     //the readback register value
 319  * notice:
 320  *****************************************************************************/
 321 u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
 322                            enum rf90_radio_path_e e_rfpath,
 323                            u32 reg_addr, u32 bitmask)
 324 {
 325         u32 reg, bitshift;
 326         struct r8192_priv *priv = ieee80211_priv(dev);
 327
 328         if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
 329                 return 0;
 330         if (priv->Rf_Mode == RF_OP_By_FW) {
 331                 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
 332                 udelay(200);
 333         } else {
 334                 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
 335         }
 336         bitshift =  ffs(bitmask) - 1;
 337         reg = (reg & bitmask) >> bitshift;
 338         return reg;
 339 }
 340
 341 /******************************************************************************
 342  * function:  We support firmware to execute RF-R/W.
 343  * input:     net_device        *dev
 344  *            rf90_radio_path_e e_rfpath
 345  *            u32               offset
 346  * output:    none
 347  * return:    u32
 348  * notice:
 349  ****************************************************************************/
 350 static u32 phy_FwRFSerialRead(struct net_device *dev,
 351                               enum rf90_radio_path_e e_rfpath,
 352                               u32 offset)
 353 {
 354         u32             reg = 0;
 355         u32             data = 0;
 356         u8              time = 0;
 357         u32             tmp;
 358
 359         /* Firmware RF Write control.
 360          * We can not execute the scheme in the initial step.
 361          * Otherwise, RF-R/W will waste much time.
 362          * This is only for site survey.
 363          */
 364         /* 1. Read operation need not insert data. bit 0-11 */
 365         /* 2. Write RF register address. bit 12-19 */
 366         data |= ((offset&0xFF)<<12);
 367         /* 3. Write RF path.  bit 20-21 */
 368         data |= ((e_rfpath&0x3)<<20);
 369         /* 4. Set RF read indicator. bit 22=0 */
 370         /* 5. Trigger Fw to operate the command. bit 31 */
 371         data |= 0x80000000;
 372         /* 6. We can not execute read operation if bit 31 is 1. */
 373         read_nic_dword(dev, QPNR, &tmp);
 374         while (tmp & 0x80000000) {
 375                 /* If FW can not finish RF-R/W for more than ?? times.
 376                  * We must reset FW.
 377                  */
 378                 if (time++ < 100) {
 379                         udelay(10);
 380                         read_nic_dword(dev, QPNR, &tmp);
 381                 } else {
 382                         break;
 383                 }
 384         }
 385         /* 7. Execute read operation. */
 386         write_nic_dword(dev, QPNR, data);
 387         /* 8. Check if firmware send back RF content. */
 388         read_nic_dword(dev, QPNR, &tmp);
 389         while (tmp & 0x80000000) {
 390                 /* If FW can not finish RF-R/W for more than ?? times.
 391                  * We must reset FW.
 392                  */
 393                 if (time++ < 100) {
 394                         udelay(10);
 395                         read_nic_dword(dev, QPNR, &tmp);
 396                 } else {
 397                         return 0;
 398                 }
 399         }
 400         read_nic_dword(dev, RF_DATA, &reg);
 401
 402         return reg;
 403 }
 404
 405 /******************************************************************************
 406  * function:  We support firmware to execute RF-R/W.
 407  * input:     net_device        *dev
 408  *            rf90_radio_path_e e_rfpath
 409  *            u32               offset
 410  *            u32               data
 411  * output:    none
 412  * return:    none
 413  * notice:
 414  ****************************************************************************/
 415 static void phy_FwRFSerialWrite(struct net_device *dev,
 416                                 enum rf90_radio_path_e e_rfpath,
 417                                 u32 offset, u32 data)
 418 {
 419         u8      time = 0;
 420         u32     tmp;
 421
 422         /* Firmware RF Write control.
 423          * We can not execute the scheme in the initial step.
 424          * Otherwise, RF-R/W will waste much time.
 425          * This is only for site survey.
 426          */
 427
 428         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 429         /* 2. Write RF register address. bit 12-19 */
 430         data |= ((offset&0xFF)<<12);
 431         /* 3. Write RF path.  bit 20-21 */
 432         data |= ((e_rfpath&0x3)<<20);
 433         /* 4. Set RF write indicator. bit 22=1 */
 434         data |= 0x400000;
 435         /* 5. Trigger Fw to operate the command. bit 31=1 */
 436         data |= 0x80000000;
 437
 438         /* 6. Write operation. We can not write if bit 31 is 1. */
 439         read_nic_dword(dev, QPNR, &tmp);
 440         while (tmp & 0x80000000) {
 441                 /* If FW can not finish RF-R/W for more than ?? times.
 442                  * We must reset FW.
 443                  */
 444                 if (time++ < 100) {
 445                         udelay(10);
 446                         read_nic_dword(dev, QPNR, &tmp);
 447                 } else {
 448                         break;
 449                 }
 450         }
 451         /* 7. No matter check bit. We always force the write.
 452          * Because FW will not accept the command.
 453          */
 454         write_nic_dword(dev, QPNR, data);
 455         /* According to test, we must delay 20us to wait firmware
 456          * to finish RF write operation.
 457          */
 458         /* We support delay in firmware side now. */
 459 }
 460
 461 /******************************************************************************
 462  * function:  This function reads BB parameters from header file we generate,
 463  *            and do register read/write
 464  * input:     net_device        *dev
 465  * output:    none
 466  * return:    none
 467  * notice:    BB parameters may change all the time, so please make
 468  *            sure it has been synced with the newest.
 469  *****************************************************************************/
 470 void rtl8192_phy_configmac(struct net_device *dev)
 471 {
 472         u32 dwArrayLen = 0, i;
 473         u32 *pdwArray = NULL;
 474         struct r8192_priv *priv = ieee80211_priv(dev);
 475
 476         if (priv->btxpowerdata_readfromEEPORM) {
 477                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 478                 dwArrayLen = MACPHY_Array_PGLength;
 479                 pdwArray = Rtl8192UsbMACPHY_Array_PG;
 480
 481         } else {
 482                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 483                 dwArrayLen = MACPHY_ArrayLength;
 484                 pdwArray = rtl819XMACPHY_Array;
 485         }
 486         for (i = 0; i < dwArrayLen; i = i+3) {
 487                 if (pdwArray[i] == 0x318)
 488                         pdwArray[i+2] = 0x00000800;
 489
 490                 RT_TRACE(COMP_DBG,
 491                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 492                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 493                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 494                                  pdwArray[i+2]);
 495         }
 496 }
 497
 498 /******************************************************************************
 499  * function:  This function does dirty work
 500  * input:     net_device        *dev
 501  *            u8                ConfigType
 502  * output:    none
 503  * return:    none
 504  * notice:    BB parameters may change all the time, so please make
 505  *            sure it has been synced with the newest.
 506  *****************************************************************************/
 507 static void rtl8192_phyConfigBB(struct net_device *dev,
 508                                 enum baseband_config_type ConfigType)
 509 {
 510         u32 i;
 511
 512         if (ConfigType == BASEBAND_CONFIG_PHY_REG) {
 513                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 514                         rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i],
 515                                          bMaskDWord,
 516                                          Rtl8192UsbPHY_REG_1T2RArray[i+1]);
 517                         RT_TRACE(COMP_DBG,
 518                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 519                                  i, Rtl8192UsbPHY_REG_1T2RArray[i],
 520                                  Rtl8192UsbPHY_REG_1T2RArray[i+1]);
 521                 }
 522         } else if (ConfigType == BASEBAND_CONFIG_AGC_TAB) {
 523                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 524                         rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i],
 525                                          bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]);
 526                         RT_TRACE(COMP_DBG,
 527                                  "i: %x, Rtl8192UsbAGCTAB_Array[0]=%x Rtl8192UsbAGCTAB_Array[1]=%x\n",
 528                                  i, Rtl8192UsbAGCTAB_Array[i],
 529                                  Rtl8192UsbAGCTAB_Array[i+1]);
 530                 }
 531         }
 532 }
 533
 534 /******************************************************************************
 535  * function:  This function initializes Register definition offset for
 536  *            Radio Path A/B/C/D
 537  * input:     net_device        *dev
 538  * output:    none
 539  * return:    none
 540  * notice:    Initialization value here is constant and it should never
 541  *            be changed
 542  *****************************************************************************/
 543 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
 544 {
 545         struct r8192_priv *priv = ieee80211_priv(dev);
 546
 547         /* RF Interface Software Control */
 548         /* 16 LSBs if read 32-bit from 0x870 */
 549         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 550         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 551         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 552         /* 16 LSBs if read 32-bit from 0x874 */
 553         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 554         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 555         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 556
 557         /* RF Interface Readback Value */
 558         /* 16 LSBs if read 32-bit from 0x8E0 */
 559         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 560         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 561         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 562         /* 16 LSBs if read 32-bit from 0x8E4 */
 563         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 564         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 565         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 566
 567         /* RF Interface Output (and Enable) */
 568         /* 16 LSBs if read 32-bit from 0x860 */
 569         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 570         /* 16 LSBs if read 32-bit from 0x864 */
 571         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 572         /* 16 LSBs if read 32-bit from 0x868 */
 573         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 574         /* 16 LSBs if read 32-bit from 0x86C */
 575         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 576
 577         /* RF Interface (Output and) Enable */
 578         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 579         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 580         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 581         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 582         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 583         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 584         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 585         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 586
 587         /* Addr of LSSI. Write RF register by driver */
 588         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 589         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 590         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 591         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 592
 593         /* RF parameter */
 594         /* BB Band Select */
 595         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 596         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 597         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 598         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 599
 600         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 601         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 602         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 603         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 604         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 605
 606         /* Tranceiver A~D HSSI Parameter-1 */
 607         /* wire control parameter1 */
 608         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 609         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 610         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 611         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 612
 613         /* Tranceiver A~D HSSI Parameter-2 */
 614         /* wire control parameter2 */
 615         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 616         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 617         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 618         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 619
 620         /* RF Switch Control */
 621         /* TR/Ant switch control */
 622         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 623         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 624         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 625         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 626
 627         /* AGC control 1 */
 628         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 629         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 630         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 631         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 632
 633         /* AGC control 2 */
 634         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 635         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 636         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 637         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 638
 639         /* RX AFE control 1 */
 640         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 641         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 642         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 643         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 644
 645         /* RX AFE control 1 */
 646         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 647         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 648         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 649         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 650
 651         /* Tx AFE control 1 */
 652         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 653         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 654         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 655         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 656
 657         /* Tx AFE control 2 */
 658         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 659         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 660         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 661         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 662
 663         /* Tranceiver LSSI Readback */
 664         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 665         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 666         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 667         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 668 }
 669
 670 /******************************************************************************
 671  * function:  This function is to write register and then readback to make
 672  *            sure whether BB and RF is OK
 673  * input:     net_device        *dev
 674  *            hw90_block_e      CheckBlock
 675  *            rf90_radio_path_e e_rfpath  //only used when checkblock is
 676  *                                       //HW90_BLOCK_RF
 677  * output:    none
 678  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 679  * notice:    This function may be removed in the ASIC
 680  ******************************************************************************/
 681 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block_e CheckBlock,
 682                             enum rf90_radio_path_e e_rfpath)
 683 {
 684         u8 ret = 0;
 685         u32 i, CheckTimes = 4, reg = 0;
 686         u32 WriteAddr[4];
 687         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 688
 689         /* Initialize register address offset to be checked */
 690         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 691         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 692         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 693         WriteAddr[HW90_BLOCK_RF] = 0x3;
 694         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
 695         for (i = 0; i < CheckTimes; i++) {
 696                 /* Write data to register and readback */
 697                 switch (CheckBlock) {
 698                 case HW90_BLOCK_MAC:
 699                         RT_TRACE(COMP_ERR,
 700                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
 701                         break;
 702
 703                 case HW90_BLOCK_PHY0:
 704                 case HW90_BLOCK_PHY1:
 705                         write_nic_dword(dev, WriteAddr[CheckBlock],
 706                                         WriteData[i]);
 707                         read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
 708                         break;
 709
 710                 case HW90_BLOCK_RF:
 711                         WriteData[i] &= 0xfff;
 712                         rtl8192_phy_SetRFReg(dev, e_rfpath,
 713                                              WriteAddr[HW90_BLOCK_RF],
 714                                              bMask12Bits, WriteData[i]);
 715                         /* TODO: we should not delay for such a long time.
 716                          * Ask SD3
 717                          */
 718                         usleep_range(1000, 1000);
 719                         reg = rtl8192_phy_QueryRFReg(dev, e_rfpath,
 720                                                      WriteAddr[HW90_BLOCK_RF],
 721                                                      bMask12Bits);
 722                         usleep_range(1000, 1000);
 723                         break;
 724
 725                 default:
 726                         ret = 1;
 727                         break;
 728                 }
 729
 730                 /* Check whether readback data is correct */
 731                 if (reg != WriteData[i]) {
 732                         RT_TRACE((COMP_PHY|COMP_ERR),
 733                                  "error reg: %x, WriteData: %x\n",
 734                                  reg, WriteData[i]);
 735                         ret = 1;
 736                         break;
 737                 }
 738         }
 739
 740         return ret;
 741 }
 742
 743 /******************************************************************************
 744  * function:  This function initializes BB&RF
 745  * input:     net_device        *dev
 746  * output:    none
 747  * return:    none
 748  * notice:    Initialization value may change all the time, so please make
 749  *            sure it has been synced with the newest.
 750  ******************************************************************************/
 751 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 752 {
 753         struct r8192_priv *priv = ieee80211_priv(dev);
 754         u8 reg_u8 = 0, eCheckItem = 0, status = 0;
 755         u32 reg_u32 = 0;
 756
 757         /**************************************
 758          * <1> Initialize BaseBand
 759          *************************************/
 760
 761         /* --set BB Global Reset-- */
 762         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 763         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 764         mdelay(50);
 765         /* ---set BB reset Active--- */
 766         read_nic_dword(dev, CPU_GEN, &reg_u32);
 767         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 768
 769         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 770         /* TODO: this function should be removed on ASIC */
 771         for (eCheckItem = (enum hw90_block_e)HW90_BLOCK_PHY0;
 772              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 773                 /* don't care RF path */
 774                 status = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block_e)eCheckItem,
 775                                                   (enum rf90_radio_path_e)0);
 776                 if (status != 0) {
 777                         RT_TRACE((COMP_ERR | COMP_PHY),
 778                                  "phy_rf8256_config(): Check PHY%d Fail!!\n",
 779                                  eCheckItem-1);
 780                         return;
 781                 }
 782         }
 783         /* ---- Set CCK and OFDM Block "OFF"---- */
 784         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 785         /* ----BB Register Initilazation---- */
 786         /* ==m==>Set PHY REG From Header<==m== */
 787         rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_PHY_REG);
 788
 789         /* ----Set BB reset de-Active---- */
 790         read_nic_dword(dev, CPU_GEN, &reg_u32);
 791         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 792
 793         /* ----BB AGC table Initialization---- */
 794         /* ==m==>Set PHY REG From Header<==m== */
 795         rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_AGC_TAB);
 796
 797         /* ----Enable XSTAL ---- */
 798         write_nic_byte_E(dev, 0x5e, 0x00);
 799         if (priv->card_8192_version == VERSION_819XU_A) {
 800                 /* Antenna gain offset from B/C/D to A */
 801                 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
 802                            priv->AntennaTxPwDiff[0];
 803                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 804                                  reg_u32);
 805
 806                 /* XSTALLCap */
 807                 reg_u32 = priv->CrystalCap & 0xf;
 808                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 809                                  reg_u32);
 810         }
 811
 812         /* Check if the CCK HighPower is turned ON.
 813          * This is used to calculate PWDB.
 814          */
 815         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 816                                                      rFPGA0_XA_HSSIParameter2,
 817                                                      0x200);
 818 }
 819
 820 /******************************************************************************
 821  * function:  This function initializes BB&RF
 822  * input:     net_device        *dev
 823  * output:    none
 824  * return:    none
 825  * notice:    Initialization value may change all the time, so please make
 826  *            sure it has been synced with the newest.
 827  *****************************************************************************/
 828 void rtl8192_BBConfig(struct net_device *dev)
 829 {
 830         rtl8192_InitBBRFRegDef(dev);
 831         /* config BB&RF. As hardCode based initialization has not been well
 832          * implemented, so use file first.
 833          * FIXME: should implement it for hardcode?
 834          */
 835         rtl8192_BB_Config_ParaFile(dev);
 836 }
 837
 838 /******************************************************************************
 839  * function:  This function obtains the initialization value of Tx power Level
 840  *            offset
 841  * input:     net_device        *dev
 842  * output:    none
 843  * return:    none
 844  *****************************************************************************/
 845 void rtl8192_phy_getTxPower(struct net_device *dev)
 846 {
 847         struct r8192_priv *priv = ieee80211_priv(dev);
 848         u8 tmp;
 849
 850         read_nic_dword(dev, rTxAGC_Rate18_06,
 851                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 852         read_nic_dword(dev, rTxAGC_Rate54_24,
 853                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 854         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 855                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 856         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 857                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 858         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 859                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 860         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 861                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 862
 863         /* Read rx initial gain */
 864         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 865         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 866         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 867         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 868         RT_TRACE(COMP_INIT,
 869                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 870                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 871                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 872
 873         /* Read framesync */
 874         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 875         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 876         priv->framesyncC34 = tmp;
 877         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
 878                 rOFDM0_RxDetector3, priv->framesync);
 879
 880         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 881         read_nic_word(dev, SIFS, &priv->SifsTime);
 882 }
 883
 884 /******************************************************************************
 885  * function:  This function sets the initialization value of Tx power Level
 886  *            offset
 887  * input:     net_device        *dev
 888  *            u8                channel
 889  * output:    none
 890  * return:    none
 891  ******************************************************************************/
 892 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 893 {
 894         struct r8192_priv *priv = ieee80211_priv(dev);
 895         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 896         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 897
 898         switch (priv->rf_chip) {
 899         case RF_8256:
 900                 /* need further implement */
 901                 phy_set_rf8256_cck_tx_power(dev, powerlevel);
 902                 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G);
 903                 break;
 904         default:
 905                 RT_TRACE((COMP_PHY|COMP_ERR),
 906                          "error RF chipID(8225 or 8258) in function %s()\n",
 907                          __func__);
 908                 break;
 909         }
 910 }
 911
 912 /******************************************************************************
 913  * function:  This function checks Rf chip to do RF config
 914  * input:     net_device        *dev
 915  * output:    none
 916  * return:    only 8256 is supported
 917  ******************************************************************************/
 918 void rtl8192_phy_RFConfig(struct net_device *dev)
 919 {
 920         struct r8192_priv *priv = ieee80211_priv(dev);
 921
 922         switch (priv->rf_chip) {
 923         case RF_8256:
 924                 phy_rf8256_config(dev);
 925                 break;
 926         default:
 927                 RT_TRACE(COMP_ERR, "error chip id\n");
 928                 break;
 929         }
 930 }
 931
 932 /******************************************************************************
 933  * function:  This function updates Initial gain
 934  * input:     net_device        *dev
 935  * output:    none
 936  * return:    As Windows has not implemented this, wait for complement
 937  ******************************************************************************/
 938 void rtl8192_phy_updateInitGain(struct net_device *dev)
 939 {
 940 }
 941
 942 /******************************************************************************
 943  * function:  This function read RF parameters from general head file,
 944  *            and do RF 3-wire
 945  * input:     net_device        *dev
 946  *            rf90_radio_path_e e_rfpath
 947  * output:    none
 948  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 949  * notice:    Delay may be required for RF configuration
 950  *****************************************************************************/
 951 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 952                                       enum rf90_radio_path_e    e_rfpath)
 953 {
 954         int i;
 955
 956         switch (e_rfpath) {
 957         case RF90_PATH_A:
 958                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
 959                         if (Rtl8192UsbRadioA_Array[i] == 0xfe) {
 960                                 mdelay(100);
 961                                 continue;
 962                         }
 963                         rtl8192_phy_SetRFReg(dev, e_rfpath,
 964                                              Rtl8192UsbRadioA_Array[i],
 965                                              bMask12Bits,
 966                                              Rtl8192UsbRadioA_Array[i+1]);
 967                         mdelay(1);
 968                 }
 969                 break;
 970         case RF90_PATH_B:
 971                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
 972                         if (Rtl8192UsbRadioB_Array[i] == 0xfe) {
 973                                 mdelay(100);
 974                                 continue;
 975                         }
 976                         rtl8192_phy_SetRFReg(dev, e_rfpath,
 977                                              Rtl8192UsbRadioB_Array[i],
 978                                              bMask12Bits,
 979                                              Rtl8192UsbRadioB_Array[i+1]);
 980                         mdelay(1);
 981                 }
 982                 break;
 983         case RF90_PATH_C:
 984                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
 985                         if (Rtl8192UsbRadioC_Array[i] == 0xfe) {
 986                                 mdelay(100);
 987                                 continue;
 988                         }
 989                         rtl8192_phy_SetRFReg(dev, e_rfpath,
 990                                              Rtl8192UsbRadioC_Array[i],
 991                                              bMask12Bits,
 992                                              Rtl8192UsbRadioC_Array[i+1]);
 993                         mdelay(1);
 994                 }
 995                 break;
 996         case RF90_PATH_D:
 997                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
 998                         if (Rtl8192UsbRadioD_Array[i] == 0xfe) {
 999                                 mdelay(100);
1000                                 continue;
1001                         }
1002                         rtl8192_phy_SetRFReg(dev, e_rfpath,
1003                                              Rtl8192UsbRadioD_Array[i],
1004                                              bMask12Bits,
1005                                              Rtl8192UsbRadioD_Array[i+1]);
1006                         mdelay(1);
1007                 }
1008                 break;
1009         default:
1010                 break;
1011         }
1012
1013         return 0;
1014 }
1015
1016 /******************************************************************************
1017  * function:  This function sets Tx Power of the channel
1018  * input:     net_device        *dev
1019  *            u8                channel
1020  * output:    none
1021  * return:    none
1022  * notice:
1023  ******************************************************************************/
1024 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1025 {
1026         struct r8192_priv *priv = ieee80211_priv(dev);
1027         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1028         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1029
1030         switch (priv->rf_chip) {
1031         case RF_8225:
1032                 break;
1033
1034         case RF_8256:
1035                 phy_set_rf8256_cck_tx_power(dev, powerlevel);
1036                 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G);
1037                 break;
1038
1039         case RF_8258:
1040                 break;
1041         default:
1042                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1043                 break;
1044         }
1045 }
1046
1047 /******************************************************************************
1048  * function:  This function sets RF state on or off
1049  * input:     net_device         *dev
1050  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1051  * output:    none
1052  * return:    none
1053  * notice:
1054  *****************************************************************************/
1055 bool rtl8192_SetRFPowerState(struct net_device *dev,
1056                              RT_RF_POWER_STATE eRFPowerState)
1057 {
1058         bool                            bResult = true;
1059         struct r8192_priv *priv = ieee80211_priv(dev);
1060
1061         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1062                 return false;
1063
1064         if (priv->SetRFPowerStateInProgress)
1065                 return false;
1066
1067         priv->SetRFPowerStateInProgress = true;
1068
1069         switch (priv->rf_chip) {
1070         case RF_8256:
1071                 switch (eRFPowerState) {
1072                 case eRfOn:
1073                         /* RF-A, RF-B */
1074                         /* enable RF-Chip A/B - 0x860[4] */
1075                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1076                                          0x1);
1077                         /* analog to digital on - 0x88c[9:8] */
1078                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1079                                          0x3);
1080                         /* digital to analog on - 0x880[4:3] */
1081                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1082                                          0x3);
1083                         /* rx antenna on - 0xc04[1:0] */
1084                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1085                         /* rx antenna on - 0xd04[1:0] */
1086                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1087                         /* analog to digital part2 on - 0x880[6:5] */
1088                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1089                                          0x3);
1090
1091                         break;
1092
1093                 case eRfSleep:
1094
1095                         break;
1096
1097                 case eRfOff:
1098                         /* RF-A, RF-B */
1099                         /* disable RF-Chip A/B - 0x860[4] */
1100                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1101                                          0x0);
1102                         /* analog to digital off, for power save */
1103                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1104                                          0x0); /* 0x88c[11:8] */
1105                         /* digital to analog off, for power save - 0x880[4:3] */
1106                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1107                                          0x0);
1108                         /* rx antenna off - 0xc04[3:0] */
1109                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1110                         /* rx antenna off - 0xd04[3:0] */
1111                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1112                         /* analog to digital part2 off, for power save */
1113                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1114                                          0x0); /* 0x880[6:5] */
1115
1116                         break;
1117
1118                 default:
1119                         bResult = false;
1120                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1121                                  __func__, eRFPowerState);
1122                         break;
1123                 }
1124                 break;
1125         default:
1126                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1127                 break;
1128         }
1129         priv->SetRFPowerStateInProgress = false;
1130
1131         return bResult;
1132 }
1133
1134 /******************************************************************************
1135  * function:  This function sets command table variable (struct sw_chnl_cmd).
1136  * input:     sw_chnl_cmd      *CmdTable    //table to be set
1137  *            u32            CmdTableIdx  //variable index in table to be set
1138  *            u32            CmdTableSz   //table size
1139  *            switch_chan_cmd_id    CmdID        //command ID to set
1140  *            u32            Para1
1141  *            u32            Para2
1142  *            u32            msDelay
1143  * output:
1144  * return:    true if finished, false otherwise
1145  * notice:
1146  ******************************************************************************/
1147 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx,
1148                                         u32 CmdTableSz, enum switch_chan_cmd_id CmdID,
1149                                         u32 Para1, u32 Para2, u32 msDelay)
1150 {
1151         struct sw_chnl_cmd *pCmd;
1152
1153         if (!CmdTable) {
1154                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1155                 return false;
1156         }
1157         if (CmdTableIdx >= CmdTableSz) {
1158                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1159                          __func__, CmdTableIdx, CmdTableSz);
1160                 return false;
1161         }
1162
1163         pCmd = CmdTable + CmdTableIdx;
1164         pCmd->cmd_id = CmdID;
1165         pCmd->para_1 = Para1;
1166         pCmd->para_2 = Para2;
1167         pCmd->ms_delay = msDelay;
1168
1169         return true;
1170 }
1171
1172 /******************************************************************************
1173  * function:  This function sets channel step by step
1174  * input:     net_device        *dev
1175  *            u8                channel
1176  *            u8                *stage   //3 stages
1177  *            u8                *step
1178  *            u32               *delay   //whether need to delay
1179  * output:    store new stage, step and delay for next step
1180  *            (combine with function above)
1181  * return:    true if finished, false otherwise
1182  * notice:    Wait for simpler function to replace it
1183  *****************************************************************************/
1184 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1185                                        u8 *stage, u8 *step, u32 *delay)
1186 {
1187         struct r8192_priv *priv = ieee80211_priv(dev);
1188         struct sw_chnl_cmd   PreCommonCmd[MAX_PRECMD_CNT];
1189         u32                PreCommonCmdCnt;
1190         struct sw_chnl_cmd   PostCommonCmd[MAX_POSTCMD_CNT];
1191         u32                PostCommonCmdCnt;
1192         struct sw_chnl_cmd   RfDependCmd[MAX_RFDEPENDCMD_CNT];
1193         u32                RfDependCmdCnt;
1194         struct sw_chnl_cmd  *CurrentCmd = NULL;
1195         u8                 e_rfpath;
1196
1197         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1198                  __func__, *stage, *step, channel);
1199         if (!is_legal_channel(priv->ieee80211, channel)) {
1200                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1201                 /* return true to tell upper caller function this channel
1202                  * setting is finished! Or it will in while loop.
1203                  */
1204                 return true;
1205         }
1206         /* FIXME: need to check whether channel is legal or not here */
1207
1208         /* <1> Fill up pre common command. */
1209         PreCommonCmdCnt = 0;
1210         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1211                                       MAX_PRECMD_CNT, CMD_ID_SET_TX_PWR_LEVEL,
1212                                       0, 0, 0);
1213         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1214                                       MAX_PRECMD_CNT, CMD_ID_END, 0, 0, 0);
1215
1216         /* <2> Fill up post common command. */
1217         PostCommonCmdCnt = 0;
1218
1219         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1220                                       MAX_POSTCMD_CNT, CMD_ID_END, 0, 0, 0);
1221
1222         /* <3> Fill up RF dependent command. */
1223         RfDependCmdCnt = 0;
1224         switch (priv->rf_chip) {
1225         case RF_8225:
1226                 if (!(channel >= 1 && channel <= 14)) {
1227                         RT_TRACE(COMP_ERR,
1228                                  "illegal channel for Zebra 8225: %d\n",
1229                                  channel);
1230                         return true;
1231                 }
1232                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1233                                               MAX_RFDEPENDCMD_CNT,
1234                                               CMD_ID_RF_WRITE_REG,
1235                                               rZebra1_Channel,
1236                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1237                                               10);
1238                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1239                                               MAX_RFDEPENDCMD_CNT,
1240                                               CMD_ID_END, 0, 0, 0);
1241                 break;
1242
1243         case RF_8256:
1244                 /* TEST!! This is not the table for 8256!! */
1245                 if (!(channel >= 1 && channel <= 14)) {
1246                         RT_TRACE(COMP_ERR,
1247                                  "illegal channel for Zebra 8256: %d\n",
1248                                  channel);
1249                         return true;
1250                 }
1251                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1252                                               MAX_RFDEPENDCMD_CNT,
1253                                               CMD_ID_RF_WRITE_REG,
1254                                               rZebra1_Channel, channel, 10);
1255                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1256                                               MAX_RFDEPENDCMD_CNT,
1257                                               CMD_ID_END, 0, 0, 0);
1258                 break;
1259
1260         case RF_8258:
1261                 break;
1262
1263         default:
1264                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1265                 return true;
1266         }
1267
1268         do {
1269                 switch (*stage) {
1270                 case 0:
1271                         CurrentCmd = &PreCommonCmd[*step];
1272                         break;
1273                 case 1:
1274                         CurrentCmd = &RfDependCmd[*step];
1275                         break;
1276                 case 2:
1277                         CurrentCmd = &PostCommonCmd[*step];
1278                         break;
1279                 }
1280
1281                 if (CurrentCmd->cmd_id == CMD_ID_END) {
1282                         if ((*stage) == 2) {
1283                                 (*delay) = CurrentCmd->ms_delay;
1284                                 return true;
1285                         }
1286                         (*stage)++;
1287                         (*step) = 0;
1288                         continue;
1289                 }
1290
1291                 switch (CurrentCmd->cmd_id) {
1292                 case CMD_ID_SET_TX_PWR_LEVEL:
1293                         if (priv->card_8192_version == VERSION_819XU_A)
1294                                 /* consider it later! */
1295                                 rtl8192_SetTxPowerLevel(dev, channel);
1296                         break;
1297                 case CMD_ID_WRITE_PORT_ULONG:
1298                         write_nic_dword(dev, CurrentCmd->para_1,
1299                                         CurrentCmd->para_2);
1300                         break;
1301                 case CMD_ID_WRITE_PORT_USHORT:
1302                         write_nic_word(dev, CurrentCmd->para_1,
1303                                        (u16)CurrentCmd->para_2);
1304                         break;
1305                 case CMD_ID_WRITE_PORT_UCHAR:
1306                         write_nic_byte(dev, CurrentCmd->para_1,
1307                                        (u8)CurrentCmd->para_2);
1308                         break;
1309                 case CMD_ID_RF_WRITE_REG:
1310                         for (e_rfpath = 0; e_rfpath < RF90_PATH_MAX; e_rfpath++) {
1311                                 rtl8192_phy_SetRFReg(dev,
1312                                                      (enum rf90_radio_path_e)e_rfpath,
1313                                                      CurrentCmd->para_1,
1314                                                      bZebra1_ChannelNum,
1315                                                      CurrentCmd->para_2);
1316                         }
1317                         break;
1318                 default:
1319                         break;
1320                 }
1321
1322                 break;
1323         } while (true);
1324
1325         (*delay) = CurrentCmd->ms_delay;
1326         (*step)++;
1327         return false;
1328 }
1329
1330 /******************************************************************************
1331  * function:  This function does actually set channel work
1332  * input:     net_device        *dev
1333  *            u8                channel
1334  * output:    none
1335  * return:    none
1336  * notice:    We should not call this function directly
1337  *****************************************************************************/
1338 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1339 {
1340         struct r8192_priv *priv = ieee80211_priv(dev);
1341         u32     delay = 0;
1342
1343         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1344                                              &priv->SwChnlStep, &delay)) {
1345                 if (!priv->up)
1346                         break;
1347         }
1348 }
1349
1350 /******************************************************************************
1351  * function:  Callback routine of the work item for switch channel.
1352  * input:     net_device        *dev
1353  *
1354  * output:    none
1355  * return:    none
1356  *****************************************************************************/
1357 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1358 {
1359         struct r8192_priv *priv = ieee80211_priv(dev);
1360
1361         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1362                  priv->chan);
1363
1364         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1365
1366         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1367 }
1368
1369 /******************************************************************************
1370  * function:  This function scheduled actual work item to set channel
1371  * input:     net_device        *dev
1372  *            u8                channel   //channel to set
1373  * output:    none
1374  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1375  * notice:    Delay may be required for RF configuration
1376  ******************************************************************************/
1377 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1378 {
1379         struct r8192_priv *priv = ieee80211_priv(dev);
1380
1381         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1382                  priv->SwChnlInProgress);
1383         if (!priv->up)
1384                 return false;
1385         if (priv->SwChnlInProgress)
1386                 return false;
1387
1388         /* -------------------------------------------- */
1389         switch (priv->ieee80211->mode) {
1390         case WIRELESS_MODE_A:
1391         case WIRELESS_MODE_N_5G:
1392                 if (channel <= 14) {
1393                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1394                         return false;
1395                 }
1396                 break;
1397         case WIRELESS_MODE_B:
1398                 if (channel > 14) {
1399                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1400                         return false;
1401                 }
1402                 break;
1403         case WIRELESS_MODE_G:
1404         case WIRELESS_MODE_N_24G:
1405                 if (channel > 14) {
1406                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1407                         return false;
1408                 }
1409                 break;
1410         }
1411         /* -------------------------------------------- */
1412
1413         priv->SwChnlInProgress = true;
1414         if (channel == 0)
1415                 channel = 1;
1416
1417         priv->chan = channel;
1418
1419         priv->SwChnlStage = 0;
1420         priv->SwChnlStep = 0;
1421         if (priv->up)
1422                 rtl8192_SwChnl_WorkItem(dev);
1423
1424         priv->SwChnlInProgress = false;
1425         return true;
1426 }
1427
1428 /******************************************************************************
1429  * function:  Callback routine of the work item for set bandwidth mode.
1430  * input:     net_device         *dev
1431  * output:    none
1432  * return:    none
1433  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1434  *            test whether current work in the queue or not.//do I?
1435  *****************************************************************************/
1436 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1437 {
1438         struct r8192_priv *priv = ieee80211_priv(dev);
1439         u8 regBwOpMode;
1440
1441         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1442                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1443
1444         if (priv->rf_chip == RF_PSEUDO_11N) {
1445                 priv->SetBWModeInProgress = false;
1446                 return;
1447         }
1448
1449         /* <1> Set MAC register */
1450         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1451
1452         switch (priv->CurrentChannelBW) {
1453         case HT_CHANNEL_WIDTH_20:
1454                 regBwOpMode |= BW_OPMODE_20MHZ;
1455                 /* We have not verify whether this register works */
1456                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1457                 break;
1458
1459         case HT_CHANNEL_WIDTH_20_40:
1460                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1461                 /* We have not verify whether this register works */
1462                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1463                 break;
1464
1465         default:
1466                 RT_TRACE(COMP_ERR,
1467                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1468                          priv->CurrentChannelBW);
1469                 break;
1470         }
1471
1472         /* <2> Set PHY related register */
1473         switch (priv->CurrentChannelBW) {
1474         case HT_CHANNEL_WIDTH_20:
1475                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1476                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1477                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1478                                  0x00100000, 1);
1479
1480                 /* Correct the tx power for CCK rate in 20M. */
1481                 priv->cck_present_attenuation =
1482                         priv->cck_present_attenuation_20Mdefault +
1483                         priv->cck_present_attenuation_difference;
1484
1485                 if (priv->cck_present_attenuation > 22)
1486                         priv->cck_present_attenuation = 22;
1487                 if (priv->cck_present_attenuation < 0)
1488                         priv->cck_present_attenuation = 0;
1489                 RT_TRACE(COMP_INIT,
1490                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1491                          priv->cck_present_attenuation);
1492
1493                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1494                         priv->bcck_in_ch14 = true;
1495                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1496                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1497                         priv->bcck_in_ch14 = false;
1498                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1499                 } else {
1500                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1501                 }
1502
1503                 break;
1504         case HT_CHANNEL_WIDTH_20_40:
1505                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1506                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1507                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1508                                  priv->nCur40MhzPrimeSC >> 1);
1509                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1510                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1511                                  priv->nCur40MhzPrimeSC);
1512                 priv->cck_present_attenuation =
1513                         priv->cck_present_attenuation_40Mdefault +
1514                         priv->cck_present_attenuation_difference;
1515
1516                 if (priv->cck_present_attenuation > 22)
1517                         priv->cck_present_attenuation = 22;
1518                 if (priv->cck_present_attenuation < 0)
1519                         priv->cck_present_attenuation = 0;
1520
1521                 RT_TRACE(COMP_INIT,
1522                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1523                          priv->cck_present_attenuation);
1524                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1525                         priv->bcck_in_ch14 = true;
1526                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1527                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1528                         priv->bcck_in_ch14 = false;
1529                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1530                 } else {
1531                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1532                 }
1533
1534                 break;
1535         default:
1536                 RT_TRACE(COMP_ERR,
1537                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1538                          priv->CurrentChannelBW);
1539                 break;
1540         }
1541         /* Skip over setting of J-mode in BB register here.
1542          * Default value is "None J mode".
1543          */
1544
1545         /* <3> Set RF related register */
1546         switch (priv->rf_chip) {
1547         case RF_8225:
1548                 break;
1549
1550         case RF_8256:
1551                 phy_set_rf8256_bandwidth(dev, priv->CurrentChannelBW);
1552                 break;
1553
1554         case RF_8258:
1555                 break;
1556
1557         case RF_PSEUDO_11N:
1558                 break;
1559
1560         default:
1561                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1562                 break;
1563         }
1564         priv->SetBWModeInProgress = false;
1565
1566         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1567                  atomic_read(&priv->ieee80211->atm_swbw));
1568 }
1569
1570 /******************************************************************************
1571  * function:  This function schedules bandwidth switch work.
1572  * input:     struct net_deviceq   *dev
1573  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1574  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1575  * output:    none
1576  * return:    none
1577  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1578  *            test whether current work in the queue or not.//do I?
1579  *****************************************************************************/
1580 void rtl8192_SetBWMode(struct net_device *dev,
1581                        enum ht_channel_width bandwidth,
1582                        enum ht_extension_chan_offset offset)
1583 {
1584         struct r8192_priv *priv = ieee80211_priv(dev);
1585
1586         if (priv->SetBWModeInProgress)
1587                 return;
1588         priv->SetBWModeInProgress = true;
1589
1590         priv->CurrentChannelBW = bandwidth;
1591
1592         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1593                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1594         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1595                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1596         else
1597                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1598
1599         rtl8192_SetBWModeWorkItem(dev);
1600 }
1601
1602 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1603 {
1604         struct r8192_priv *priv = ieee80211_priv(dev);
1605
1606         priv->InitialGainOperateType = Operation;
1607
1608         if (priv->up)
1609                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1610 }
1611
1612 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1613 {
1614         struct delayed_work *dwork = to_delayed_work(work);
1615         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1616                                                initialgain_operate_wq);
1617         struct net_device *dev = priv->ieee80211->dev;
1618 #define SCAN_RX_INITIAL_GAIN    0x17
1619 #define POWER_DETECTION_TH      0x08
1620         u32     bitmask;
1621         u8      initial_gain;
1622         u8      Operation;
1623
1624         Operation = priv->InitialGainOperateType;
1625
1626         switch (Operation) {
1627         case IG_Backup:
1628                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1629                 initial_gain = SCAN_RX_INITIAL_GAIN;
1630                 bitmask = bMaskByte0;
1631                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1632                         /* FW DIG OFF */
1633                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1634                 priv->initgain_backup.xaagccore1 =
1635                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1636                 priv->initgain_backup.xbagccore1 =
1637                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1638                 priv->initgain_backup.xcagccore1 =
1639                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1640                 priv->initgain_backup.xdagccore1 =
1641                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1642                 bitmask = bMaskByte2;
1643                 priv->initgain_backup.cca =
1644                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1645
1646                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1647                          priv->initgain_backup.xaagccore1);
1648                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1649                          priv->initgain_backup.xbagccore1);
1650                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1651                          priv->initgain_backup.xcagccore1);
1652                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1653                          priv->initgain_backup.xdagccore1);
1654                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1655                          priv->initgain_backup.cca);
1656
1657                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1658                          initial_gain);
1659                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1660                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1661                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1662                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1663                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1664                          POWER_DETECTION_TH);
1665                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1666                 break;
1667         case IG_Restore:
1668                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1669                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1670                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1671                         /* FW DIG OFF */
1672                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1673
1674                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1675                                  (u32)priv->initgain_backup.xaagccore1);
1676                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1677                                  (u32)priv->initgain_backup.xbagccore1);
1678                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1679                                  (u32)priv->initgain_backup.xcagccore1);
1680                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1681                                  (u32)priv->initgain_backup.xdagccore1);
1682                 bitmask  = bMaskByte2;
1683                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1684                                  (u32)priv->initgain_backup.cca);
1685
1686                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1687                          priv->initgain_backup.xaagccore1);
1688                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1689                          priv->initgain_backup.xbagccore1);
1690                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1691                          priv->initgain_backup.xcagccore1);
1692                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1693                          priv->initgain_backup.xdagccore1);
1694                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1695                          priv->initgain_backup.cca);
1696
1697                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1698
1699                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1700                         /* FW DIG ON */
1701                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1702                 break;
1703         default:
1704                 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1705                 break;
1706         }
1707 }