drivers/staging/rtl8192u/r819xU_phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "r8192U.h"
   3 #include "r8192U_hw.h"
   4 #include "r819xU_phy.h"
   5 #include "r819xU_phyreg.h"
   6 #include "r8190_rtl8256.h"
   7 #include "r8192U_dm.h"
   8 #include "r819xU_firmware_img.h"
   9
  10 #include "dot11d.h"
  11 #include <linux/bitops.h>
  12
  13 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  14         0,
  15         0x085c, /* 2412 1  */
  16         0x08dc, /* 2417 2  */
  17         0x095c, /* 2422 3  */
  18         0x09dc, /* 2427 4  */
  19         0x0a5c, /* 2432 5  */
  20         0x0adc, /* 2437 6  */
  21         0x0b5c, /* 2442 7  */
  22         0x0bdc, /* 2447 8  */
  23         0x0c5c, /* 2452 9  */
  24         0x0cdc, /* 2457 10 */
  25         0x0d5c, /* 2462 11 */
  26         0x0ddc, /* 2467 12 */
  27         0x0e5c, /* 2472 13 */
  28         0x0f72, /* 2484    */
  29 };
  30
  31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  32
  33 /******************************************************************************
  34  * function:  This function checks different RF type to execute legal judgement.
  35  *            If RF Path is illegal, we will return false.
  36  * input:     net_device         *dev
  37  *            u32                e_rfpath
  38  * output:    none
  39  * return:    0(illegal, false), 1(legal, true)
  40  *****************************************************************************/
  41 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 e_rfpath)
  42 {
  43         u8 ret = 1;
  44         struct r8192_priv *priv = ieee80211_priv(dev);
  45
  46         if (priv->rf_type == RF_2T4R) {
  47                 ret = 0;
  48         } else if (priv->rf_type == RF_1T2R) {
  49                 if (e_rfpath == RF90_PATH_A || e_rfpath == RF90_PATH_B)
  50                         ret = 1;
  51                 else if (e_rfpath == RF90_PATH_C || e_rfpath == RF90_PATH_D)
  52                         ret = 0;
  53         }
  54         return ret;
  55 }
  56
  57 /******************************************************************************
  58  * function:  This function sets specific bits to BB register
  59  * input:     net_device *dev
  60  *            u32        reg_addr   //target addr to be modified
  61  *            u32        bitmask    //taget bit pos to be modified
  62  *            u32        data       //value to be write
  63  * output:    none
  64  * return:    none
  65  * notice:
  66  ******************************************************************************/
  67 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  68                       u32 data)
  69 {
  70
  71         u32 reg, bitshift;
  72
  73         if (bitmask != bMaskDWord) {
  74                 read_nic_dword(dev, reg_addr, &reg);
  75                 bitshift = ffs(bitmask) - 1;
  76                 reg &= ~bitmask;
  77                 reg |= data << bitshift;
  78                 write_nic_dword(dev, reg_addr, reg);
  79         } else {
  80                 write_nic_dword(dev, reg_addr, data);
  81         }
  82 }
  83
  84 /******************************************************************************
  85  * function:  This function reads specific bits from BB register
  86  * input:     net_device        *dev
  87  *            u32               reg_addr   //target addr to be readback
  88  *            u32               bitmask    //taget bit pos to be readback
  89  * output:    none
  90  * return:    u32               data       //the readback register value
  91  * notice:
  92  ******************************************************************************/
  93 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
  94 {
  95         u32 reg, bitshift;
  96
  97         read_nic_dword(dev, reg_addr, &reg);
  98         bitshift = ffs(bitmask) - 1;
  99
 100         return (reg & bitmask) >> bitshift;
 101 }
 102
 103 static u32 phy_FwRFSerialRead(struct net_device *dev,
 104                               enum rf90_radio_path_e e_rfpath,
 105                               u32 offset);
 106
 107 static void phy_FwRFSerialWrite(struct net_device *dev,
 108                                 enum rf90_radio_path_e e_rfpath,
 109                                 u32  offset,
 110                                 u32  data);
 111
 112 /******************************************************************************
 113  * function:  This function reads register from RF chip
 114  * input:     net_device        *dev
 115  *            rf90_radio_path_e e_rfpath    //radio path of A/B/C/D
 116  *            u32               offset     //target address to be read
 117  * output:    none
 118  * return:    u32               readback value
 119  * notice:    There are three types of serial operations:
 120  *            (1) Software serial write.
 121  *            (2)Hardware LSSI-Low Speed Serial Interface.
 122  *            (3)Hardware HSSI-High speed serial write.
 123  *            Driver here need to implement (1) and (2)
 124  *            ---need more spec for this information.
 125  ******************************************************************************/
 126 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
 127                                     enum rf90_radio_path_e e_rfpath, u32 offset)
 128 {
 129         struct r8192_priv *priv = ieee80211_priv(dev);
 130         u32 ret = 0;
 131         u32 new_offset = 0;
 132         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath];
 133
 134         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 135         /* Make sure RF register offset is correct */
 136         offset &= 0x3f;
 137
 138         /* Switch page for 8256 RF IC */
 139         if (priv->rf_chip == RF_8256) {
 140                 if (offset >= 31) {
 141                         priv->RfReg0Value[e_rfpath] |= 0x140;
 142                         /* Switch to Reg_Mode2 for Reg 31-45 */
 143                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 144                                          bMaskDWord,
 145                                          priv->RfReg0Value[e_rfpath]<<16);
 146                         /* Modify offset */
 147                         new_offset = offset - 30;
 148                 } else if (offset >= 16) {
 149                         priv->RfReg0Value[e_rfpath] |= 0x100;
 150                         priv->RfReg0Value[e_rfpath] &= (~0x40);
 151                         /* Switch to Reg_Mode1 for Reg16-30 */
 152                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 153                                          bMaskDWord,
 154                                          priv->RfReg0Value[e_rfpath]<<16);
 155
 156                         new_offset = offset - 15;
 157                 } else {
 158                         new_offset = offset;
 159                 }
 160         } else {
 161                 RT_TRACE((COMP_PHY|COMP_ERR),
 162                          "check RF type here, need to be 8256\n");
 163                 new_offset = offset;
 164         }
 165         /* Put desired read addr to LSSI control Register */
 166         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 167                          new_offset);
 168         /* Issue a posedge trigger */
 169         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 170         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 171
 172
 173         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 174         usleep_range(1000, 1000);
 175
 176         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 177                                  bLSSIReadBackData);
 178
 179
 180         /* Switch back to Reg_Mode0 */
 181         if (priv->rf_chip == RF_8256) {
 182                 priv->RfReg0Value[e_rfpath] &= 0xebf;
 183
 184                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 185                                  priv->RfReg0Value[e_rfpath] << 16);
 186         }
 187
 188         return ret;
 189 }
 190
 191 /******************************************************************************
 192  * function:  This function writes data to RF register
 193  * input:     net_device        *dev
 194  *            rf90_radio_path_e e_rfpath  //radio path of A/B/C/D
 195  *            u32               offset   //target address to be written
 196  *            u32               data     //the new register data to be written
 197  * output:    none
 198  * return:    none
 199  * notice:    For RF8256 only.
 200  * ===========================================================================
 201  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 202  *              (Reg00[12])     (Reg00[10])
 203  * ===========================================================================
 204  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 205  * ---------------------------------------------------------------------------
 206  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 207  * ---------------------------------------------------------------------------
 208  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 209  * ---------------------------------------------------------------------------
 210  *****************************************************************************/
 211 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 212                                       enum rf90_radio_path_e e_rfpath,
 213                                       u32 offset,
 214                                       u32 data)
 215 {
 216         struct r8192_priv *priv = ieee80211_priv(dev);
 217         u32 DataAndAddr = 0, new_offset = 0;
 218         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[e_rfpath];
 219
 220         offset &= 0x3f;
 221         if (priv->rf_chip == RF_8256) {
 222
 223                 if (offset >= 31) {
 224                         priv->RfReg0Value[e_rfpath] |= 0x140;
 225                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 226                                          bMaskDWord,
 227                                          priv->RfReg0Value[e_rfpath] << 16);
 228                         new_offset = offset - 30;
 229                 } else if (offset >= 16) {
 230                         priv->RfReg0Value[e_rfpath] |= 0x100;
 231                         priv->RfReg0Value[e_rfpath] &= (~0x40);
 232                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 233                                          bMaskDWord,
 234                                          priv->RfReg0Value[e_rfpath]<<16);
 235                         new_offset = offset - 15;
 236                 } else {
 237                         new_offset = offset;
 238                 }
 239         } else {
 240                 RT_TRACE((COMP_PHY|COMP_ERR),
 241                          "check RF type here, need to be 8256\n");
 242                 new_offset = offset;
 243         }
 244
 245         /* Put write addr in [5:0] and write data in [31:16] */
 246         DataAndAddr = (data<<16) | (new_offset&0x3f);
 247
 248         /* Write operation */
 249         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 250
 251
 252         if (offset == 0x0)
 253                 priv->RfReg0Value[e_rfpath] = data;
 254
 255         /* Switch back to Reg_Mode0 */
 256         if (priv->rf_chip == RF_8256) {
 257                 if (offset != 0) {
 258                         priv->RfReg0Value[e_rfpath] &= 0xebf;
 259                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 260                                          bMaskDWord,
 261                                          priv->RfReg0Value[e_rfpath] << 16);
 262                 }
 263         }
 264 }
 265
 266 /******************************************************************************
 267  * function:  This function set specific bits to RF register
 268  * input:     net_device        dev
 269  *            rf90_radio_path_e e_rfpath  //radio path of A/B/C/D
 270  *            u32               reg_addr //target addr to be modified
 271  *            u32               bitmask  //taget bit pos to be modified
 272  *            u32               data     //value to be written
 273  * output:    none
 274  * return:    none
 275  * notice:
 276  *****************************************************************************/
 277 void rtl8192_phy_SetRFReg(struct net_device *dev,
 278                           enum rf90_radio_path_e e_rfpath,
 279                           u32 reg_addr, u32 bitmask, u32 data)
 280 {
 281         struct r8192_priv *priv = ieee80211_priv(dev);
 282         u32 reg, bitshift;
 283
 284         if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
 285                 return;
 286
 287         if (priv->Rf_Mode == RF_OP_By_FW) {
 288                 if (bitmask != bMask12Bits) {
 289                         /* RF data is 12 bits only */
 290                         reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
 291                         bitshift =  ffs(bitmask) - 1;
 292                         reg &= ~bitmask;
 293                         reg |= data << bitshift;
 294
 295                         phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg);
 296                 } else {
 297                         phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, data);
 298                 }
 299
 300                 udelay(200);
 301
 302         } else {
 303                 if (bitmask != bMask12Bits) {
 304                         /* RF data is 12 bits only */
 305                         reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
 306                         bitshift =  ffs(bitmask) - 1;
 307                         reg &= ~bitmask;
 308                         reg |= data << bitshift;
 309
 310                         rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg);
 311                 } else {
 312                         rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, data);
 313                 }
 314         }
 315 }
 316
 317 /******************************************************************************
 318  * function:  This function reads specific bits from RF register
 319  * input:     net_device        *dev
 320  *            u32               reg_addr //target addr to be readback
 321  *            u32               bitmask  //taget bit pos to be readback
 322  * output:    none
 323  * return:    u32               data     //the readback register value
 324  * notice:
 325  *****************************************************************************/
 326 u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
 327                            enum rf90_radio_path_e e_rfpath,
 328                            u32 reg_addr, u32 bitmask)
 329 {
 330         u32 reg, bitshift;
 331         struct r8192_priv *priv = ieee80211_priv(dev);
 332
 333
 334         if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
 335                 return 0;
 336         if (priv->Rf_Mode == RF_OP_By_FW) {
 337                 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
 338                 udelay(200);
 339         } else {
 340                 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
 341         }
 342         bitshift =  ffs(bitmask) - 1;
 343         reg = (reg & bitmask) >> bitshift;
 344         return reg;
 345
 346 }
 347
 348 /******************************************************************************
 349  * function:  We support firmware to execute RF-R/W.
 350  * input:     net_device        *dev
 351  *            rf90_radio_path_e e_rfpath
 352  *            u32               offset
 353  * output:    none
 354  * return:    u32
 355  * notice:
 356  ****************************************************************************/
 357 static u32 phy_FwRFSerialRead(struct net_device *dev,
 358                               enum rf90_radio_path_e e_rfpath,
 359                               u32 offset)
 360 {
 361         u32             reg = 0;
 362         u32             data = 0;
 363         u8              time = 0;
 364         u32             tmp;
 365
 366         /* Firmware RF Write control.
 367          * We can not execute the scheme in the initial step.
 368          * Otherwise, RF-R/W will waste much time.
 369          * This is only for site survey.
 370          */
 371         /* 1. Read operation need not insert data. bit 0-11 */
 372         /* 2. Write RF register address. bit 12-19 */
 373         data |= ((offset&0xFF)<<12);
 374         /* 3. Write RF path.  bit 20-21 */
 375         data |= ((e_rfpath&0x3)<<20);
 376         /* 4. Set RF read indicator. bit 22=0 */
 377         /* 5. Trigger Fw to operate the command. bit 31 */
 378         data |= 0x80000000;
 379         /* 6. We can not execute read operation if bit 31 is 1. */
 380         read_nic_dword(dev, QPNR, &tmp);
 381         while (tmp & 0x80000000) {
 382                 /* If FW can not finish RF-R/W for more than ?? times.
 383                  * We must reset FW.
 384                  */
 385                 if (time++ < 100) {
 386                         udelay(10);
 387                         read_nic_dword(dev, QPNR, &tmp);
 388                 } else {
 389                         break;
 390                 }
 391         }
 392         /* 7. Execute read operation. */
 393         write_nic_dword(dev, QPNR, data);
 394         /* 8. Check if firmware send back RF content. */
 395         read_nic_dword(dev, QPNR, &tmp);
 396         while (tmp & 0x80000000) {
 397                 /* If FW can not finish RF-R/W for more than ?? times.
 398                  * We must reset FW.
 399                  */
 400                 if (time++ < 100) {
 401                         udelay(10);
 402                         read_nic_dword(dev, QPNR, &tmp);
 403                 } else {
 404                         return 0;
 405                 }
 406         }
 407         read_nic_dword(dev, RF_DATA, &reg);
 408
 409         return reg;
 410 }
 411
 412 /******************************************************************************
 413  * function:  We support firmware to execute RF-R/W.
 414  * input:     net_device        *dev
 415  *            rf90_radio_path_e e_rfpath
 416  *            u32               offset
 417  *            u32               data
 418  * output:    none
 419  * return:    none
 420  * notice:
 421  ****************************************************************************/
 422 static void phy_FwRFSerialWrite(struct net_device *dev,
 423                                 enum rf90_radio_path_e e_rfpath,
 424                                 u32 offset, u32 data)
 425 {
 426         u8      time = 0;
 427         u32     tmp;
 428
 429         /* Firmware RF Write control.
 430          * We can not execute the scheme in the initial step.
 431          * Otherwise, RF-R/W will waste much time.
 432          * This is only for site survey.
 433          */
 434
 435         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 436         /* 2. Write RF register address. bit 12-19 */
 437         data |= ((offset&0xFF)<<12);
 438         /* 3. Write RF path.  bit 20-21 */
 439         data |= ((e_rfpath&0x3)<<20);
 440         /* 4. Set RF write indicator. bit 22=1 */
 441         data |= 0x400000;
 442         /* 5. Trigger Fw to operate the command. bit 31=1 */
 443         data |= 0x80000000;
 444
 445         /* 6. Write operation. We can not write if bit 31 is 1. */
 446         read_nic_dword(dev, QPNR, &tmp);
 447         while (tmp & 0x80000000) {
 448                 /* If FW can not finish RF-R/W for more than ?? times.
 449                  * We must reset FW.
 450                  */
 451                 if (time++ < 100) {
 452                         udelay(10);
 453                         read_nic_dword(dev, QPNR, &tmp);
 454                 } else {
 455                         break;
 456                 }
 457         }
 458         /* 7. No matter check bit. We always force the write.
 459          * Because FW will not accept the command.
 460          */
 461         write_nic_dword(dev, QPNR, data);
 462         /* According to test, we must delay 20us to wait firmware
 463          * to finish RF write operation.
 464          */
 465         /* We support delay in firmware side now. */
 466 }
 467
 468 /******************************************************************************
 469  * function:  This function reads BB parameters from header file we generate,
 470  *            and do register read/write
 471  * input:     net_device        *dev
 472  * output:    none
 473  * return:    none
 474  * notice:    BB parameters may change all the time, so please make
 475  *            sure it has been synced with the newest.
 476  *****************************************************************************/
 477 void rtl8192_phy_configmac(struct net_device *dev)
 478 {
 479         u32 dwArrayLen = 0, i;
 480         u32 *pdwArray = NULL;
 481         struct r8192_priv *priv = ieee80211_priv(dev);
 482
 483         if (priv->btxpowerdata_readfromEEPORM) {
 484                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 485                 dwArrayLen = MACPHY_Array_PGLength;
 486                 pdwArray = Rtl8192UsbMACPHY_Array_PG;
 487
 488         } else {
 489                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 490                 dwArrayLen = MACPHY_ArrayLength;
 491                 pdwArray = rtl819XMACPHY_Array;
 492         }
 493         for (i = 0; i < dwArrayLen; i = i+3) {
 494                 if (pdwArray[i] == 0x318)
 495                         pdwArray[i+2] = 0x00000800;
 496
 497                 RT_TRACE(COMP_DBG,
 498                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 499                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 500                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 501                                  pdwArray[i+2]);
 502         }
 503 }
 504
 505 /******************************************************************************
 506  * function:  This function does dirty work
 507  * input:     net_device        *dev
 508  *            u8                ConfigType
 509  * output:    none
 510  * return:    none
 511  * notice:    BB parameters may change all the time, so please make
 512  *            sure it has been synced with the newest.
 513  *****************************************************************************/
 514 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 515 {
 516         u32 i;
 517
 518 #ifdef TO_DO_LIST
 519         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 520
 521         if (Adapter->bInHctTest) {
 522                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 523                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 524                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 525                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 526         }
 527 #endif
 528         if (ConfigType == BaseBand_Config_PHY_REG) {
 529                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 530                         rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i],
 531                                          bMaskDWord,
 532                                          Rtl8192UsbPHY_REG_1T2RArray[i+1]);
 533                         RT_TRACE(COMP_DBG,
 534                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 535                                  i, Rtl8192UsbPHY_REG_1T2RArray[i],
 536                                  Rtl8192UsbPHY_REG_1T2RArray[i+1]);
 537                 }
 538         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 539                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 540                         rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i],
 541                                          bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]);
 542                         RT_TRACE(COMP_DBG,
 543                                  "i: %x, Rtl8192UsbAGCTAB_Array[0]=%x Rtl8192UsbAGCTAB_Array[1]=%x\n",
 544                                  i, Rtl8192UsbAGCTAB_Array[i],
 545                                  Rtl8192UsbAGCTAB_Array[i+1]);
 546                 }
 547         }
 548 }
 549
 550 /******************************************************************************
 551  * function:  This function initializes Register definition offset for
 552  *            Radio Path A/B/C/D
 553  * input:     net_device        *dev
 554  * output:    none
 555  * return:    none
 556  * notice:    Initialization value here is constant and it should never
 557  *            be changed
 558  *****************************************************************************/
 559 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
 560 {
 561         struct r8192_priv *priv = ieee80211_priv(dev);
 562
 563         /* RF Interface Software Control */
 564         /* 16 LSBs if read 32-bit from 0x870 */
 565         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 566         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 567         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 568         /* 16 LSBs if read 32-bit from 0x874 */
 569         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 570         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 571         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 572
 573         /* RF Interface Readback Value */
 574         /* 16 LSBs if read 32-bit from 0x8E0 */
 575         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 576         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 577         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 578         /* 16 LSBs if read 32-bit from 0x8E4 */
 579         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 580         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 581         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 582
 583         /* RF Interface Output (and Enable) */
 584         /* 16 LSBs if read 32-bit from 0x860 */
 585         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 586         /* 16 LSBs if read 32-bit from 0x864 */
 587         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 588         /* 16 LSBs if read 32-bit from 0x868 */
 589         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 590         /* 16 LSBs if read 32-bit from 0x86C */
 591         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 592
 593         /* RF Interface (Output and) Enable */
 594         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 595         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 596         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 597         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 598         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 599         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 600         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 601         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 602
 603         /* Addr of LSSI. Write RF register by driver */
 604         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 605         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 606         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 607         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 608
 609         /* RF parameter */
 610         /* BB Band Select */
 611         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 612         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 613         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 614         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 615
 616         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 617         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 618         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 619         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 620         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 621
 622         /* Tranceiver A~D HSSI Parameter-1 */
 623         /* wire control parameter1 */
 624         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 625         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 626         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 627         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 628
 629         /* Tranceiver A~D HSSI Parameter-2 */
 630         /* wire control parameter2 */
 631         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 632         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 633         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 634         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 635
 636         /* RF Switch Control */
 637         /* TR/Ant switch control */
 638         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 639         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 640         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 641         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 642
 643         /* AGC control 1 */
 644         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 645         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 646         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 647         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 648
 649         /* AGC control 2 */
 650         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 651         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 652         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 653         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 654
 655         /* RX AFE control 1 */
 656         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 657         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 658         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 659         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 660
 661         /* RX AFE control 1 */
 662         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 663         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 664         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 665         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 666
 667         /* Tx AFE control 1 */
 668         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 669         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 670         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 671         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 672
 673         /* Tx AFE control 2 */
 674         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 675         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 676         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 677         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 678
 679         /* Tranceiver LSSI Readback */
 680         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 681         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 682         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 683         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 684 }
 685
 686 /******************************************************************************
 687  * function:  This function is to write register and then readback to make
 688  *            sure whether BB and RF is OK
 689  * input:     net_device        *dev
 690  *            hw90_block_e      CheckBlock
 691  *            rf90_radio_path_e e_rfpath  //only used when checkblock is
 692  *                                       //HW90_BLOCK_RF
 693  * output:    none
 694  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 695  * notice:    This function may be removed in the ASIC
 696  ******************************************************************************/
 697 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block_e CheckBlock,
 698                             enum rf90_radio_path_e e_rfpath)
 699 {
 700         u8 ret = 0;
 701         u32 i, CheckTimes = 4, reg = 0;
 702         u32 WriteAddr[4];
 703         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 704
 705         /* Initialize register address offset to be checked */
 706         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 707         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 708         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 709         WriteAddr[HW90_BLOCK_RF] = 0x3;
 710         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
 711         for (i = 0; i < CheckTimes; i++) {
 712
 713                 /* Write data to register and readback */
 714                 switch (CheckBlock) {
 715                 case HW90_BLOCK_MAC:
 716                         RT_TRACE(COMP_ERR,
 717                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
 718                         break;
 719
 720                 case HW90_BLOCK_PHY0:
 721                 case HW90_BLOCK_PHY1:
 722                         write_nic_dword(dev, WriteAddr[CheckBlock],
 723                                         WriteData[i]);
 724                         read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
 725                         break;
 726
 727                 case HW90_BLOCK_RF:
 728                         WriteData[i] &= 0xfff;
 729                         rtl8192_phy_SetRFReg(dev, e_rfpath,
 730                                              WriteAddr[HW90_BLOCK_RF],
 731                                              bMask12Bits, WriteData[i]);
 732                         /* TODO: we should not delay for such a long time.
 733                          * Ask SD3
 734                          */
 735                         usleep_range(1000, 1000);
 736                         reg = rtl8192_phy_QueryRFReg(dev, e_rfpath,
 737                                                      WriteAddr[HW90_BLOCK_RF],
 738                                                      bMask12Bits);
 739                         usleep_range(1000, 1000);
 740                         break;
 741
 742                 default:
 743                         ret = 1;
 744                         break;
 745                 }
 746
 747
 748                 /* Check whether readback data is correct */
 749                 if (reg != WriteData[i]) {
 750                         RT_TRACE((COMP_PHY|COMP_ERR),
 751                                  "error reg: %x, WriteData: %x\n",
 752                                  reg, WriteData[i]);
 753                         ret = 1;
 754                         break;
 755                 }
 756         }
 757
 758         return ret;
 759 }
 760
 761 /******************************************************************************
 762  * function:  This function initializes BB&RF
 763  * input:     net_device        *dev
 764  * output:    none
 765  * return:    none
 766  * notice:    Initialization value may change all the time, so please make
 767  *            sure it has been synced with the newest.
 768  ******************************************************************************/
 769 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 770 {
 771         struct r8192_priv *priv = ieee80211_priv(dev);
 772         u8 reg_u8 = 0, eCheckItem = 0, status = 0;
 773         u32 reg_u32 = 0;
 774
 775         /**************************************
 776          * <1> Initialize BaseBand
 777          *************************************/
 778
 779         /* --set BB Global Reset-- */
 780         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 781         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 782         mdelay(50);
 783         /* ---set BB reset Active--- */
 784         read_nic_dword(dev, CPU_GEN, &reg_u32);
 785         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 786
 787         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 788         /* TODO: this function should be removed on ASIC */
 789         for (eCheckItem = (enum hw90_block_e)HW90_BLOCK_PHY0;
 790              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 791                 /* don't care RF path */
 792                 status = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block_e)eCheckItem,
 793                                                   (enum rf90_radio_path_e)0);
 794                 if (status != 0) {
 795                         RT_TRACE((COMP_ERR | COMP_PHY),
 796                                  "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
 797                                  eCheckItem-1);
 798                         return;
 799                 }
 800         }
 801         /* ---- Set CCK and OFDM Block "OFF"---- */
 802         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 803         /* ----BB Register Initilazation---- */
 804         /* ==m==>Set PHY REG From Header<==m== */
 805         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 806
 807         /* ----Set BB reset de-Active---- */
 808         read_nic_dword(dev, CPU_GEN, &reg_u32);
 809         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 810
 811         /* ----BB AGC table Initialization---- */
 812         /* ==m==>Set PHY REG From Header<==m== */
 813         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 814
 815         /* ----Enable XSTAL ---- */
 816         write_nic_byte_E(dev, 0x5e, 0x00);
 817         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 818                 /* Antenna gain offset from B/C/D to A */
 819                 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
 820                            priv->AntennaTxPwDiff[0];
 821                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 822                                  reg_u32);
 823
 824                 /* XSTALLCap */
 825                 reg_u32 = priv->CrystalCap & 0xf;
 826                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 827                                  reg_u32);
 828         }
 829
 830         /* Check if the CCK HighPower is turned ON.
 831          * This is used to calculate PWDB.
 832          */
 833         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 834                                                      rFPGA0_XA_HSSIParameter2,
 835                                                      0x200);
 836 }
 837
 838 /******************************************************************************
 839  * function:  This function initializes BB&RF
 840  * input:     net_device        *dev
 841  * output:    none
 842  * return:    none
 843  * notice:    Initialization value may change all the time, so please make
 844  *            sure it has been synced with the newest.
 845  *****************************************************************************/
 846 void rtl8192_BBConfig(struct net_device *dev)
 847 {
 848         rtl8192_InitBBRFRegDef(dev);
 849         /* config BB&RF. As hardCode based initialization has not been well
 850          * implemented, so use file first.
 851          * FIXME: should implement it for hardcode?
 852          */
 853         rtl8192_BB_Config_ParaFile(dev);
 854 }
 855
 856
 857 /******************************************************************************
 858  * function:  This function obtains the initialization value of Tx power Level
 859  *            offset
 860  * input:     net_device        *dev
 861  * output:    none
 862  * return:    none
 863  *****************************************************************************/
 864 void rtl8192_phy_getTxPower(struct net_device *dev)
 865 {
 866         struct r8192_priv *priv = ieee80211_priv(dev);
 867         u8 tmp;
 868
 869         read_nic_dword(dev, rTxAGC_Rate18_06,
 870                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 871         read_nic_dword(dev, rTxAGC_Rate54_24,
 872                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 873         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 874                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 875         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 876                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 877         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 878                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 879         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 880                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 881
 882         /* Read rx initial gain */
 883         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 884         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 885         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 886         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 887         RT_TRACE(COMP_INIT,
 888                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 889                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 890                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 891
 892         /* Read framesync */
 893         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 894         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 895         priv->framesyncC34 = tmp;
 896         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
 897                 rOFDM0_RxDetector3, priv->framesync);
 898
 899         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 900         read_nic_word(dev, SIFS, &priv->SifsTime);
 901 }
 902
 903 /******************************************************************************
 904  * function:  This function sets the initialization value of Tx power Level
 905  *            offset
 906  * input:     net_device        *dev
 907  *            u8                channel
 908  * output:    none
 909  * return:    none
 910  ******************************************************************************/
 911 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 912 {
 913         struct r8192_priv *priv = ieee80211_priv(dev);
 914         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 915         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 916
 917         switch (priv->rf_chip) {
 918         case RF_8256:
 919                 /* need further implement */
 920                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 921                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 922                 break;
 923         default:
 924                 RT_TRACE((COMP_PHY|COMP_ERR),
 925                          "error RF chipID(8225 or 8258) in function %s()\n",
 926                          __func__);
 927                 break;
 928         }
 929 }
 930
 931 /******************************************************************************
 932  * function:  This function checks Rf chip to do RF config
 933  * input:     net_device        *dev
 934  * output:    none
 935  * return:    only 8256 is supported
 936  ******************************************************************************/
 937 void rtl8192_phy_RFConfig(struct net_device *dev)
 938 {
 939         struct r8192_priv *priv = ieee80211_priv(dev);
 940
 941         switch (priv->rf_chip) {
 942         case RF_8256:
 943                 PHY_RF8256_Config(dev);
 944                 break;
 945         default:
 946                 RT_TRACE(COMP_ERR, "error chip id\n");
 947                 break;
 948         }
 949 }
 950
 951 /******************************************************************************
 952  * function:  This function updates Initial gain
 953  * input:     net_device        *dev
 954  * output:    none
 955  * return:    As Windows has not implemented this, wait for complement
 956  ******************************************************************************/
 957 void rtl8192_phy_updateInitGain(struct net_device *dev)
 958 {
 959 }
 960
 961 /******************************************************************************
 962  * function:  This function read RF parameters from general head file,
 963  *            and do RF 3-wire
 964  * input:     net_device        *dev
 965  *            rf90_radio_path_e e_rfpath
 966  * output:    none
 967  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 968  * notice:    Delay may be required for RF configuration
 969  *****************************************************************************/
 970 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 971                                       enum rf90_radio_path_e    e_rfpath)
 972 {
 973
 974         int i;
 975
 976         switch (e_rfpath) {
 977         case RF90_PATH_A:
 978                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
 979
 980                         if (Rtl8192UsbRadioA_Array[i] == 0xfe) {
 981                                 mdelay(100);
 982                                 continue;
 983                         }
 984                         rtl8192_phy_SetRFReg(dev, e_rfpath,
 985                                              Rtl8192UsbRadioA_Array[i],
 986                                              bMask12Bits,
 987                                              Rtl8192UsbRadioA_Array[i+1]);
 988                         mdelay(1);
 989
 990                 }
 991                 break;
 992         case RF90_PATH_B:
 993                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
 994
 995                         if (Rtl8192UsbRadioB_Array[i] == 0xfe) {
 996                                 mdelay(100);
 997                                 continue;
 998                         }
 999                         rtl8192_phy_SetRFReg(dev, e_rfpath,
1000                                              Rtl8192UsbRadioB_Array[i],
1001                                              bMask12Bits,
1002                                              Rtl8192UsbRadioB_Array[i+1]);
1003                         mdelay(1);
1004
1005                 }
1006                 break;
1007         case RF90_PATH_C:
1008                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1009
1010                         if (Rtl8192UsbRadioC_Array[i] == 0xfe) {
1011                                 mdelay(100);
1012                                 continue;
1013                         }
1014                         rtl8192_phy_SetRFReg(dev, e_rfpath,
1015                                              Rtl8192UsbRadioC_Array[i],
1016                                              bMask12Bits,
1017                                              Rtl8192UsbRadioC_Array[i+1]);
1018                         mdelay(1);
1019
1020                 }
1021                 break;
1022         case RF90_PATH_D:
1023                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1024
1025                         if (Rtl8192UsbRadioD_Array[i] == 0xfe) {
1026                                 mdelay(100);
1027                                 continue;
1028                         }
1029                         rtl8192_phy_SetRFReg(dev, e_rfpath,
1030                                              Rtl8192UsbRadioD_Array[i],
1031                                              bMask12Bits,
1032                                              Rtl8192UsbRadioD_Array[i+1]);
1033                         mdelay(1);
1034
1035                 }
1036                 break;
1037         default:
1038                 break;
1039         }
1040
1041         return 0;
1042
1043 }
1044
1045 /******************************************************************************
1046  * function:  This function sets Tx Power of the channel
1047  * input:     net_device        *dev
1048  *            u8                channel
1049  * output:    none
1050  * return:    none
1051  * notice:
1052  ******************************************************************************/
1053 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1054 {
1055         struct r8192_priv *priv = ieee80211_priv(dev);
1056         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1057         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1058
1059         switch (priv->rf_chip) {
1060         case RF_8225:
1061 #ifdef TO_DO_LIST
1062                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1063                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1064 #endif
1065                 break;
1066
1067         case RF_8256:
1068                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1069                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1070                 break;
1071
1072         case RF_8258:
1073                 break;
1074         default:
1075                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1076                 break;
1077         }
1078 }
1079
1080 /******************************************************************************
1081  * function:  This function sets RF state on or off
1082  * input:     net_device         *dev
1083  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1084  * output:    none
1085  * return:    none
1086  * notice:
1087  *****************************************************************************/
1088 bool rtl8192_SetRFPowerState(struct net_device *dev,
1089                              RT_RF_POWER_STATE eRFPowerState)
1090 {
1091         bool                            bResult = true;
1092         struct r8192_priv *priv = ieee80211_priv(dev);
1093
1094         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1095                 return false;
1096
1097         if (priv->SetRFPowerStateInProgress)
1098                 return false;
1099
1100         priv->SetRFPowerStateInProgress = true;
1101
1102         switch (priv->rf_chip) {
1103         case RF_8256:
1104                 switch (eRFPowerState) {
1105                 case eRfOn:
1106                         /* RF-A, RF-B */
1107                         /* enable RF-Chip A/B - 0x860[4] */
1108                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1109                                          0x1);
1110                         /* analog to digital on - 0x88c[9:8] */
1111                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1112                                          0x3);
1113                         /* digital to analog on - 0x880[4:3] */
1114                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1115                                          0x3);
1116                         /* rx antenna on - 0xc04[1:0] */
1117                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1118                         /* rx antenna on - 0xd04[1:0] */
1119                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1120                         /* analog to digital part2 on - 0x880[6:5] */
1121                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1122                                          0x3);
1123
1124                         break;
1125
1126                 case eRfSleep:
1127
1128                         break;
1129
1130                 case eRfOff:
1131                         /* RF-A, RF-B */
1132                         /* disable RF-Chip A/B - 0x860[4] */
1133                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1134                                          0x0);
1135                         /* analog to digital off, for power save */
1136                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1137                                          0x0); /* 0x88c[11:8] */
1138                         /* digital to analog off, for power save - 0x880[4:3] */
1139                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1140                                          0x0);
1141                         /* rx antenna off - 0xc04[3:0] */
1142                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1143                         /* rx antenna off - 0xd04[3:0] */
1144                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1145                         /* analog to digital part2 off, for power save */
1146                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1147                                          0x0); /* 0x880[6:5] */
1148
1149                         break;
1150
1151                 default:
1152                         bResult = false;
1153                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1154                                  __func__, eRFPowerState);
1155                         break;
1156                 }
1157                 break;
1158         default:
1159                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1160                 break;
1161         }
1162 #ifdef TO_DO_LIST
1163         if (bResult) {
1164                 /* Update current RF state variable. */
1165                 pHalData->eRFPowerState = eRFPowerState;
1166                 switch (pHalData->RFChipID) {
1167                 case RF_8256:
1168                         switch (pHalData->eRFPowerState) {
1169                         case eRfOff:
1170                                 /* If Rf off reason is from IPS,
1171                                  * LED should blink with no link
1172                                  */
1173                                 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1174                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1175                                 else
1176                                         /* Turn off LED if RF is not ON. */
1177                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1178                                 break;
1179
1180                         case eRfOn:
1181                                 /* Turn on RF we are still linked, which might
1182                                  * happen when we quickly turn off and on HW RF.
1183                                  */
1184                                 if (pMgntInfo->bMediaConnect)
1185                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1186                                 else
1187                                         /* Turn off LED if RF is not ON. */
1188                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1189                                 break;
1190
1191                         default:
1192                                 break;
1193                         }
1194                         break;
1195
1196                 default:
1197                         RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1198                                  __func__);
1199                         break;
1200                 }
1201
1202         }
1203 #endif
1204         priv->SetRFPowerStateInProgress = false;
1205
1206         return bResult;
1207 }
1208
1209 /******************************************************************************
1210  * function:  This function sets command table variable (struct sw_chnl_cmd).
1211  * input:     sw_chnl_cmd      *CmdTable    //table to be set
1212  *            u32            CmdTableIdx  //variable index in table to be set
1213  *            u32            CmdTableSz   //table size
1214  *            switch_chan_cmd_id    CmdID        //command ID to set
1215  *            u32            Para1
1216  *            u32            Para2
1217  *            u32            msDelay
1218  * output:
1219  * return:    true if finished, false otherwise
1220  * notice:
1221  ******************************************************************************/
1222 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx,
1223                                         u32 CmdTableSz, enum switch_chan_cmd_id CmdID,
1224                                         u32 Para1, u32 Para2, u32 msDelay)
1225 {
1226         struct sw_chnl_cmd *pCmd;
1227
1228         if (CmdTable == NULL) {
1229                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1230                 return false;
1231         }
1232         if (CmdTableIdx >= CmdTableSz) {
1233                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1234                          __func__, CmdTableIdx, CmdTableSz);
1235                 return false;
1236         }
1237
1238         pCmd = CmdTable + CmdTableIdx;
1239         pCmd->cmd_id = CmdID;
1240         pCmd->para_1 = Para1;
1241         pCmd->para_2 = Para2;
1242         pCmd->ms_delay = msDelay;
1243
1244         return true;
1245 }
1246
1247 /******************************************************************************
1248  * function:  This function sets channel step by step
1249  * input:     net_device        *dev
1250  *            u8                channel
1251  *            u8                *stage   //3 stages
1252  *            u8                *step
1253  *            u32               *delay   //whether need to delay
1254  * output:    store new stage, step and delay for next step
1255  *            (combine with function above)
1256  * return:    true if finished, false otherwise
1257  * notice:    Wait for simpler function to replace it
1258  *****************************************************************************/
1259 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1260                                        u8 *stage, u8 *step, u32 *delay)
1261 {
1262         struct r8192_priv *priv = ieee80211_priv(dev);
1263         struct sw_chnl_cmd   PreCommonCmd[MAX_PRECMD_CNT];
1264         u32                PreCommonCmdCnt;
1265         struct sw_chnl_cmd   PostCommonCmd[MAX_POSTCMD_CNT];
1266         u32                PostCommonCmdCnt;
1267         struct sw_chnl_cmd   RfDependCmd[MAX_RFDEPENDCMD_CNT];
1268         u32                RfDependCmdCnt;
1269         struct sw_chnl_cmd  *CurrentCmd = NULL;
1270         u8                 e_rfpath;
1271
1272         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1273                  __func__, *stage, *step, channel);
1274         if (!IsLegalChannel(priv->ieee80211, channel)) {
1275                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1276                 /* return true to tell upper caller function this channel
1277                  * setting is finished! Or it will in while loop.
1278                  */
1279                 return true;
1280         }
1281         /* FIXME: need to check whether channel is legal or not here */
1282
1283
1284         /* <1> Fill up pre common command. */
1285         PreCommonCmdCnt = 0;
1286         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1287                                       MAX_PRECMD_CNT, CMD_ID_SET_TX_PWR_LEVEL,
1288                                       0, 0, 0);
1289         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1290                                       MAX_PRECMD_CNT, CMD_ID_END, 0, 0, 0);
1291
1292         /* <2> Fill up post common command. */
1293         PostCommonCmdCnt = 0;
1294
1295         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1296                                       MAX_POSTCMD_CNT, CMD_ID_END, 0, 0, 0);
1297
1298         /* <3> Fill up RF dependent command. */
1299         RfDependCmdCnt = 0;
1300         switch (priv->rf_chip) {
1301         case RF_8225:
1302                 if (!(channel >= 1 && channel <= 14)) {
1303                         RT_TRACE(COMP_ERR,
1304                                  "illegal channel for Zebra 8225: %d\n",
1305                                  channel);
1306                         return true;
1307                 }
1308                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1309                                               MAX_RFDEPENDCMD_CNT,
1310                                               CMD_ID_RF_WRITE_REG,
1311                                               rZebra1_Channel,
1312                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1313                                               10);
1314                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1315                                               MAX_RFDEPENDCMD_CNT,
1316                                               CMD_ID_END, 0, 0, 0);
1317                 break;
1318
1319         case RF_8256:
1320                 /* TEST!! This is not the table for 8256!! */
1321                 if (!(channel >= 1 && channel <= 14)) {
1322                         RT_TRACE(COMP_ERR,
1323                                  "illegal channel for Zebra 8256: %d\n",
1324                                  channel);
1325                         return true;
1326                 }
1327                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1328                                               MAX_RFDEPENDCMD_CNT,
1329                                               CMD_ID_RF_WRITE_REG,
1330                                               rZebra1_Channel, channel, 10);
1331                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1332                                               MAX_RFDEPENDCMD_CNT,
1333                                               CMD_ID_END, 0, 0, 0);
1334                 break;
1335
1336         case RF_8258:
1337                 break;
1338
1339         default:
1340                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1341                 return true;
1342         }
1343
1344
1345         do {
1346                 switch (*stage) {
1347                 case 0:
1348                         CurrentCmd = &PreCommonCmd[*step];
1349                         break;
1350                 case 1:
1351                         CurrentCmd = &RfDependCmd[*step];
1352                         break;
1353                 case 2:
1354                         CurrentCmd = &PostCommonCmd[*step];
1355                         break;
1356                 }
1357
1358                 if (CurrentCmd->cmd_id == CMD_ID_END) {
1359                         if ((*stage) == 2) {
1360                                 (*delay) = CurrentCmd->ms_delay;
1361                                 return true;
1362                         }
1363                         (*stage)++;
1364                         (*step) = 0;
1365                         continue;
1366                 }
1367
1368                 switch (CurrentCmd->cmd_id) {
1369                 case CMD_ID_SET_TX_PWR_LEVEL:
1370                         if (priv->card_8192_version == (u8)VERSION_819xU_A)
1371                                 /* consider it later! */
1372                                 rtl8192_SetTxPowerLevel(dev, channel);
1373                         break;
1374                 case CMD_ID_WRITE_PORT_ULONG:
1375                         write_nic_dword(dev, CurrentCmd->para_1,
1376                                         CurrentCmd->para_2);
1377                         break;
1378                 case CMD_ID_WRITE_PORT_USHORT:
1379                         write_nic_word(dev, CurrentCmd->para_1,
1380                                        (u16)CurrentCmd->para_2);
1381                         break;
1382                 case CMD_ID_WRITE_PORT_UCHAR:
1383                         write_nic_byte(dev, CurrentCmd->para_1,
1384                                        (u8)CurrentCmd->para_2);
1385                         break;
1386                 case CMD_ID_RF_WRITE_REG:
1387                         for (e_rfpath = 0; e_rfpath < RF90_PATH_MAX; e_rfpath++) {
1388                                 rtl8192_phy_SetRFReg(dev,
1389                                                      (enum rf90_radio_path_e)e_rfpath,
1390                                                      CurrentCmd->para_1,
1391                                                      bZebra1_ChannelNum,
1392                                                      CurrentCmd->para_2);
1393                         }
1394                         break;
1395                 default:
1396                         break;
1397                 }
1398
1399                 break;
1400         } while (true);
1401
1402         (*delay) = CurrentCmd->ms_delay;
1403         (*step)++;
1404         return false;
1405 }
1406
1407 /******************************************************************************
1408  * function:  This function does actually set channel work
1409  * input:     net_device        *dev
1410  *            u8                channel
1411  * output:    none
1412  * return:    none
1413  * notice:    We should not call this function directly
1414  *****************************************************************************/
1415 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1416 {
1417         struct r8192_priv *priv = ieee80211_priv(dev);
1418         u32     delay = 0;
1419
1420         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1421                                              &priv->SwChnlStep, &delay)) {
1422                 if (!priv->up)
1423                         break;
1424         }
1425 }
1426
1427 /******************************************************************************
1428  * function:  Callback routine of the work item for switch channel.
1429  * input:     net_device        *dev
1430  *
1431  * output:    none
1432  * return:    none
1433  *****************************************************************************/
1434 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1435 {
1436
1437         struct r8192_priv *priv = ieee80211_priv(dev);
1438
1439         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1440                  priv->chan);
1441
1442
1443         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1444
1445         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1446 }
1447
1448 /******************************************************************************
1449  * function:  This function scheduled actual work item to set channel
1450  * input:     net_device        *dev
1451  *            u8                channel   //channel to set
1452  * output:    none
1453  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1454  * notice:    Delay may be required for RF configuration
1455  ******************************************************************************/
1456 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1457 {
1458         struct r8192_priv *priv = ieee80211_priv(dev);
1459
1460         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1461                  priv->SwChnlInProgress);
1462         if (!priv->up)
1463                 return false;
1464         if (priv->SwChnlInProgress)
1465                 return false;
1466
1467         /* -------------------------------------------- */
1468         switch (priv->ieee80211->mode) {
1469         case WIRELESS_MODE_A:
1470         case WIRELESS_MODE_N_5G:
1471                 if (channel <= 14) {
1472                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1473                         return false;
1474                 }
1475                 break;
1476         case WIRELESS_MODE_B:
1477                 if (channel > 14) {
1478                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1479                         return false;
1480                 }
1481                 break;
1482         case WIRELESS_MODE_G:
1483         case WIRELESS_MODE_N_24G:
1484                 if (channel > 14) {
1485                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1486                         return false;
1487                 }
1488                 break;
1489         }
1490         /* -------------------------------------------- */
1491
1492         priv->SwChnlInProgress = true;
1493         if (channel == 0)
1494                 channel = 1;
1495
1496         priv->chan = channel;
1497
1498         priv->SwChnlStage = 0;
1499         priv->SwChnlStep = 0;
1500         if (priv->up)
1501                 rtl8192_SwChnl_WorkItem(dev);
1502
1503         priv->SwChnlInProgress = false;
1504         return true;
1505 }
1506
1507 /******************************************************************************
1508  * function:  Callback routine of the work item for set bandwidth mode.
1509  * input:     net_device         *dev
1510  * output:    none
1511  * return:    none
1512  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1513  *            test whether current work in the queue or not.//do I?
1514  *****************************************************************************/
1515 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1516 {
1517
1518         struct r8192_priv *priv = ieee80211_priv(dev);
1519         u8 regBwOpMode;
1520
1521         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1522                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1523
1524
1525         if (priv->rf_chip == RF_PSEUDO_11N) {
1526                 priv->SetBWModeInProgress = false;
1527                 return;
1528         }
1529
1530         /* <1> Set MAC register */
1531         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1532
1533         switch (priv->CurrentChannelBW) {
1534         case HT_CHANNEL_WIDTH_20:
1535                 regBwOpMode |= BW_OPMODE_20MHZ;
1536                 /* We have not verify whether this register works */
1537                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1538                 break;
1539
1540         case HT_CHANNEL_WIDTH_20_40:
1541                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1542                 /* We have not verify whether this register works */
1543                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1544                 break;
1545
1546         default:
1547                 RT_TRACE(COMP_ERR,
1548                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1549                          priv->CurrentChannelBW);
1550                 break;
1551         }
1552
1553         /* <2> Set PHY related register */
1554         switch (priv->CurrentChannelBW) {
1555         case HT_CHANNEL_WIDTH_20:
1556                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1557                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1558                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1559                                  0x00100000, 1);
1560
1561                 /* Correct the tx power for CCK rate in 20M. */
1562                 priv->cck_present_attenuation =
1563                         priv->cck_present_attenuation_20Mdefault +
1564                         priv->cck_present_attenuation_difference;
1565
1566                 if (priv->cck_present_attenuation > 22)
1567                         priv->cck_present_attenuation = 22;
1568                 if (priv->cck_present_attenuation < 0)
1569                         priv->cck_present_attenuation = 0;
1570                 RT_TRACE(COMP_INIT,
1571                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1572                          priv->cck_present_attenuation);
1573
1574                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1575                         priv->bcck_in_ch14 = true;
1576                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1577                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1578                         priv->bcck_in_ch14 = false;
1579                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1580                 } else {
1581                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1582                 }
1583
1584                 break;
1585         case HT_CHANNEL_WIDTH_20_40:
1586                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1587                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1588                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1589                                  priv->nCur40MhzPrimeSC>>1);
1590                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1591                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1592                                  priv->nCur40MhzPrimeSC);
1593                 priv->cck_present_attenuation =
1594                         priv->cck_present_attenuation_40Mdefault +
1595                         priv->cck_present_attenuation_difference;
1596
1597                 if (priv->cck_present_attenuation > 22)
1598                         priv->cck_present_attenuation = 22;
1599                 if (priv->cck_present_attenuation < 0)
1600                         priv->cck_present_attenuation = 0;
1601
1602                 RT_TRACE(COMP_INIT,
1603                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1604                          priv->cck_present_attenuation);
1605                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1606                         priv->bcck_in_ch14 = true;
1607                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1608                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1609                         priv->bcck_in_ch14 = false;
1610                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1611                 } else {
1612                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1613                 }
1614
1615                 break;
1616         default:
1617                 RT_TRACE(COMP_ERR,
1618                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1619                          priv->CurrentChannelBW);
1620                 break;
1621
1622         }
1623         /* Skip over setting of J-mode in BB register here.
1624          * Default value is "None J mode".
1625          */
1626
1627         /* <3> Set RF related register */
1628         switch (priv->rf_chip) {
1629         case RF_8225:
1630 #ifdef TO_DO_LIST
1631                 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1632 #endif
1633                 break;
1634
1635         case RF_8256:
1636                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1637                 break;
1638
1639         case RF_8258:
1640                 break;
1641
1642         case RF_PSEUDO_11N:
1643                 break;
1644
1645         default:
1646                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1647                 break;
1648         }
1649         priv->SetBWModeInProgress = false;
1650
1651         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1652                  atomic_read(&priv->ieee80211->atm_swbw));
1653 }
1654
1655 /******************************************************************************
1656  * function:  This function schedules bandwidth switch work.
1657  * input:     struct net_deviceq   *dev
1658  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1659  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1660  * output:    none
1661  * return:    none
1662  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1663  *            test whether current work in the queue or not.//do I?
1664  *****************************************************************************/
1665 void rtl8192_SetBWMode(struct net_device *dev,
1666                        enum ht_channel_width bandwidth,
1667                        enum ht_extension_chan_offset offset)
1668 {
1669         struct r8192_priv *priv = ieee80211_priv(dev);
1670
1671         if (priv->SetBWModeInProgress)
1672                 return;
1673         priv->SetBWModeInProgress = true;
1674
1675         priv->CurrentChannelBW = bandwidth;
1676
1677         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1678                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1679         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1680                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1681         else
1682                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1683
1684         rtl8192_SetBWModeWorkItem(dev);
1685
1686 }
1687
1688 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1689 {
1690         struct r8192_priv *priv = ieee80211_priv(dev);
1691
1692         priv->InitialGainOperateType = Operation;
1693
1694         if (priv->up)
1695                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1696 }
1697
1698 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1699 {
1700         struct delayed_work *dwork = to_delayed_work(work);
1701         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1702                                                initialgain_operate_wq);
1703         struct net_device *dev = priv->ieee80211->dev;
1704 #define SCAN_RX_INITIAL_GAIN    0x17
1705 #define POWER_DETECTION_TH      0x08
1706         u32     bitmask;
1707         u8      initial_gain;
1708         u8      Operation;
1709
1710         Operation = priv->InitialGainOperateType;
1711
1712         switch (Operation) {
1713         case IG_Backup:
1714                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1715                 initial_gain = SCAN_RX_INITIAL_GAIN;
1716                 bitmask = bMaskByte0;
1717                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1718                         /* FW DIG OFF */
1719                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1720                 priv->initgain_backup.xaagccore1 =
1721                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1722                 priv->initgain_backup.xbagccore1 =
1723                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1724                 priv->initgain_backup.xcagccore1 =
1725                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1726                 priv->initgain_backup.xdagccore1 =
1727                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1728                 bitmask = bMaskByte2;
1729                 priv->initgain_backup.cca =
1730                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1731
1732                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1733                          priv->initgain_backup.xaagccore1);
1734                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1735                          priv->initgain_backup.xbagccore1);
1736                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1737                          priv->initgain_backup.xcagccore1);
1738                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1739                          priv->initgain_backup.xdagccore1);
1740                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1741                          priv->initgain_backup.cca);
1742
1743                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1744                          initial_gain);
1745                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1746                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1747                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1748                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1749                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1750                          POWER_DETECTION_TH);
1751                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1752                 break;
1753         case IG_Restore:
1754                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1755                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1756                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1757                         /* FW DIG OFF */
1758                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1759
1760                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1761                                  (u32)priv->initgain_backup.xaagccore1);
1762                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1763                                  (u32)priv->initgain_backup.xbagccore1);
1764                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1765                                  (u32)priv->initgain_backup.xcagccore1);
1766                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1767                                  (u32)priv->initgain_backup.xdagccore1);
1768                 bitmask  = bMaskByte2;
1769                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1770                                  (u32)priv->initgain_backup.cca);
1771
1772                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1773                          priv->initgain_backup.xaagccore1);
1774                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1775                          priv->initgain_backup.xbagccore1);
1776                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1777                          priv->initgain_backup.xcagccore1);
1778                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1779                          priv->initgain_backup.xdagccore1);
1780                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1781                          priv->initgain_backup.cca);
1782
1783                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1784
1785                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1786                         /* FW DIG ON */
1787                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1788                 break;
1789         default:
1790                 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1791                 break;
1792         }
1793 }