drivers/staging/rtl8192e/rtl8192e/rtl_dm.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * The full GNU General Public License is included in this distribution in the
  10  * file called LICENSE.
  11  *
  12  * Contact Information:
  13  * wlanfae <wlanfae@realtek.com>
  14  *****************************************************************************/
  15 #include "rtl_core.h"
  16 #include "rtl_dm.h"
  17 #include "r8192E_hw.h"
  18 #include "r8192E_phy.h"
  19 #include "r8192E_phyreg.h"
  20 #include "r8190P_rtl8256.h"
  21 #include "r8192E_cmdpkt.h"
  22
  23 /*---------------------------Define Local Constant---------------------------*/
  24 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
  25         0x5e4322,
  26         0x5e4322,
  27         0x5ea44f,
  28         0x5e4322,
  29         0x604322,
  30         0xa44f,
  31         0x5e4322,
  32         0x5e4332
  33 };
  34
  35 static u32 edca_setting_DL_GMode[HT_IOT_PEER_MAX] = {
  36         0x5e4322,
  37         0x5e4322,
  38         0x5e4322,
  39         0x5e4322,
  40         0x604322,
  41         0xa44f,
  42         0x5e4322,
  43         0x5e4322
  44 };
  45
  46 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
  47         0x5e4322,
  48         0xa44f,
  49         0x5ea44f,
  50         0x5e4322,
  51         0x604322,
  52         0x5e4322,
  53         0x5e4322,
  54         0x5e4332
  55 };
  56
  57 const u32 dm_tx_bb_gain[TxBBGainTableLength] = {
  58         0x7f8001fe, /* 12 dB */
  59         0x788001e2, /* 11 dB */
  60         0x71c001c7,
  61         0x6b8001ae,
  62         0x65400195,
  63         0x5fc0017f,
  64         0x5a400169,
  65         0x55400155,
  66         0x50800142,
  67         0x4c000130,
  68         0x47c0011f,
  69         0x43c0010f,
  70         0x40000100,
  71         0x3c8000f2,
  72         0x390000e4,
  73         0x35c000d7,
  74         0x32c000cb,
  75         0x300000c0,
  76         0x2d4000b5,
  77         0x2ac000ab,
  78         0x288000a2,
  79         0x26000098,
  80         0x24000090,
  81         0x22000088,
  82         0x20000080,
  83         0x1a00006c,
  84         0x1c800072,
  85         0x18000060,
  86         0x19800066,
  87         0x15800056,
  88         0x26c0005b,
  89         0x14400051,
  90         0x24400051,
  91         0x1300004c,
  92         0x12000048,
  93         0x11000044,
  94         0x10000040, /* -24 dB */
  95 };
  96
  97 const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8] = {
  98         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  99         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
 100         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
 101         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
 102         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
 103         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
 104         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
 105         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
 106         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
 107         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
 108         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
 109         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
 110         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
 111         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
 112         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
 113         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
 114         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
 115         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
 116         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
 117         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 118         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 119         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
 120         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}
 121 };
 122
 123 const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8] = {
 124         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
 125         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
 126         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
 127         {0x2d, 0x2d, 0x27, 0x17, 0x00, 0x00, 0x00, 0x00},
 128         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
 129         {0x28, 0x28, 0x22, 0x14, 0x00, 0x00, 0x00, 0x00},
 130         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
 131         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
 132         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
 133         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
 134         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
 135         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
 136         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
 137         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
 138         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
 139         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
 140         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
 141         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
 142         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
 143         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 144         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 145         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
 146         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}
 147 };
 148
 149 /*---------------------------Define Local Constant---------------------------*/
 150
 151
 152 /*------------------------Define global variable-----------------------------*/
 153 struct dig_t dm_digtable;
 154
 155 struct drx_path_sel DM_RxPathSelTable;
 156 /*------------------------Define global variable-----------------------------*/
 157
 158
 159 /*------------------------Define local variable------------------------------*/
 160 /*------------------------Define local variable------------------------------*/
 161
 162
 163
 164 /*---------------------Define local function prototype-----------------------*/
 165 static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev);
 166
 167 static void _rtl92e_dm_init_bandwidth_autoswitch(struct net_device *dev);
 168 static  void    _rtl92e_dm_bandwidth_autoswitch(struct net_device *dev);
 169
 170
 171 static  void    _rtl92e_dm_check_tx_power_tracking(struct net_device *dev);
 172
 173 static void _rtl92e_dm_bb_initialgain_restore(struct net_device *dev);
 174 static void _rtl92e_dm_dig_init(struct net_device *dev);
 175 static void _rtl92e_dm_ctrl_initgain_byrssi(struct net_device *dev);
 176 static void _rtl92e_dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
 177 static void _rtl92e_dm_ctrl_initgain_byrssi_driver(struct net_device *dev);
 178 static void _rtl92e_dm_ctrl_initgain_byrssi_false_alarm(struct net_device *dev);
 179 static void _rtl92e_dm_initial_gain(struct net_device *dev);
 180 static void _rtl92e_dm_pd_th(struct net_device *dev);
 181 static void _rtl92e_dm_cs_ratio(struct net_device *dev);
 182
 183 static  void _rtl92e_dm_init_cts_to_self(struct net_device *dev);
 184 static void _rtl92e_dm_init_wa_broadcom_iot(struct net_device *dev);
 185
 186 static void _rtl92e_dm_check_edca_turbo(struct net_device *dev);
 187 static void _rtl92e_dm_check_rx_path_selection(struct net_device *dev);
 188 static void _rtl92e_dm_init_rx_path_selection(struct net_device *dev);
 189 static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev);
 190
 191
 192 static void _rtl92e_dm_init_fsync(struct net_device *dev);
 193 static void _rtl92e_dm_deinit_fsync(struct net_device *dev);
 194
 195 static  void _rtl92e_dm_check_txrateandretrycount(struct net_device *dev);
 196 static void _rtl92e_dm_check_fsync(struct net_device *dev);
 197 static void _rtl92e_dm_check_rf_ctrl_gpio(void *data);
 198 static void _rtl92e_dm_fsync_timer_callback(unsigned long data);
 199
 200 /*---------------------Define local function prototype-----------------------*/
 201
 202 static  void    _rtl92e_dm_init_dynamic_tx_power(struct net_device *dev);
 203 static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev);
 204
 205 static void _rtl92e_dm_send_rssi_to_fw(struct net_device *dev);
 206 static void _rtl92e_dm_cts_to_self(struct net_device *dev);
 207 /*---------------------------Define function prototype------------------------*/
 208
 209 void rtl92e_dm_init(struct net_device *dev)
 210 {
 211         struct r8192_priv *priv = rtllib_priv(dev);
 212
 213         priv->DM_Type = DM_Type_ByDriver;
 214
 215         priv->undecorated_smoothed_pwdb = -1;
 216
 217         _rtl92e_dm_init_dynamic_tx_power(dev);
 218
 219         rtl92e_init_adaptive_rate(dev);
 220
 221         _rtl92e_dm_dig_init(dev);
 222         rtl92e_dm_init_edca_turbo(dev);
 223         _rtl92e_dm_init_bandwidth_autoswitch(dev);
 224         _rtl92e_dm_init_fsync(dev);
 225         _rtl92e_dm_init_rx_path_selection(dev);
 226         _rtl92e_dm_init_cts_to_self(dev);
 227         if (IS_HARDWARE_TYPE_8192SE(dev))
 228                 _rtl92e_dm_init_wa_broadcom_iot(dev);
 229
 230         INIT_DELAYED_WORK_RSL(&priv->gpio_change_rf_wq,
 231                               (void *)_rtl92e_dm_check_rf_ctrl_gpio, dev);
 232 }
 233
 234 void rtl92e_dm_deinit(struct net_device *dev)
 235 {
 236
 237         _rtl92e_dm_deinit_fsync(dev);
 238
 239 }
 240
 241 void rtl92e_dm_watchdog(struct net_device *dev)
 242 {
 243         struct r8192_priv *priv = rtllib_priv(dev);
 244
 245         if (priv->being_init_adapter)
 246                 return;
 247
 248         _rtl92e_dm_check_txrateandretrycount(dev);
 249         _rtl92e_dm_check_edca_turbo(dev);
 250
 251         _rtl92e_dm_check_rate_adaptive(dev);
 252         _rtl92e_dm_dynamic_tx_power(dev);
 253         _rtl92e_dm_check_tx_power_tracking(dev);
 254
 255         _rtl92e_dm_ctrl_initgain_byrssi(dev);
 256         _rtl92e_dm_bandwidth_autoswitch(dev);
 257
 258         _rtl92e_dm_check_rx_path_selection(dev);
 259         _rtl92e_dm_check_fsync(dev);
 260
 261         _rtl92e_dm_send_rssi_to_fw(dev);
 262         _rtl92e_dm_cts_to_self(dev);
 263 }
 264
 265 void rtl92e_init_adaptive_rate(struct net_device *dev)
 266 {
 267
 268         struct r8192_priv *priv = rtllib_priv(dev);
 269         struct rate_adaptive *pra = &priv->rate_adaptive;
 270
 271         pra->ratr_state = DM_RATR_STA_MAX;
 272         pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
 273         pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
 274         pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
 275
 276         pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
 277         pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
 278         pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
 279
 280         if (priv->CustomerID == RT_CID_819x_Netcore)
 281                 pra->ping_rssi_enable = 1;
 282         else
 283                 pra->ping_rssi_enable = 0;
 284         pra->ping_rssi_thresh_for_ra = 15;
 285
 286
 287         if (priv->rf_type == RF_2T4R) {
 288                 pra->upper_rssi_threshold_ratr          =       0x8f0f0000;
 289                 pra->middle_rssi_threshold_ratr         =       0x8f0ff000;
 290                 pra->low_rssi_threshold_ratr            =       0x8f0ff001;
 291                 pra->low_rssi_threshold_ratr_40M        =       0x8f0ff005;
 292                 pra->low_rssi_threshold_ratr_20M        =       0x8f0ff001;
 293                 pra->ping_rssi_ratr     =       0x0000000d;
 294         } else if (priv->rf_type == RF_1T2R) {
 295                 pra->upper_rssi_threshold_ratr          =       0x000fc000;
 296                 pra->middle_rssi_threshold_ratr         =       0x000ff000;
 297                 pra->low_rssi_threshold_ratr            =       0x000ff001;
 298                 pra->low_rssi_threshold_ratr_40M        =       0x000ff005;
 299                 pra->low_rssi_threshold_ratr_20M        =       0x000ff001;
 300                 pra->ping_rssi_ratr     =       0x0000000d;
 301         }
 302
 303 }
 304
 305
 306 static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev)
 307 {
 308         struct r8192_priv *priv = rtllib_priv(dev);
 309         struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo;
 310         struct rate_adaptive *pra = &priv->rate_adaptive;
 311         u32 currentRATR, targetRATR = 0;
 312         u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
 313         bool bshort_gi_enabled = false;
 314         static u8 ping_rssi_state;
 315
 316         if (!priv->up) {
 317                 RT_TRACE(COMP_RATE,
 318                          "<---- _rtl92e_dm_check_rate_adaptive(): driver is going to unload\n");
 319                 return;
 320         }
 321
 322         if (pra->rate_adaptive_disabled)
 323                 return;
 324
 325         if (!(priv->rtllib->mode == WIRELESS_MODE_N_24G ||
 326             priv->rtllib->mode == WIRELESS_MODE_N_5G))
 327                 return;
 328
 329         if (priv->rtllib->state == RTLLIB_LINKED) {
 330
 331                 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz &&
 332                                      pHTInfo->bCurShortGI40MHz) ||
 333                                     (!pHTInfo->bCurTxBW40MHz &&
 334                                      pHTInfo->bCurShortGI20MHz);
 335
 336                 pra->upper_rssi_threshold_ratr =
 337                                 (pra->upper_rssi_threshold_ratr & (~BIT31)) |
 338                                 ((bshort_gi_enabled) ? BIT31 : 0);
 339
 340                 pra->middle_rssi_threshold_ratr =
 341                                 (pra->middle_rssi_threshold_ratr & (~BIT31)) |
 342                                 ((bshort_gi_enabled) ? BIT31 : 0);
 343
 344                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
 345                         pra->low_rssi_threshold_ratr =
 346                                 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) |
 347                                 ((bshort_gi_enabled) ? BIT31 : 0);
 348                 } else {
 349                         pra->low_rssi_threshold_ratr =
 350                                 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) |
 351                                 ((bshort_gi_enabled) ? BIT31 : 0);
 352                 }
 353                 pra->ping_rssi_ratr =
 354                                 (pra->ping_rssi_ratr & (~BIT31)) |
 355                                 ((bshort_gi_enabled) ? BIT31 : 0);
 356
 357                 if (pra->ratr_state == DM_RATR_STA_HIGH) {
 358                         HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
 359                         LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 360                                         (pra->low_rssi_thresh_for_ra40M) : (pra->low_rssi_thresh_for_ra20M);
 361                 } else if (pra->ratr_state == DM_RATR_STA_LOW) {
 362                         HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
 363                         LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 364                                         (pra->low2high_rssi_thresh_for_ra40M) : (pra->low2high_rssi_thresh_for_ra20M);
 365                 } else {
 366                         HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
 367                         LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 368                                         (pra->low_rssi_thresh_for_ra40M) : (pra->low_rssi_thresh_for_ra20M);
 369                 }
 370
 371                 if (priv->undecorated_smoothed_pwdb >=
 372                     (long)HighRSSIThreshForRA) {
 373                         pra->ratr_state = DM_RATR_STA_HIGH;
 374                         targetRATR = pra->upper_rssi_threshold_ratr;
 375                 } else if (priv->undecorated_smoothed_pwdb >=
 376                            (long)LowRSSIThreshForRA) {
 377                         pra->ratr_state = DM_RATR_STA_MIDDLE;
 378                         targetRATR = pra->middle_rssi_threshold_ratr;
 379                 } else {
 380                         pra->ratr_state = DM_RATR_STA_LOW;
 381                         targetRATR = pra->low_rssi_threshold_ratr;
 382                 }
 383
 384                 if (pra->ping_rssi_enable) {
 385                         if (priv->undecorated_smoothed_pwdb <
 386                             (long)(pra->ping_rssi_thresh_for_ra+5)) {
 387                                 if ((priv->undecorated_smoothed_pwdb <
 388                                      (long)pra->ping_rssi_thresh_for_ra) ||
 389                                     ping_rssi_state) {
 390                                         pra->ratr_state = DM_RATR_STA_LOW;
 391                                         targetRATR = pra->ping_rssi_ratr;
 392                                         ping_rssi_state = 1;
 393                                 }
 394                         } else {
 395                                 ping_rssi_state = 0;
 396                         }
 397                 }
 398
 399                 if (priv->rtllib->GetHalfNmodeSupportByAPsHandler(dev))
 400                         targetRATR &=  0xf00fffff;
 401
 402                 currentRATR = rtl92e_readl(dev, RATR0);
 403                 if (targetRATR !=  currentRATR) {
 404                         u32 ratr_value;
 405
 406                         ratr_value = targetRATR;
 407                         RT_TRACE(COMP_RATE,
 408                                  "currentRATR = %x, targetRATR = %x\n",
 409                                  currentRATR, targetRATR);
 410                         if (priv->rf_type == RF_1T2R)
 411                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
 412                         rtl92e_writel(dev, RATR0, ratr_value);
 413                         rtl92e_writeb(dev, UFWP, 1);
 414
 415                         pra->last_ratr = targetRATR;
 416                 }
 417
 418         } else {
 419                 pra->ratr_state = DM_RATR_STA_MAX;
 420         }
 421 }
 422
 423 static void _rtl92e_dm_init_bandwidth_autoswitch(struct net_device *dev)
 424 {
 425         struct r8192_priv *priv = rtllib_priv(dev);
 426
 427         priv->rtllib->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
 428         priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
 429         priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = false;
 430         priv->rtllib->bandwidth_auto_switch.bautoswitch_enable = false;
 431 }
 432
 433 static void _rtl92e_dm_bandwidth_autoswitch(struct net_device *dev)
 434 {
 435         struct r8192_priv *priv = rtllib_priv(dev);
 436
 437         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||
 438            !priv->rtllib->bandwidth_auto_switch.bautoswitch_enable)
 439                 return;
 440         if (priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz == false) {
 441                 if (priv->undecorated_smoothed_pwdb <=
 442                     priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
 443                         priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = true;
 444         } else {
 445                 if (priv->undecorated_smoothed_pwdb >=
 446                     priv->rtllib->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
 447                         priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = false;
 448         }
 449 }
 450
 451 static u32 OFDMSwingTable[OFDM_Table_Length] = {
 452         0x7f8001fe,
 453         0x71c001c7,
 454         0x65400195,
 455         0x5a400169,
 456         0x50800142,
 457         0x47c0011f,
 458         0x40000100,
 459         0x390000e4,
 460         0x32c000cb,
 461         0x2d4000b5,
 462         0x288000a2,
 463         0x24000090,
 464         0x20000080,
 465         0x1c800072,
 466         0x19800066,
 467         0x26c0005b,
 468         0x24400051,
 469         0x12000048,
 470         0x10000040
 471 };
 472
 473 static u8       CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
 474         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
 475         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
 476         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
 477         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
 478         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
 479         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
 480         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
 481         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
 482         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
 483         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
 484         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 485         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}
 486 };
 487
 488 static u8       CCKSwingTable_Ch14[CCK_Table_length][8] = {
 489         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
 490         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
 491         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
 492         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
 493         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
 494         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
 495         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
 496         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
 497         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
 498         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
 499         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 500         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}
 501 };
 502
 503 #define         Pw_Track_Flag                           0x11d
 504 #define         Tssi_Mea_Value                          0x13c
 505 #define         Tssi_Report_Value1                      0x134
 506 #define         Tssi_Report_Value2                      0x13e
 507 #define         FW_Busy_Flag                            0x13f
 508
 509 static void _rtl92e_dm_tx_update_tssi_weak_signal(struct net_device *dev,
 510                                                   u8 RF_Type)
 511 {
 512         struct r8192_priv *p = rtllib_priv(dev);
 513
 514         if (RF_Type == RF_2T4R) {
 515                 if ((p->rfa_txpowertrackingindex > 0) &&
 516                     (p->rfc_txpowertrackingindex > 0)) {
 517                         p->rfa_txpowertrackingindex--;
 518                         if (p->rfa_txpowertrackingindex_real > 4) {
 519                                 p->rfa_txpowertrackingindex_real--;
 520                                 rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 521                                                   bMaskDWord,
 522                                                   dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
 523                         }
 524
 525                         p->rfc_txpowertrackingindex--;
 526                         if (p->rfc_txpowertrackingindex_real > 4) {
 527                                 p->rfc_txpowertrackingindex_real--;
 528                                 rtl92e_set_bb_reg(dev,
 529                                                   rOFDM0_XCTxIQImbalance,
 530                                                   bMaskDWord,
 531                                                   dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
 532                         }
 533                 } else {
 534                         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 535                                           bMaskDWord,
 536                                           dm_tx_bb_gain[4]);
 537                         rtl92e_set_bb_reg(dev,
 538                                           rOFDM0_XCTxIQImbalance,
 539                                           bMaskDWord, dm_tx_bb_gain[4]);
 540                 }
 541         } else {
 542                 if (p->rfa_txpowertrackingindex > 0) {
 543                         p->rfa_txpowertrackingindex--;
 544                         if (p->rfa_txpowertrackingindex_real > 4) {
 545                                 p->rfa_txpowertrackingindex_real--;
 546                                 rtl92e_set_bb_reg(dev,
 547                                                   rOFDM0_XATxIQImbalance,
 548                                                   bMaskDWord,
 549                                                   dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
 550                         }
 551                 } else {
 552                         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 553                                           bMaskDWord, dm_tx_bb_gain[4]);
 554                 }
 555         }
 556 }
 557
 558 static void _rtl92e_dm_tx_update_tssi_strong_signal(struct net_device *dev,
 559                                                     u8 RF_Type)
 560 {
 561         struct r8192_priv *p = rtllib_priv(dev);
 562
 563         if (RF_Type == RF_2T4R) {
 564                 if ((p->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&
 565                     (p->rfc_txpowertrackingindex < TxBBGainTableLength - 1)) {
 566                         p->rfa_txpowertrackingindex++;
 567                         p->rfa_txpowertrackingindex_real++;
 568                         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 569                                           bMaskDWord,
 570                                           dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
 571                         p->rfc_txpowertrackingindex++;
 572                         p->rfc_txpowertrackingindex_real++;
 573                         rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance,
 574                                           bMaskDWord,
 575                                           dm_tx_bb_gain[p->rfc_txpowertrackingindex_real]);
 576                 } else {
 577                         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 578                                           bMaskDWord,
 579                                           dm_tx_bb_gain[TxBBGainTableLength - 1]);
 580                         rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance,
 581                                           bMaskDWord,
 582                                           dm_tx_bb_gain[TxBBGainTableLength - 1]);
 583                 }
 584         } else {
 585                 if (p->rfa_txpowertrackingindex < (TxBBGainTableLength - 1)) {
 586                         p->rfa_txpowertrackingindex++;
 587                         p->rfa_txpowertrackingindex_real++;
 588                         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 589                                           bMaskDWord,
 590                                           dm_tx_bb_gain[p->rfa_txpowertrackingindex_real]);
 591                 } else {
 592                         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance,
 593                                           bMaskDWord,
 594                                           dm_tx_bb_gain[TxBBGainTableLength - 1]);
 595                 }
 596         }
 597 }
 598
 599 static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev)
 600 {
 601         struct r8192_priv *priv = rtllib_priv(dev);
 602         bool    bHighpowerstate, viviflag = false;
 603         struct dcmd_txcmd tx_cmd;
 604         u8      powerlevelOFDM24G;
 605         int     i = 0, j = 0, k = 0;
 606         u8      RF_Type, tmp_report[5] = {0, 0, 0, 0, 0};
 607         u32     Value;
 608         u8      Pwr_Flag;
 609         u16     Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0;
 610         u32     delta = 0;
 611
 612         RT_TRACE(COMP_POWER_TRACKING, "%s()\n", __func__);
 613         rtl92e_writeb(dev, Pw_Track_Flag, 0);
 614         rtl92e_writeb(dev, FW_Busy_Flag, 0);
 615         priv->rtllib->bdynamic_txpower_enable = false;
 616         bHighpowerstate = priv->bDynamicTxHighPower;
 617
 618         powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
 619         RF_Type = priv->rf_type;
 620         Value = (RF_Type<<8) | powerlevelOFDM24G;
 621
 622         RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n",
 623                  powerlevelOFDM24G);
 624
 625
 626         for (j = 0; j <= 30; j++) {
 627
 628                 tx_cmd.Op               = TXCMD_SET_TX_PWR_TRACKING;
 629                 tx_cmd.Length   = 4;
 630                 tx_cmd.Value            = Value;
 631                 rtl92e_send_cmd_pkt(dev, DESC_PACKET_TYPE_NORMAL, (u8 *)&tx_cmd,
 632                                     sizeof(struct dcmd_txcmd));
 633                 mdelay(1);
 634                 for (i = 0; i <= 30; i++) {
 635                         Pwr_Flag = rtl92e_readb(dev, Pw_Track_Flag);
 636
 637                         if (Pwr_Flag == 0) {
 638                                 mdelay(1);
 639
 640                                 if (priv->bResetInProgress) {
 641                                         RT_TRACE(COMP_POWER_TRACKING,
 642                                                  "we are in silent reset progress, so return\n");
 643                                         rtl92e_writeb(dev, Pw_Track_Flag, 0);
 644                                         rtl92e_writeb(dev, FW_Busy_Flag, 0);
 645                                         return;
 646                                 }
 647                                 if (priv->rtllib->eRFPowerState != eRfOn) {
 648                                         RT_TRACE(COMP_POWER_TRACKING,
 649                                                  "we are in power save, so return\n");
 650                                         rtl92e_writeb(dev, Pw_Track_Flag, 0);
 651                                         rtl92e_writeb(dev, FW_Busy_Flag, 0);
 652                                         return;
 653                                 }
 654
 655                                 continue;
 656                         }
 657
 658                         Avg_TSSI_Meas = rtl92e_readw(dev, Tssi_Mea_Value);
 659
 660                         if (Avg_TSSI_Meas == 0) {
 661                                 rtl92e_writeb(dev, Pw_Track_Flag, 0);
 662                                 rtl92e_writeb(dev, FW_Busy_Flag, 0);
 663                                 return;
 664                         }
 665
 666                         for (k = 0; k < 5; k++) {
 667                                 if (k != 4)
 668                                         tmp_report[k] = rtl92e_readb(dev,
 669                                                          Tssi_Report_Value1+k);
 670                                 else
 671                                         tmp_report[k] = rtl92e_readb(dev,
 672                                                          Tssi_Report_Value2);
 673
 674                                 RT_TRACE(COMP_POWER_TRACKING,
 675                                          "TSSI_report_value = %d\n",
 676                                          tmp_report[k]);
 677
 678                                 if (tmp_report[k] <= 20) {
 679                                         viviflag = true;
 680                                         break;
 681                                 }
 682                         }
 683
 684                         if (viviflag) {
 685                                 rtl92e_writeb(dev, Pw_Track_Flag, 0);
 686                                 viviflag = false;
 687                                 RT_TRACE(COMP_POWER_TRACKING,
 688                                          "we filted this data\n");
 689                                 for (k = 0; k < 5; k++)
 690                                         tmp_report[k] = 0;
 691                                 break;
 692                         }
 693
 694                         for (k = 0; k < 5; k++)
 695                                 Avg_TSSI_Meas_from_driver += tmp_report[k];
 696
 697                         Avg_TSSI_Meas_from_driver *= 100 / 5;
 698                         RT_TRACE(COMP_POWER_TRACKING,
 699                                  "Avg_TSSI_Meas_from_driver = %d\n",
 700                                  Avg_TSSI_Meas_from_driver);
 701                         TSSI_13dBm = priv->TSSI_13dBm;
 702                         RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n",
 703                                  TSSI_13dBm);
 704
 705                         if (Avg_TSSI_Meas_from_driver > TSSI_13dBm)
 706                                 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
 707                         else
 708                                 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
 709
 710                         if (delta <= E_FOR_TX_POWER_TRACK) {
 711                                 priv->rtllib->bdynamic_txpower_enable = true;
 712                                 rtl92e_writeb(dev, Pw_Track_Flag, 0);
 713                                 rtl92e_writeb(dev, FW_Busy_Flag, 0);
 714                                 RT_TRACE(COMP_POWER_TRACKING,
 715                                          "tx power track is done\n");
 716                                 RT_TRACE(COMP_POWER_TRACKING,
 717                                          "priv->rfa_txpowertrackingindex = %d\n",
 718                                          priv->rfa_txpowertrackingindex);
 719                                 RT_TRACE(COMP_POWER_TRACKING,
 720                                          "priv->rfa_txpowertrackingindex_real = %d\n",
 721                                          priv->rfa_txpowertrackingindex_real);
 722                                 RT_TRACE(COMP_POWER_TRACKING,
 723                                          "priv->CCKPresentAttentuation_difference = %d\n",
 724                                          priv->CCKPresentAttentuation_difference);
 725                                 RT_TRACE(COMP_POWER_TRACKING,
 726                                          "priv->CCKPresentAttentuation = %d\n",
 727                                          priv->CCKPresentAttentuation);
 728                                 return;
 729                         }
 730                         if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
 731                                 _rtl92e_dm_tx_update_tssi_weak_signal(dev,
 732                                                                       RF_Type);
 733                         else
 734                                 _rtl92e_dm_tx_update_tssi_strong_signal(dev, RF_Type);
 735
 736                         if (RF_Type == RF_2T4R) {
 737                                 priv->CCKPresentAttentuation_difference
 738                                         = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
 739                         } else {
 740                                 priv->CCKPresentAttentuation_difference
 741                                         = priv->rfa_txpowertrackingindex_real - priv->rfa_txpowertracking_default;
 742                         }
 743
 744                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 745                                 priv->CCKPresentAttentuation =
 746                                          priv->CCKPresentAttentuation_20Mdefault +
 747                                          priv->CCKPresentAttentuation_difference;
 748                         else
 749                                 priv->CCKPresentAttentuation =
 750                                          priv->CCKPresentAttentuation_40Mdefault +
 751                                          priv->CCKPresentAttentuation_difference;
 752
 753                         if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
 754                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
 755                         if (priv->CCKPresentAttentuation < 0)
 756                                 priv->CCKPresentAttentuation = 0;
 757
 758                         if (priv->CCKPresentAttentuation > -1 &&
 759                             priv->CCKPresentAttentuation < CCKTxBBGainTableLength) {
 760                                 if (priv->rtllib->current_network.channel == 14 &&
 761                                     !priv->bcck_in_ch14) {
 762                                         priv->bcck_in_ch14 = true;
 763                                         rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 764                                 } else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) {
 765                                         priv->bcck_in_ch14 = false;
 766                                         rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 767                                 } else
 768                                         rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 769                         }
 770                         RT_TRACE(COMP_POWER_TRACKING,
 771                                  "priv->rfa_txpowertrackingindex = %d\n",
 772                                  priv->rfa_txpowertrackingindex);
 773                         RT_TRACE(COMP_POWER_TRACKING,
 774                                  "priv->rfa_txpowertrackingindex_real = %d\n",
 775                                  priv->rfa_txpowertrackingindex_real);
 776                         RT_TRACE(COMP_POWER_TRACKING,
 777                                  "priv->CCKPresentAttentuation_difference = %d\n",
 778                                  priv->CCKPresentAttentuation_difference);
 779                         RT_TRACE(COMP_POWER_TRACKING,
 780                                  "priv->CCKPresentAttentuation = %d\n",
 781                                  priv->CCKPresentAttentuation);
 782
 783                         if (priv->CCKPresentAttentuation_difference <= -12 ||
 784                             priv->CCKPresentAttentuation_difference >= 24) {
 785                                 priv->rtllib->bdynamic_txpower_enable = true;
 786                                 rtl92e_writeb(dev, Pw_Track_Flag, 0);
 787                                 rtl92e_writeb(dev, FW_Busy_Flag, 0);
 788                                 RT_TRACE(COMP_POWER_TRACKING,
 789                                          "tx power track--->limited\n");
 790                                 return;
 791                         }
 792
 793                         rtl92e_writeb(dev, Pw_Track_Flag, 0);
 794                         Avg_TSSI_Meas_from_driver = 0;
 795                         for (k = 0; k < 5; k++)
 796                                 tmp_report[k] = 0;
 797                         break;
 798                 }
 799                 rtl92e_writeb(dev, FW_Busy_Flag, 0);
 800         }
 801         priv->rtllib->bdynamic_txpower_enable = true;
 802         rtl92e_writeb(dev, Pw_Track_Flag, 0);
 803 }
 804
 805 static void _rtl92e_dm_tx_power_tracking_cb_thermal(struct net_device *dev)
 806 {
 807 #define ThermalMeterVal 9
 808         struct r8192_priv *priv = rtllib_priv(dev);
 809         u32 tmpRegA, TempCCk;
 810         u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
 811         int i = 0, CCKSwingNeedUpdate = 0;
 812
 813         if (!priv->btxpower_trackingInit) {
 814                 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
 815                                             bMaskDWord);
 816                 for (i = 0; i < OFDM_Table_Length; i++) {
 817                         if (tmpRegA == OFDMSwingTable[i]) {
 818                                 priv->OFDM_index[0] = (u8)i;
 819                                 RT_TRACE(COMP_POWER_TRACKING,
 820                                          "Initial reg0x%x = 0x%x, OFDM_index = 0x%x\n",
 821                                          rOFDM0_XATxIQImbalance, tmpRegA,
 822                                          priv->OFDM_index[0]);
 823                         }
 824                 }
 825
 826                 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1, bMaskByte2);
 827                 for (i = 0; i < CCK_Table_length; i++) {
 828                         if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) {
 829                                 priv->CCK_index = (u8) i;
 830                                 RT_TRACE(COMP_POWER_TRACKING,
 831                                          "Initial reg0x%x = 0x%x, CCK_index = 0x%x\n",
 832                                          rCCK0_TxFilter1, TempCCk,
 833                                          priv->CCK_index);
 834                                 break;
 835                         }
 836                 }
 837                 priv->btxpower_trackingInit = true;
 838                 return;
 839         }
 840
 841         tmpRegA = rtl92e_get_rf_reg(dev, RF90_PATH_A, 0x12, 0x078);
 842         RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA);
 843         if (tmpRegA < 3 || tmpRegA > 13)
 844                 return;
 845         if (tmpRegA >= 12)
 846                 tmpRegA = 12;
 847         RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA);
 848         priv->ThermalMeter[0] = ThermalMeterVal;
 849         priv->ThermalMeter[1] = ThermalMeterVal;
 850
 851         if (priv->ThermalMeter[0] >= (u8)tmpRegA) {
 852                 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0] -
 853                               (u8)tmpRegA);
 854                 tmpCCK40Mindex = tmpCCK20Mindex - 6;
 855                 if (tmpOFDMindex >= OFDM_Table_Length)
 856                         tmpOFDMindex = OFDM_Table_Length-1;
 857                 if (tmpCCK20Mindex >= CCK_Table_length)
 858                         tmpCCK20Mindex = CCK_Table_length-1;
 859                 if (tmpCCK40Mindex >= CCK_Table_length)
 860                         tmpCCK40Mindex = CCK_Table_length-1;
 861         } else {
 862                 tmpval = (u8)tmpRegA - priv->ThermalMeter[0];
 863                 if (tmpval >= 6) {
 864                         tmpOFDMindex = 0;
 865                         tmpCCK20Mindex = 0;
 866                 } else {
 867                         tmpOFDMindex = 6 - tmpval;
 868                         tmpCCK20Mindex = 6 - tmpval;
 869                 }
 870                 tmpCCK40Mindex = 0;
 871         }
 872         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
 873                 tmpCCKindex = tmpCCK40Mindex;
 874         else
 875                 tmpCCKindex = tmpCCK20Mindex;
 876
 877         priv->Record_CCK_20Mindex = tmpCCK20Mindex;
 878         priv->Record_CCK_40Mindex = tmpCCK40Mindex;
 879         RT_TRACE(COMP_POWER_TRACKING,
 880                  "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
 881                  priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex);
 882
 883         if (priv->rtllib->current_network.channel == 14 &&
 884             !priv->bcck_in_ch14) {
 885                 priv->bcck_in_ch14 = true;
 886                 CCKSwingNeedUpdate = 1;
 887         } else if (priv->rtllib->current_network.channel != 14 &&
 888                    priv->bcck_in_ch14) {
 889                 priv->bcck_in_ch14 = false;
 890                 CCKSwingNeedUpdate = 1;
 891         }
 892
 893         if (priv->CCK_index != tmpCCKindex) {
 894                 priv->CCK_index = tmpCCKindex;
 895                 CCKSwingNeedUpdate = 1;
 896         }
 897
 898         if (CCKSwingNeedUpdate)
 899                 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 900         if (priv->OFDM_index[0] != tmpOFDMindex) {
 901                 priv->OFDM_index[0] = tmpOFDMindex;
 902                 rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord,
 903                                   OFDMSwingTable[priv->OFDM_index[0]]);
 904                 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
 905                          priv->OFDM_index[0],
 906                          OFDMSwingTable[priv->OFDM_index[0]]);
 907         }
 908         priv->txpower_count = 0;
 909 }
 910
 911 void rtl92e_dm_txpower_tracking_wq(void *data)
 912 {
 913         struct r8192_priv *priv = container_of_dwork_rsl(data,
 914                                   struct r8192_priv, txpower_tracking_wq);
 915         struct net_device *dev = priv->rtllib->dev;
 916
 917         if (priv->IC_Cut >= IC_VersionCut_D)
 918                 _rtl92e_dm_tx_power_tracking_callback_tssi(dev);
 919         else
 920                 _rtl92e_dm_tx_power_tracking_cb_thermal(dev);
 921 }
 922
 923 static void _rtl92e_dm_initialize_tx_power_tracking_tssi(struct net_device *dev)
 924 {
 925
 926         struct r8192_priv *priv = rtllib_priv(dev);
 927
 928         priv->btxpower_tracking = true;
 929         priv->txpower_count       = 0;
 930         priv->btxpower_trackingInit = false;
 931
 932 }
 933
 934 static void _rtl92e_dm_init_tx_power_tracking_thermal(struct net_device *dev)
 935 {
 936         struct r8192_priv *priv = rtllib_priv(dev);
 937
 938
 939         if (priv->rtllib->FwRWRF)
 940                 priv->btxpower_tracking = true;
 941         else
 942                 priv->btxpower_tracking = false;
 943         priv->txpower_count       = 0;
 944         priv->btxpower_trackingInit = false;
 945         RT_TRACE(COMP_POWER_TRACKING, "pMgntInfo->bTXPowerTracking = %d\n",
 946                  priv->btxpower_tracking);
 947 }
 948
 949 void rtl92e_dm_init_txpower_tracking(struct net_device *dev)
 950 {
 951         struct r8192_priv *priv = rtllib_priv(dev);
 952
 953         if (priv->IC_Cut >= IC_VersionCut_D)
 954                 _rtl92e_dm_initialize_tx_power_tracking_tssi(dev);
 955         else
 956                 _rtl92e_dm_init_tx_power_tracking_thermal(dev);
 957 }
 958
 959 static void _rtl92e_dm_check_tx_power_tracking_tssi(struct net_device *dev)
 960 {
 961         struct r8192_priv *priv = rtllib_priv(dev);
 962         static u32 tx_power_track_counter;
 963
 964         RT_TRACE(COMP_POWER_TRACKING, "%s()\n", __func__);
 965         if (rtl92e_readb(dev, 0x11e) == 1)
 966                 return;
 967         if (!priv->btxpower_tracking)
 968                 return;
 969         tx_power_track_counter++;
 970
 971
 972          if (tx_power_track_counter >= 180) {
 973                 schedule_delayed_work(&priv->txpower_tracking_wq, 0);
 974                 tx_power_track_counter = 0;
 975         }
 976
 977 }
 978
 979 static void _rtl92e_dm_check_tx_power_tracking_thermal(struct net_device *dev)
 980 {
 981         struct r8192_priv *priv = rtllib_priv(dev);
 982         static u8       TM_Trigger;
 983         u8              TxPowerCheckCnt = 0;
 984
 985         if (IS_HARDWARE_TYPE_8192SE(dev))
 986                 TxPowerCheckCnt = 5;
 987         else
 988                 TxPowerCheckCnt = 2;
 989         if (!priv->btxpower_tracking)
 990                 return;
 991
 992         if (priv->txpower_count  <= TxPowerCheckCnt) {
 993                 priv->txpower_count++;
 994                 return;
 995         }
 996
 997         if (!TM_Trigger) {
 998                 rtl92e_set_rf_reg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
 999                 rtl92e_set_rf_reg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1000                 rtl92e_set_rf_reg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1001                 rtl92e_set_rf_reg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1002                 TM_Trigger = 1;
1003                 return;
1004         }
1005         netdev_info(dev, "===============>Schedule TxPowerTrackingWorkItem\n");
1006         schedule_delayed_work(&priv->txpower_tracking_wq, 0);
1007         TM_Trigger = 0;
1008
1009 }
1010
1011 static void _rtl92e_dm_check_tx_power_tracking(struct net_device *dev)
1012 {
1013         struct r8192_priv *priv = rtllib_priv(dev);
1014
1015         if (priv->IC_Cut >= IC_VersionCut_D)
1016                 _rtl92e_dm_check_tx_power_tracking_tssi(dev);
1017         else
1018                 _rtl92e_dm_check_tx_power_tracking_thermal(dev);
1019 }
1020
1021 static void _rtl92e_dm_cck_tx_power_adjust_tssi(struct net_device *dev,
1022                                                 bool bInCH14)
1023 {
1024         u32 TempVal;
1025         struct r8192_priv *priv = rtllib_priv(dev);
1026         u8 attenuation = (u8)priv->CCKPresentAttentuation;
1027
1028         TempVal = 0;
1029         if (!bInCH14) {
1030                 TempVal = (u32)(dm_cck_tx_bb_gain[attenuation][0] +
1031                           (dm_cck_tx_bb_gain[attenuation][1] << 8));
1032
1033                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1034                 TempVal = (u32)((dm_cck_tx_bb_gain[attenuation][2]) +
1035                           (dm_cck_tx_bb_gain[attenuation][3] << 8) +
1036                           (dm_cck_tx_bb_gain[attenuation][4] << 16)+
1037                           (dm_cck_tx_bb_gain[attenuation][5] << 24));
1038                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1039                 TempVal = (u32)(dm_cck_tx_bb_gain[attenuation][6] +
1040                           (dm_cck_tx_bb_gain[attenuation][7] << 8));
1041
1042                 rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1043         } else {
1044                 TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][0]) +
1045                           (dm_cck_tx_bb_gain_ch14[attenuation][1] << 8));
1046
1047                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1048                 TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][2]) +
1049                           (dm_cck_tx_bb_gain_ch14[attenuation][3] << 8) +
1050                           (dm_cck_tx_bb_gain_ch14[attenuation][4] << 16)+
1051                           (dm_cck_tx_bb_gain_ch14[attenuation][5] << 24));
1052                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1053                 TempVal = (u32)((dm_cck_tx_bb_gain_ch14[attenuation][6]) +
1054                           (dm_cck_tx_bb_gain_ch14[attenuation][7] << 8));
1055
1056                 rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1057         }
1058 }
1059
1060 static void _rtl92e_dm_cck_tx_power_adjust_thermal_meter(struct net_device *dev,
1061                                                          bool bInCH14)
1062 {
1063         u32 TempVal;
1064         struct r8192_priv *priv = rtllib_priv(dev);
1065
1066         TempVal = 0;
1067         if (!bInCH14) {
1068                 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1069                           (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1] << 8);
1070                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1071                 RT_TRACE(COMP_POWER_TRACKING,
1072                          "CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_TxFilter1,
1073                          TempVal);
1074                 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1075                           (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3] << 8) +
1076                           (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4] << 16)+
1077                           (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5] << 24);
1078                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1079                 RT_TRACE(COMP_POWER_TRACKING,
1080                          "CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_TxFilter2,
1081                          TempVal);
1082                 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1083                           (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7] << 8);
1084
1085                 rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1086                 RT_TRACE(COMP_POWER_TRACKING,
1087                          "CCK not chnl 14, reg 0x%x = 0x%x\n", rCCK0_DebugPort,
1088                          TempVal);
1089         } else {
1090                 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1091                           (CCKSwingTable_Ch14[priv->CCK_index][1] << 8);
1092
1093                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1094                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1095                         rCCK0_TxFilter1, TempVal);
1096                 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1097                           (CCKSwingTable_Ch14[priv->CCK_index][3] << 8) +
1098                           (CCKSwingTable_Ch14[priv->CCK_index][4] << 16)+
1099                           (CCKSwingTable_Ch14[priv->CCK_index][5] << 24);
1100                 rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1101                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1102                         rCCK0_TxFilter2, TempVal);
1103                 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1104                           (CCKSwingTable_Ch14[priv->CCK_index][7]<<8);
1105
1106                 rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1107                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1108                         rCCK0_DebugPort, TempVal);
1109         }
1110 }
1111
1112 void rtl92e_dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1113 {
1114         struct r8192_priv *priv = rtllib_priv(dev);
1115
1116         if (priv->IC_Cut >= IC_VersionCut_D)
1117                 _rtl92e_dm_cck_tx_power_adjust_tssi(dev, binch14);
1118         else
1119                 _rtl92e_dm_cck_tx_power_adjust_thermal_meter(dev, binch14);
1120 }
1121
1122 static void _rtl92e_dm_tx_power_reset_recovery(struct net_device *dev)
1123 {
1124         struct r8192_priv *priv = rtllib_priv(dev);
1125
1126         RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1127         rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord,
1128                           dm_tx_bb_gain[priv->rfa_txpowertrackingindex]);
1129         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",
1130                  dm_tx_bb_gain[priv->rfa_txpowertrackingindex]);
1131         RT_TRACE(COMP_POWER_TRACKING,
1132                  "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",
1133                  priv->rfa_txpowertrackingindex);
1134         RT_TRACE(COMP_POWER_TRACKING,
1135                  "Reset Recovery : RF A I/Q Amplify Gain is %d\n",
1136                  dm_tx_bb_gain_idx_to_amplify(priv->rfa_txpowertrackingindex));
1137         RT_TRACE(COMP_POWER_TRACKING,
1138                  "Reset Recovery: CCK Attenuation is %d dB\n",
1139                  priv->CCKPresentAttentuation);
1140         rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1141
1142         rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord,
1143                           dm_tx_bb_gain[priv->rfc_txpowertrackingindex]);
1144         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",
1145                  dm_tx_bb_gain[priv->rfc_txpowertrackingindex]);
1146         RT_TRACE(COMP_POWER_TRACKING,
1147                  "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",
1148                  priv->rfc_txpowertrackingindex);
1149         RT_TRACE(COMP_POWER_TRACKING,
1150                  "Reset Recovery : RF C I/Q Amplify Gain is %d\n",
1151                  dm_tx_bb_gain_idx_to_amplify(priv->rfc_txpowertrackingindex));
1152 }
1153
1154 void rtl92e_dm_restore_state(struct net_device *dev)
1155 {
1156         struct r8192_priv *priv = rtllib_priv(dev);
1157         u32     reg_ratr = priv->rate_adaptive.last_ratr;
1158         u32 ratr_value;
1159
1160         if (!priv->up) {
1161                 RT_TRACE(COMP_RATE,
1162                          "<---- rtl92e_dm_restore_state(): driver is going to unload\n");
1163                 return;
1164         }
1165
1166         if (priv->rate_adaptive.rate_adaptive_disabled)
1167                 return;
1168         if (!(priv->rtllib->mode == WIRELESS_MODE_N_24G ||
1169               priv->rtllib->mode == WIRELESS_MODE_N_5G))
1170                 return;
1171         ratr_value = reg_ratr;
1172         if (priv->rf_type == RF_1T2R)
1173                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
1174         rtl92e_writel(dev, RATR0, ratr_value);
1175         rtl92e_writeb(dev, UFWP, 1);
1176         if (priv->btxpower_trackingInit && priv->btxpower_tracking)
1177                 _rtl92e_dm_tx_power_reset_recovery(dev);
1178
1179         _rtl92e_dm_bb_initialgain_restore(dev);
1180
1181 }
1182
1183 static void _rtl92e_dm_bb_initialgain_restore(struct net_device *dev)
1184 {
1185         struct r8192_priv *priv = rtllib_priv(dev);
1186         u32 bit_mask = 0x7f;
1187
1188         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1189                 return;
1190
1191         rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1192         rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, bit_mask,
1193                           (u32)priv->initgain_backup.xaagccore1);
1194         rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, bit_mask,
1195                           (u32)priv->initgain_backup.xbagccore1);
1196         rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, bit_mask,
1197                           (u32)priv->initgain_backup.xcagccore1);
1198         rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, bit_mask,
1199                           (u32)priv->initgain_backup.xdagccore1);
1200         bit_mask  = bMaskByte2;
1201         rtl92e_set_bb_reg(dev, rCCK0_CCA, bit_mask,
1202                           (u32)priv->initgain_backup.cca);
1203
1204         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",
1205                  priv->initgain_backup.xaagccore1);
1206         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",
1207                  priv->initgain_backup.xbagccore1);
1208         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",
1209                  priv->initgain_backup.xcagccore1);
1210         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",
1211                  priv->initgain_backup.xdagccore1);
1212         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",
1213                  priv->initgain_backup.cca);
1214         rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1215
1216 }
1217
1218 void rtl92e_dm_backup_state(struct net_device *dev)
1219 {
1220         struct r8192_priv *priv = rtllib_priv(dev);
1221         u32 bit_mask = bMaskByte0;
1222
1223         priv->bswitch_fsync  = false;
1224         priv->bfsync_processing = false;
1225
1226         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1227                 return;
1228
1229         rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1230         priv->initgain_backup.xaagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, bit_mask);
1231         priv->initgain_backup.xbagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, bit_mask);
1232         priv->initgain_backup.xcagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, bit_mask);
1233         priv->initgain_backup.xdagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, bit_mask);
1234         bit_mask  = bMaskByte2;
1235         priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, rCCK0_CCA, bit_mask);
1236
1237         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",
1238                  priv->initgain_backup.xaagccore1);
1239         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",
1240                  priv->initgain_backup.xbagccore1);
1241         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",
1242                  priv->initgain_backup.xcagccore1);
1243         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",
1244                  priv->initgain_backup.xdagccore1);
1245         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",
1246                  priv->initgain_backup.cca);
1247 }
1248
1249 static void _rtl92e_dm_dig_init(struct net_device *dev)
1250 {
1251         struct r8192_priv *priv = rtllib_priv(dev);
1252
1253         dm_digtable.dig_enable_flag     = true;
1254
1255         dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1256
1257         dm_digtable.dig_algorithm_switch = 0;
1258
1259         dm_digtable.dig_state           = DM_STA_DIG_MAX;
1260         dm_digtable.dig_highpwr_state   = DM_STA_DIG_MAX;
1261         dm_digtable.CurSTAConnectState = DIG_STA_DISCONNECT;
1262         dm_digtable.PreSTAConnectState = DIG_STA_DISCONNECT;
1263
1264         dm_digtable.rssi_low_thresh     = DM_DIG_THRESH_LOW;
1265         dm_digtable.rssi_high_thresh    = DM_DIG_THRESH_HIGH;
1266
1267         dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1268         dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1269
1270         dm_digtable.rssi_val = 50;
1271         dm_digtable.backoff_val = DM_DIG_BACKOFF;
1272         dm_digtable.rx_gain_range_max = DM_DIG_MAX;
1273         if (priv->CustomerID == RT_CID_819x_Netcore)
1274                 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
1275         else
1276                 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1277 }
1278
1279 static void _rtl92e_dm_ctrl_initgain_byrssi(struct net_device *dev)
1280 {
1281
1282         if (dm_digtable.dig_enable_flag == false)
1283                 return;
1284
1285         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1286                 _rtl92e_dm_ctrl_initgain_byrssi_false_alarm(dev);
1287         else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1288                 _rtl92e_dm_ctrl_initgain_byrssi_driver(dev);
1289         else
1290                 return;
1291 }
1292
1293 /*-----------------------------------------------------------------------------
1294  * Function:    dm_CtrlInitGainBeforeConnectByRssiAndFalseAlarm()
1295  *
1296  * Overview:    Driver monitor RSSI and False Alarm to change initial gain.
1297                         Only change initial gain during link in progress.
1298  *
1299  * Input:               IN      PADAPTER        pAdapter
1300  *
1301  * Output:              NONE
1302  *
1303  * Return:              NONE
1304  *
1305  * Revised History:
1306  *      When            Who             Remark
1307  *      03/04/2009      hpfan   Create Version 0.
1308  *
1309  ******************************************************************************/
1310
1311 static void _rtl92e_dm_ctrl_initgain_byrssi_driver(struct net_device *dev)
1312 {
1313         struct r8192_priv *priv = rtllib_priv(dev);
1314         u8 i;
1315         static u8       fw_dig;
1316
1317         if (dm_digtable.dig_enable_flag == false)
1318                 return;
1319
1320         if (dm_digtable.dig_algorithm_switch)
1321                 fw_dig = 0;
1322         if (fw_dig <= 3) {
1323                 for (i = 0; i < 3; i++)
1324                         rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1325                 fw_dig++;
1326                 dm_digtable.dig_state = DM_STA_DIG_OFF;
1327         }
1328
1329         if (priv->rtllib->state == RTLLIB_LINKED)
1330                 dm_digtable.CurSTAConnectState = DIG_STA_CONNECT;
1331         else
1332                 dm_digtable.CurSTAConnectState = DIG_STA_DISCONNECT;
1333
1334
1335         dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1336         _rtl92e_dm_initial_gain(dev);
1337         _rtl92e_dm_pd_th(dev);
1338         _rtl92e_dm_cs_ratio(dev);
1339         if (dm_digtable.dig_algorithm_switch)
1340                 dm_digtable.dig_algorithm_switch = 0;
1341         dm_digtable.PreSTAConnectState = dm_digtable.CurSTAConnectState;
1342
1343 }
1344
1345 static void _rtl92e_dm_ctrl_initgain_byrssi_false_alarm(struct net_device *dev)
1346 {
1347         struct r8192_priv *priv = rtllib_priv(dev);
1348         static u32 reset_cnt;
1349         u8 i;
1350
1351         if (dm_digtable.dig_enable_flag == false)
1352                 return;
1353
1354         if (dm_digtable.dig_algorithm_switch) {
1355                 dm_digtable.dig_state = DM_STA_DIG_MAX;
1356                 for (i = 0; i < 3; i++)
1357                         rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1358                 dm_digtable.dig_algorithm_switch = 0;
1359         }
1360
1361         if (priv->rtllib->state != RTLLIB_LINKED)
1362                 return;
1363
1364         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1365                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1366                 return;
1367         if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) {
1368                 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1369                         (priv->reset_count == reset_cnt))
1370                         return;
1371                 reset_cnt = priv->reset_count;
1372
1373                 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1374                 dm_digtable.dig_state = DM_STA_DIG_OFF;
1375
1376                 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1377
1378                 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, 0x17);
1379                 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, 0x17);
1380                 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, 0x17);
1381                 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, 0x17);
1382
1383                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1384                         rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x00);
1385                 else
1386                         rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x42);
1387
1388                 rtl92e_writeb(dev, 0xa0a, 0x08);
1389
1390                 return;
1391         }
1392
1393         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1394                 u8 reset_flag = 0;
1395
1396                 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1397                     (priv->reset_count == reset_cnt)) {
1398                         _rtl92e_dm_ctrl_initgain_byrssi_highpwr(dev);
1399                         return;
1400                 }
1401                 if (priv->reset_count != reset_cnt)
1402                         reset_flag = 1;
1403
1404                 reset_cnt = priv->reset_count;
1405
1406                 dm_digtable.dig_state = DM_STA_DIG_ON;
1407
1408                 if (reset_flag == 1) {
1409                         rtl92e_writeb(dev, rOFDM0_XAAGCCore1, 0x2c);
1410                         rtl92e_writeb(dev, rOFDM0_XBAGCCore1, 0x2c);
1411                         rtl92e_writeb(dev, rOFDM0_XCAGCCore1, 0x2c);
1412                         rtl92e_writeb(dev, rOFDM0_XDAGCCore1, 0x2c);
1413                 } else {
1414                         rtl92e_writeb(dev, rOFDM0_XAAGCCore1, 0x20);
1415                         rtl92e_writeb(dev, rOFDM0_XBAGCCore1, 0x20);
1416                         rtl92e_writeb(dev, rOFDM0_XCAGCCore1, 0x20);
1417                         rtl92e_writeb(dev, rOFDM0_XDAGCCore1, 0x20);
1418                 }
1419
1420                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1421                         rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x20);
1422                 else
1423                         rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x44);
1424
1425                 rtl92e_writeb(dev, 0xa0a, 0xcd);
1426
1427                 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1428         }
1429         _rtl92e_dm_ctrl_initgain_byrssi_highpwr(dev);
1430 }
1431
1432
1433 static void _rtl92e_dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev)
1434 {
1435         struct r8192_priv *priv = rtllib_priv(dev);
1436         static u32 reset_cnt_highpwr;
1437
1438         if ((priv->undecorated_smoothed_pwdb >
1439              dm_digtable.rssi_high_power_lowthresh) &&
1440             (priv->undecorated_smoothed_pwdb <
1441              dm_digtable.rssi_high_power_highthresh))
1442                 return;
1443
1444         if (priv->undecorated_smoothed_pwdb >=
1445             dm_digtable.rssi_high_power_highthresh) {
1446                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1447                         (priv->reset_count == reset_cnt_highpwr))
1448                         return;
1449                 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1450
1451                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1452                         rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x10);
1453                 else
1454                         rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x43);
1455         } else {
1456                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF &&
1457                         (priv->reset_count == reset_cnt_highpwr))
1458                         return;
1459                 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1460
1461                 if ((priv->undecorated_smoothed_pwdb <
1462                      dm_digtable.rssi_high_power_lowthresh) &&
1463                     (priv->undecorated_smoothed_pwdb >=
1464                     dm_digtable.rssi_high_thresh)) {
1465                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1466                                 rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x20);
1467                         else
1468                                 rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x44);
1469                 }
1470         }
1471         reset_cnt_highpwr = priv->reset_count;
1472 }
1473
1474 static void _rtl92e_dm_initial_gain(struct net_device *dev)
1475 {
1476         struct r8192_priv *priv = rtllib_priv(dev);
1477         u8 initial_gain = 0;
1478         static u8 initialized, force_write;
1479         static u32 reset_cnt;
1480
1481         if (dm_digtable.dig_algorithm_switch) {
1482                 initialized = 0;
1483                 reset_cnt = 0;
1484         }
1485
1486         if (rtllib_act_scanning(priv->rtllib, true) == true) {
1487                 force_write = 1;
1488                 return;
1489         }
1490
1491         if (dm_digtable.PreSTAConnectState == dm_digtable.CurSTAConnectState) {
1492                 if (dm_digtable.CurSTAConnectState == DIG_STA_CONNECT) {
1493                         long gain_range = dm_digtable.rssi_val + 10 -
1494                                           dm_digtable.backoff_val;
1495                         gain_range = clamp_t(long, gain_range,
1496                                              dm_digtable.rx_gain_range_min,
1497                                              dm_digtable.rx_gain_range_max);
1498                         dm_digtable.cur_ig_value = gain_range;
1499                 } else {
1500                         if (dm_digtable.cur_ig_value == 0)
1501                                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1502                         else
1503                                 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
1504                 }
1505         } else {
1506                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1507                 dm_digtable.pre_ig_value = 0;
1508         }
1509
1510         if (priv->reset_count != reset_cnt) {
1511                 force_write = 1;
1512                 reset_cnt = priv->reset_count;
1513         }
1514
1515         if (dm_digtable.pre_ig_value != rtl92e_readb(dev, rOFDM0_XAAGCCore1))
1516                 force_write = 1;
1517
1518         if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
1519             || !initialized || force_write) {
1520                 initial_gain = (u8)dm_digtable.cur_ig_value;
1521                 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain);
1522                 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain);
1523                 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain);
1524                 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain);
1525                 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1526                 initialized = 1;
1527                 force_write = 0;
1528         }
1529 }
1530
1531 static void _rtl92e_dm_pd_th(struct net_device *dev)
1532 {
1533         struct r8192_priv *priv = rtllib_priv(dev);
1534         static u8 initialized, force_write;
1535         static u32 reset_cnt;
1536
1537         if (dm_digtable.dig_algorithm_switch) {
1538                 initialized = 0;
1539                 reset_cnt = 0;
1540         }
1541
1542         if (dm_digtable.PreSTAConnectState == dm_digtable.CurSTAConnectState) {
1543                 if (dm_digtable.CurSTAConnectState == DIG_STA_CONNECT) {
1544                         if (dm_digtable.rssi_val >=
1545                             dm_digtable.rssi_high_power_highthresh)
1546                                 dm_digtable.curpd_thstate =
1547                                                         DIG_PD_AT_HIGH_POWER;
1548                         else if (dm_digtable.rssi_val <=
1549                                  dm_digtable.rssi_low_thresh)
1550                                 dm_digtable.curpd_thstate =
1551                                                         DIG_PD_AT_LOW_POWER;
1552                         else if ((dm_digtable.rssi_val >=
1553                                   dm_digtable.rssi_high_thresh) &&
1554                                  (dm_digtable.rssi_val <
1555                                   dm_digtable.rssi_high_power_lowthresh))
1556                                 dm_digtable.curpd_thstate =
1557                                                         DIG_PD_AT_NORMAL_POWER;
1558                         else
1559                                 dm_digtable.curpd_thstate =
1560                                                 dm_digtable.prepd_thstate;
1561                 } else {
1562                         dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1563                 }
1564         } else {
1565                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1566         }
1567
1568         if (priv->reset_count != reset_cnt) {
1569                 force_write = 1;
1570                 reset_cnt = priv->reset_count;
1571         }
1572
1573         if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
1574             (initialized <= 3) || force_write) {
1575                 if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) {
1576                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1577                                 rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x00);
1578                         else
1579                                 rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x42);
1580                 } else if (dm_digtable.curpd_thstate ==
1581                            DIG_PD_AT_NORMAL_POWER) {
1582                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1583                                 rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x20);
1584                         else
1585                                 rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x44);
1586                 } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) {
1587                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1588                                 rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x10);
1589                         else
1590                                 rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x43);
1591                 }
1592                 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
1593                 if (initialized <= 3)
1594                         initialized++;
1595                 force_write = 0;
1596         }
1597 }
1598
1599 static void _rtl92e_dm_cs_ratio(struct net_device *dev)
1600 {
1601         struct r8192_priv *priv = rtllib_priv(dev);
1602         static u8 initialized, force_write;
1603         static u32 reset_cnt;
1604
1605         if (dm_digtable.dig_algorithm_switch) {
1606                 initialized = 0;
1607                 reset_cnt = 0;
1608         }
1609
1610         if (dm_digtable.PreSTAConnectState == dm_digtable.CurSTAConnectState) {
1611                 if (dm_digtable.CurSTAConnectState == DIG_STA_CONNECT) {
1612                         if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
1613                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
1614                         else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh)
1615                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
1616                         else
1617                                 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
1618                 } else {
1619                         dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
1620                 }
1621         } else {
1622                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
1623         }
1624
1625         if (priv->reset_count != reset_cnt) {
1626                 force_write = 1;
1627                 reset_cnt = priv->reset_count;
1628         }
1629
1630
1631         if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
1632             !initialized || force_write) {
1633                 if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
1634                         rtl92e_writeb(dev, 0xa0a, 0x08);
1635                 else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
1636                         rtl92e_writeb(dev, 0xa0a, 0xcd);
1637                 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
1638                 initialized = 1;
1639                 force_write = 0;
1640         }
1641 }
1642
1643 void rtl92e_dm_init_edca_turbo(struct net_device *dev)
1644 {
1645         struct r8192_priv *priv = rtllib_priv(dev);
1646
1647         priv->bcurrent_turbo_EDCA = false;
1648         priv->rtllib->bis_any_nonbepkts = false;
1649         priv->bis_cur_rdlstate = false;
1650 }
1651
1652 static void _rtl92e_dm_check_edca_turbo(struct net_device *dev)
1653 {
1654         struct r8192_priv *priv = rtllib_priv(dev);
1655         struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo;
1656
1657         static unsigned long lastTxOkCnt;
1658         static unsigned long lastRxOkCnt;
1659         unsigned long curTxOkCnt = 0;
1660         unsigned long curRxOkCnt = 0;
1661
1662         if (priv->rtllib->iw_mode == IW_MODE_ADHOC)
1663                 goto dm_CheckEdcaTurbo_EXIT;
1664         if (priv->rtllib->state != RTLLIB_LINKED)
1665                 goto dm_CheckEdcaTurbo_EXIT;
1666         if (priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
1667                 goto dm_CheckEdcaTurbo_EXIT;
1668
1669         if (!priv->rtllib->bis_any_nonbepkts) {
1670                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
1671                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
1672                 if (pHTInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX) {
1673                         if (curTxOkCnt > 4*curRxOkCnt) {
1674                                 if (priv->bis_cur_rdlstate ||
1675                                     !priv->bcurrent_turbo_EDCA) {
1676                                         rtl92e_writel(dev, EDCAPARA_BE,
1677                                                       edca_setting_UL[pHTInfo->IOTPeer]);
1678                                         priv->bis_cur_rdlstate = false;
1679                                 }
1680                         } else {
1681                                 if (!priv->bis_cur_rdlstate ||
1682                                     !priv->bcurrent_turbo_EDCA) {
1683                                         if (priv->rtllib->mode == WIRELESS_MODE_G)
1684                                                 rtl92e_writel(dev, EDCAPARA_BE,
1685                                                               edca_setting_DL_GMode[pHTInfo->IOTPeer]);
1686                                         else
1687                                                 rtl92e_writel(dev, EDCAPARA_BE,
1688                                                               edca_setting_DL[pHTInfo->IOTPeer]);
1689                                         priv->bis_cur_rdlstate = true;
1690                                 }
1691                         }
1692                         priv->bcurrent_turbo_EDCA = true;
1693                 } else {
1694                         if (curRxOkCnt > 4*curTxOkCnt) {
1695                                 if (!priv->bis_cur_rdlstate ||
1696                                     !priv->bcurrent_turbo_EDCA) {
1697                                         if (priv->rtllib->mode == WIRELESS_MODE_G)
1698                                                 rtl92e_writel(dev, EDCAPARA_BE,
1699                                                               edca_setting_DL_GMode[pHTInfo->IOTPeer]);
1700                                         else
1701                                                 rtl92e_writel(dev, EDCAPARA_BE,
1702                                                               edca_setting_DL[pHTInfo->IOTPeer]);
1703                                         priv->bis_cur_rdlstate = true;
1704                                 }
1705                         } else {
1706                                 if (priv->bis_cur_rdlstate ||
1707                                     !priv->bcurrent_turbo_EDCA) {
1708                                         rtl92e_writel(dev, EDCAPARA_BE,
1709                                                       edca_setting_UL[pHTInfo->IOTPeer]);
1710                                         priv->bis_cur_rdlstate = false;
1711                                 }
1712
1713                         }
1714
1715                         priv->bcurrent_turbo_EDCA = true;
1716                 }
1717         } else {
1718                  if (priv->bcurrent_turbo_EDCA) {
1719                         u8 tmp = AC0_BE;
1720
1721                         priv->rtllib->SetHwRegHandler(dev, HW_VAR_AC_PARAM,
1722                                                       (u8 *)(&tmp));
1723                         priv->bcurrent_turbo_EDCA = false;
1724                 }
1725         }
1726
1727
1728 dm_CheckEdcaTurbo_EXIT:
1729         priv->rtllib->bis_any_nonbepkts = false;
1730         lastTxOkCnt = priv->stats.txbytesunicast;
1731         lastRxOkCnt = priv->stats.rxbytesunicast;
1732 }
1733
1734 static void _rtl92e_dm_init_cts_to_self(struct net_device *dev)
1735 {
1736         struct r8192_priv *priv = rtllib_priv((struct net_device *)dev);
1737
1738         priv->rtllib->bCTSToSelfEnable = true;
1739 }
1740
1741 static void _rtl92e_dm_cts_to_self(struct net_device *dev)
1742 {
1743         struct r8192_priv *priv = rtllib_priv((struct net_device *)dev);
1744         struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo;
1745         static unsigned long lastTxOkCnt;
1746         static unsigned long lastRxOkCnt;
1747         unsigned long curTxOkCnt = 0;
1748         unsigned long curRxOkCnt = 0;
1749
1750         if (priv->rtllib->bCTSToSelfEnable != true) {
1751                 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
1752                 return;
1753         }
1754         if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {
1755                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
1756                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
1757                 if (curRxOkCnt > 4*curTxOkCnt)
1758                         pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
1759                 else
1760                         pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
1761
1762                 lastTxOkCnt = priv->stats.txbytesunicast;
1763                 lastRxOkCnt = priv->stats.rxbytesunicast;
1764         }
1765 }
1766
1767
1768 static void _rtl92e_dm_init_wa_broadcom_iot(struct net_device *dev)
1769 {
1770         struct r8192_priv *priv = rtllib_priv((struct net_device *)dev);
1771         struct rt_hi_throughput *pHTInfo = priv->rtllib->pHTInfo;
1772
1773         pHTInfo->bWAIotBroadcom = false;
1774         pHTInfo->WAIotTH = WAIotTHVal;
1775 }
1776
1777 static void _rtl92e_dm_check_rf_ctrl_gpio(void *data)
1778 {
1779         struct r8192_priv *priv = container_of_dwork_rsl(data,
1780                                   struct r8192_priv, gpio_change_rf_wq);
1781         struct net_device *dev = priv->rtllib->dev;
1782         u8 tmp1byte;
1783         enum rt_rf_power_state eRfPowerStateToSet;
1784         bool bActuallySet = false;
1785
1786         bActuallySet = false;
1787
1788         if ((priv->up_first_time == 1) || (priv->being_init_adapter))
1789                 return;
1790
1791         if (priv->bfirst_after_down) {
1792                 priv->bfirst_after_down = true;
1793                 return;
1794         }
1795
1796         tmp1byte = rtl92e_readb(dev, GPI);
1797
1798         eRfPowerStateToSet = (tmp1byte&BIT1) ?  eRfOn : eRfOff;
1799
1800         if (priv->bHwRadioOff && (eRfPowerStateToSet == eRfOn)) {
1801                 RT_TRACE(COMP_RF, "gpiochangeRF  - HW Radio ON\n");
1802                 netdev_info(dev, "gpiochangeRF  - HW Radio ON\n");
1803                 priv->bHwRadioOff = false;
1804                 bActuallySet = true;
1805         } else if (!priv->bHwRadioOff && (eRfPowerStateToSet == eRfOff)) {
1806                 RT_TRACE(COMP_RF, "gpiochangeRF  - HW Radio OFF\n");
1807                 netdev_info(dev, "gpiochangeRF  - HW Radio OFF\n");
1808                 priv->bHwRadioOff = true;
1809                 bActuallySet = true;
1810         }
1811
1812         if (bActuallySet) {
1813                 mdelay(1000);
1814                 priv->bHwRfOffAction = 1;
1815                 rtl92e_set_rf_state(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
1816         }
1817 }
1818
1819 void rtl92e_dm_rf_pathcheck_wq(void *data)
1820 {
1821         struct r8192_priv *priv = container_of_dwork_rsl(data,
1822                                   struct r8192_priv,
1823                                   rfpath_check_wq);
1824         struct net_device *dev = priv->rtllib->dev;
1825         u8 rfpath, i;
1826
1827         rfpath = rtl92e_readb(dev, 0xc04);
1828
1829         for (i = 0; i < RF90_PATH_MAX; i++) {
1830                 if (rfpath & (0x01<<i))
1831                         priv->brfpath_rxenable[i] = true;
1832                 else
1833                         priv->brfpath_rxenable[i] = false;
1834         }
1835         if (!DM_RxPathSelTable.Enable)
1836                 return;
1837
1838         _rtl92e_dm_rx_path_sel_byrssi(dev);
1839 }
1840
1841 static void _rtl92e_dm_init_rx_path_selection(struct net_device *dev)
1842 {
1843         u8 i;
1844         struct r8192_priv *priv = rtllib_priv(dev);
1845
1846         DM_RxPathSelTable.Enable = 1;
1847         DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
1848         DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
1849         if (priv->CustomerID == RT_CID_819x_Netcore)
1850                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
1851         else
1852                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
1853         DM_RxPathSelTable.disabledRF = 0;
1854         for (i = 0; i < 4; i++) {
1855                 DM_RxPathSelTable.rf_rssi[i] = 50;
1856                 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
1857                 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
1858         }
1859 }
1860
1861 #define PWDB_IN_RANGE   ((cur_cck_pwdb < tmp_cck_max_pwdb) &&   \
1862                         (cur_cck_pwdb > tmp_cck_sec_pwdb))
1863
1864 static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev)
1865 {
1866         struct r8192_priv *priv = rtllib_priv(dev);
1867         u8 i, max_rssi_index = 0, min_rssi_index = 0;
1868         u8 sec_rssi_index = 0, rf_num = 0;
1869         u8 tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0;
1870         u8 cck_default_Rx = 0x2;
1871         u8 cck_optional_Rx = 0x3;
1872         long tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0;
1873         u8 cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0;
1874         u8 cck_rx_ver2_sec_index = 0;
1875         u8 cur_rf_rssi;
1876         long cur_cck_pwdb;
1877         static u8 disabled_rf_cnt, cck_Rx_Path_initialized;
1878         u8 update_cck_rx_path;
1879
1880         if (priv->rf_type != RF_2T4R)
1881                 return;
1882
1883         if (!cck_Rx_Path_initialized) {
1884                 DM_RxPathSelTable.cck_Rx_path = (rtl92e_readb(dev, 0xa07)&0xf);
1885                 cck_Rx_Path_initialized = 1;
1886         }
1887
1888         DM_RxPathSelTable.disabledRF = 0xf;
1889         DM_RxPathSelTable.disabledRF &= ~(rtl92e_readb(dev, 0xc04));
1890
1891         if (priv->rtllib->mode == WIRELESS_MODE_B)
1892                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
1893
1894         for (i = 0; i < RF90_PATH_MAX; i++) {
1895                 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
1896
1897                 if (priv->brfpath_rxenable[i]) {
1898                         rf_num++;
1899                         cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
1900
1901                         if (rf_num == 1) {
1902                                 max_rssi_index = min_rssi_index = sec_rssi_index = i;
1903                                 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
1904                         } else if (rf_num == 2) {
1905                                 if (cur_rf_rssi >= tmp_max_rssi) {
1906                                         tmp_max_rssi = cur_rf_rssi;
1907                                         max_rssi_index = i;
1908                                 } else {
1909                                         tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
1910                                         sec_rssi_index = min_rssi_index = i;
1911                                 }
1912                         } else {
1913                                 if (cur_rf_rssi > tmp_max_rssi) {
1914                                         tmp_sec_rssi = tmp_max_rssi;
1915                                         sec_rssi_index = max_rssi_index;
1916                                         tmp_max_rssi = cur_rf_rssi;
1917                                         max_rssi_index = i;
1918                                 } else if (cur_rf_rssi == tmp_max_rssi) {
1919                                         tmp_sec_rssi = cur_rf_rssi;
1920                                         sec_rssi_index = i;
1921                                 } else if ((cur_rf_rssi < tmp_max_rssi) &&
1922                                            (cur_rf_rssi > tmp_sec_rssi)) {
1923                                         tmp_sec_rssi = cur_rf_rssi;
1924                                         sec_rssi_index = i;
1925                                 } else if (cur_rf_rssi == tmp_sec_rssi) {
1926                                         if (tmp_sec_rssi == tmp_min_rssi) {
1927                                                 tmp_sec_rssi = cur_rf_rssi;
1928                                                 sec_rssi_index = i;
1929                                         }
1930                                 } else if ((cur_rf_rssi < tmp_sec_rssi) &&
1931                                            (cur_rf_rssi > tmp_min_rssi)) {
1932                                         ;
1933                                 } else if (cur_rf_rssi == tmp_min_rssi) {
1934                                         if (tmp_sec_rssi == tmp_min_rssi) {
1935                                                 tmp_min_rssi = cur_rf_rssi;
1936                                                 min_rssi_index = i;
1937                                         }
1938                                 } else if (cur_rf_rssi < tmp_min_rssi) {
1939                                         tmp_min_rssi = cur_rf_rssi;
1940                                         min_rssi_index = i;
1941                                 }
1942                         }
1943                 }
1944         }
1945
1946         rf_num = 0;
1947         if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) {
1948                 for (i = 0; i < RF90_PATH_MAX; i++) {
1949                         if (priv->brfpath_rxenable[i]) {
1950                                 rf_num++;
1951                                 cur_cck_pwdb =
1952                                          DM_RxPathSelTable.cck_pwdb_sta[i];
1953
1954                                 if (rf_num == 1) {
1955                                         cck_rx_ver2_max_index = i;
1956                                         cck_rx_ver2_min_index = i;
1957                                         cck_rx_ver2_sec_index = i;
1958                                         tmp_cck_max_pwdb = cur_cck_pwdb;
1959                                         tmp_cck_min_pwdb = cur_cck_pwdb;
1960                                         tmp_cck_sec_pwdb = cur_cck_pwdb;
1961                                 } else if (rf_num == 2) {
1962                                         if (cur_cck_pwdb >= tmp_cck_max_pwdb) {
1963                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
1964                                                 cck_rx_ver2_max_index = i;
1965                                         } else {
1966                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
1967                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
1968                                                 cck_rx_ver2_sec_index = i;
1969                                                 cck_rx_ver2_min_index = i;
1970                                         }
1971                                 } else {
1972                                         if (cur_cck_pwdb > tmp_cck_max_pwdb) {
1973                                                 tmp_cck_sec_pwdb =
1974                                                          tmp_cck_max_pwdb;
1975                                                 cck_rx_ver2_sec_index =
1976                                                          cck_rx_ver2_max_index;
1977                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
1978                                                 cck_rx_ver2_max_index = i;
1979                                         } else if (cur_cck_pwdb ==
1980                                                    tmp_cck_max_pwdb) {
1981                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
1982                                                 cck_rx_ver2_sec_index = i;
1983                                         } else if (PWDB_IN_RANGE) {
1984                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
1985                                                 cck_rx_ver2_sec_index = i;
1986                                         } else if (cur_cck_pwdb ==
1987                                                    tmp_cck_sec_pwdb) {
1988                                                 if (tmp_cck_sec_pwdb ==
1989                                                     tmp_cck_min_pwdb) {
1990                                                         tmp_cck_sec_pwdb =
1991                                                                  cur_cck_pwdb;
1992                                                         cck_rx_ver2_sec_index =
1993                                                                  i;
1994                                                 }
1995                                         } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) &&
1996                                                    (cur_cck_pwdb > tmp_cck_min_pwdb)) {
1997                                                 ;
1998                                         } else if (cur_cck_pwdb == tmp_cck_min_pwdb) {
1999                                                 if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2000                                                         tmp_cck_min_pwdb = cur_cck_pwdb;
2001                                                         cck_rx_ver2_min_index = i;
2002                                                 }
2003                                         } else if (cur_cck_pwdb < tmp_cck_min_pwdb) {
2004                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
2005                                                 cck_rx_ver2_min_index = i;
2006                                         }
2007                                 }
2008
2009                         }
2010                 }
2011         }
2012
2013         update_cck_rx_path = 0;
2014         if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) {
2015                 cck_default_Rx = cck_rx_ver2_max_index;
2016                 cck_optional_Rx = cck_rx_ver2_sec_index;
2017                 if (tmp_cck_max_pwdb != -64)
2018                         update_cck_rx_path = 1;
2019         }
2020
2021         if (tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) {
2022                 if ((tmp_max_rssi - tmp_min_rssi) >=
2023                      DM_RxPathSelTable.diff_TH) {
2024                         DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] =
2025                                  tmp_max_rssi+5;
2026                         rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
2027                                           0x1<<min_rssi_index, 0x0);
2028                         rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
2029                                           0x1<<min_rssi_index, 0x0);
2030                         disabled_rf_cnt++;
2031                 }
2032                 if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) {
2033                         cck_default_Rx = max_rssi_index;
2034                         cck_optional_Rx = sec_rssi_index;
2035                         if (tmp_max_rssi)
2036                                 update_cck_rx_path = 1;
2037                 }
2038         }
2039
2040         if (update_cck_rx_path) {
2041                 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2) |
2042                                                 (cck_optional_Rx);
2043                 rtl92e_set_bb_reg(dev, rCCK0_AFESetting, 0x0f000000,
2044                                   DM_RxPathSelTable.cck_Rx_path);
2045         }
2046
2047         if (DM_RxPathSelTable.disabledRF) {
2048                 for (i = 0; i < 4; i++) {
2049                         if ((DM_RxPathSelTable.disabledRF>>i) & 0x1) {
2050                                 if (tmp_max_rssi >=
2051                                     DM_RxPathSelTable.rf_enable_rssi_th[i]) {
2052                                         rtl92e_set_bb_reg(dev,
2053                                                           rOFDM0_TRxPathEnable,
2054                                                           0x1 << i, 0x1);
2055                                         rtl92e_set_bb_reg(dev,
2056                                                           rOFDM1_TRxPathEnable,
2057                                                           0x1 << i, 0x1);
2058                                         DM_RxPathSelTable.rf_enable_rssi_th[i]
2059                                                  = 100;
2060                                         disabled_rf_cnt--;
2061                                 }
2062                         }
2063                 }
2064         }
2065 }
2066
2067 static void _rtl92e_dm_check_rx_path_selection(struct net_device *dev)
2068 {
2069         struct r8192_priv *priv = rtllib_priv(dev);
2070
2071         schedule_delayed_work(&priv->rfpath_check_wq, 0);
2072 }
2073
2074
2075 static void _rtl92e_dm_init_fsync(struct net_device *dev)
2076 {
2077         struct r8192_priv *priv = rtllib_priv(dev);
2078
2079         priv->rtllib->fsync_time_interval = 500;
2080         priv->rtllib->fsync_rate_bitmap = 0x0f000800;
2081         priv->rtllib->fsync_rssi_threshold = 30;
2082         priv->rtllib->bfsync_enable = false;
2083         priv->rtllib->fsync_multiple_timeinterval = 3;
2084         priv->rtllib->fsync_firstdiff_ratethreshold = 100;
2085         priv->rtllib->fsync_seconddiff_ratethreshold = 200;
2086         priv->rtllib->fsync_state = Default_Fsync;
2087         priv->framesyncMonitor = 1;
2088
2089         setup_timer(&priv->fsync_timer, _rtl92e_dm_fsync_timer_callback,
2090                     (unsigned long)dev);
2091 }
2092
2093
2094 static void _rtl92e_dm_deinit_fsync(struct net_device *dev)
2095 {
2096         struct r8192_priv *priv = rtllib_priv(dev);
2097
2098         del_timer_sync(&priv->fsync_timer);
2099 }
2100
2101 static void _rtl92e_dm_fsync_timer_callback(unsigned long data)
2102 {
2103         struct net_device *dev = (struct net_device *)data;
2104         struct r8192_priv *priv = rtllib_priv((struct net_device *)data);
2105         u32 rate_index, rate_count = 0, rate_count_diff = 0;
2106         bool            bSwitchFromCountDiff = false;
2107         bool            bDoubleTimeInterval = false;
2108
2109         if (priv->rtllib->state == RTLLIB_LINKED &&
2110             priv->rtllib->bfsync_enable &&
2111             (priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2112                 u32 rate_bitmap;
2113
2114                 for (rate_index = 0; rate_index <= 27; rate_index++) {
2115                         rate_bitmap  = 1 << rate_index;
2116                         if (priv->rtllib->fsync_rate_bitmap &  rate_bitmap)
2117                                 rate_count +=
2118                                    priv->stats.received_rate_histogram[1]
2119                                    [rate_index];
2120                 }
2121
2122                 if (rate_count < priv->rate_record)
2123                         rate_count_diff = 0xffffffff - rate_count +
2124                                           priv->rate_record;
2125                 else
2126                         rate_count_diff = rate_count - priv->rate_record;
2127                 if (rate_count_diff < priv->rateCountDiffRecord) {
2128
2129                         u32 DiffNum = priv->rateCountDiffRecord -
2130                                       rate_count_diff;
2131                         if (DiffNum >=
2132                             priv->rtllib->fsync_seconddiff_ratethreshold)
2133                                 priv->ContinueDiffCount++;
2134                         else
2135                                 priv->ContinueDiffCount = 0;
2136
2137                         if (priv->ContinueDiffCount >= 2) {
2138                                 bSwitchFromCountDiff = true;
2139                                 priv->ContinueDiffCount = 0;
2140                         }
2141                 } else {
2142                         priv->ContinueDiffCount = 0;
2143                 }
2144
2145                 if (rate_count_diff <=
2146                     priv->rtllib->fsync_firstdiff_ratethreshold) {
2147                         bSwitchFromCountDiff = true;
2148                         priv->ContinueDiffCount = 0;
2149                 }
2150                 priv->rate_record = rate_count;
2151                 priv->rateCountDiffRecord = rate_count_diff;
2152                 RT_TRACE(COMP_HALDM,
2153                          "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n",
2154                          priv->rate_record, rate_count, rate_count_diff,
2155                          priv->bswitch_fsync);
2156                 if (priv->undecorated_smoothed_pwdb >
2157                     priv->rtllib->fsync_rssi_threshold &&
2158                     bSwitchFromCountDiff) {
2159                         bDoubleTimeInterval = true;
2160                         priv->bswitch_fsync = !priv->bswitch_fsync;
2161                         if (priv->bswitch_fsync) {
2162                                 rtl92e_writeb(dev, 0xC36, 0x1c);
2163                                 rtl92e_writeb(dev, 0xC3e, 0x90);
2164                         } else {
2165                                 rtl92e_writeb(dev, 0xC36, 0x5c);
2166                                 rtl92e_writeb(dev, 0xC3e, 0x96);
2167                         }
2168                 } else if (priv->undecorated_smoothed_pwdb <=
2169                            priv->rtllib->fsync_rssi_threshold) {
2170                         if (priv->bswitch_fsync) {
2171                                 priv->bswitch_fsync  = false;
2172                                 rtl92e_writeb(dev, 0xC36, 0x5c);
2173                                 rtl92e_writeb(dev, 0xC3e, 0x96);
2174                         }
2175                 }
2176                 if (bDoubleTimeInterval) {
2177                         if (timer_pending(&priv->fsync_timer))
2178                                 del_timer_sync(&priv->fsync_timer);
2179                         priv->fsync_timer.expires = jiffies +
2180                                  msecs_to_jiffies(priv->rtllib->fsync_time_interval *
2181                                  priv->rtllib->fsync_multiple_timeinterval);
2182                         add_timer(&priv->fsync_timer);
2183                 } else {
2184                         if (timer_pending(&priv->fsync_timer))
2185                                 del_timer_sync(&priv->fsync_timer);
2186                         priv->fsync_timer.expires = jiffies +
2187                                  msecs_to_jiffies(priv->rtllib->fsync_time_interval);
2188                         add_timer(&priv->fsync_timer);
2189                 }
2190         } else {
2191                 if (priv->bswitch_fsync) {
2192                         priv->bswitch_fsync  = false;
2193                         rtl92e_writeb(dev, 0xC36, 0x5c);
2194                         rtl92e_writeb(dev, 0xC3e, 0x96);
2195                 }
2196                 priv->ContinueDiffCount = 0;
2197                 rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c52cd);
2198         }
2199         RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount);
2200         RT_TRACE(COMP_HALDM,
2201                  "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n",
2202                  priv->rate_record, rate_count, rate_count_diff,
2203                  priv->bswitch_fsync);
2204 }
2205
2206 static void _rtl92e_dm_start_hw_fsync(struct net_device *dev)
2207 {
2208         u8 rf_timing = 0x77;
2209         struct r8192_priv *priv = rtllib_priv(dev);
2210
2211         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2212         rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c12cf);
2213         priv->rtllib->SetHwRegHandler(dev, HW_VAR_RF_TIMING,
2214                                       (u8 *)(&rf_timing));
2215         rtl92e_writeb(dev, 0xc3b, 0x41);
2216 }
2217
2218 static void _rtl92e_dm_end_hw_fsync(struct net_device *dev)
2219 {
2220         u8 rf_timing = 0xaa;
2221         struct r8192_priv *priv = rtllib_priv(dev);
2222
2223         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2224         rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c52cd);
2225         priv->rtllib->SetHwRegHandler(dev, HW_VAR_RF_TIMING, (u8 *)
2226                                      (&rf_timing));
2227         rtl92e_writeb(dev, 0xc3b, 0x49);
2228 }
2229
2230 static void _rtl92e_dm_end_sw_fsync(struct net_device *dev)
2231 {
2232         struct r8192_priv *priv = rtllib_priv(dev);
2233
2234         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2235         del_timer_sync(&(priv->fsync_timer));
2236
2237         if (priv->bswitch_fsync) {
2238                 priv->bswitch_fsync  = false;
2239
2240                 rtl92e_writeb(dev, 0xC36, 0x5c);
2241
2242                 rtl92e_writeb(dev, 0xC3e, 0x96);
2243         }
2244
2245         priv->ContinueDiffCount = 0;
2246         rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c52cd);
2247 }
2248
2249 static void _rtl92e_dm_start_sw_fsync(struct net_device *dev)
2250 {
2251         struct r8192_priv *priv = rtllib_priv(dev);
2252         u32                     rateIndex;
2253         u32                     rateBitmap;
2254
2255         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2256         priv->rate_record = 0;
2257         priv->ContinueDiffCount = 0;
2258         priv->rateCountDiffRecord = 0;
2259         priv->bswitch_fsync  = false;
2260
2261         if (priv->rtllib->mode == WIRELESS_MODE_N_24G) {
2262                 priv->rtllib->fsync_firstdiff_ratethreshold = 600;
2263                 priv->rtllib->fsync_seconddiff_ratethreshold = 0xffff;
2264         } else {
2265                 priv->rtllib->fsync_firstdiff_ratethreshold = 200;
2266                 priv->rtllib->fsync_seconddiff_ratethreshold = 200;
2267         }
2268         for (rateIndex = 0; rateIndex <= 27; rateIndex++) {
2269                 rateBitmap  = 1 << rateIndex;
2270                 if (priv->rtllib->fsync_rate_bitmap & rateBitmap)
2271                         priv->rate_record +=
2272                                  priv->stats.received_rate_histogram[1]
2273                                 [rateIndex];
2274         }
2275         if (timer_pending(&priv->fsync_timer))
2276                 del_timer_sync(&priv->fsync_timer);
2277         priv->fsync_timer.expires = jiffies +
2278                                     msecs_to_jiffies(priv->rtllib->fsync_time_interval);
2279         add_timer(&priv->fsync_timer);
2280
2281         rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c12cd);
2282
2283 }
2284
2285 static void _rtl92e_dm_check_fsync(struct net_device *dev)
2286 {
2287 #define RegC38_Default                  0
2288 #define RegC38_NonFsync_Other_AP        1
2289 #define RegC38_Fsync_AP_BCM             2
2290         struct r8192_priv *priv = rtllib_priv(dev);
2291         static u8 reg_c38_State = RegC38_Default;
2292         static u32 reset_cnt;
2293
2294         RT_TRACE(COMP_HALDM,
2295                  "RSSI %d TimeInterval %d MultipleTimeInterval %d\n",
2296                  priv->rtllib->fsync_rssi_threshold,
2297                  priv->rtllib->fsync_time_interval,
2298                  priv->rtllib->fsync_multiple_timeinterval);
2299         RT_TRACE(COMP_HALDM,
2300                  "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n",
2301                  priv->rtllib->fsync_rate_bitmap,
2302                  priv->rtllib->fsync_firstdiff_ratethreshold,
2303                  priv->rtllib->fsync_seconddiff_ratethreshold);
2304
2305         if (priv->rtllib->state == RTLLIB_LINKED &&
2306             priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {
2307                 if (priv->rtllib->bfsync_enable == 0) {
2308                         switch (priv->rtllib->fsync_state) {
2309                         case Default_Fsync:
2310                                 _rtl92e_dm_start_hw_fsync(dev);
2311                                 priv->rtllib->fsync_state = HW_Fsync;
2312                                 break;
2313                         case SW_Fsync:
2314                                 _rtl92e_dm_end_sw_fsync(dev);
2315                                 _rtl92e_dm_start_hw_fsync(dev);
2316                                 priv->rtllib->fsync_state = HW_Fsync;
2317                                 break;
2318                         case HW_Fsync:
2319                         default:
2320                                 break;
2321                         }
2322                 } else {
2323                         switch (priv->rtllib->fsync_state) {
2324                         case Default_Fsync:
2325                                 _rtl92e_dm_start_sw_fsync(dev);
2326                                 priv->rtllib->fsync_state = SW_Fsync;
2327                                 break;
2328                         case HW_Fsync:
2329                                 _rtl92e_dm_end_hw_fsync(dev);
2330                                 _rtl92e_dm_start_sw_fsync(dev);
2331                                 priv->rtllib->fsync_state = SW_Fsync;
2332                                 break;
2333                         case SW_Fsync:
2334                         default:
2335                                 break;
2336
2337                         }
2338                 }
2339                 if (priv->framesyncMonitor) {
2340                         if (reg_c38_State != RegC38_Fsync_AP_BCM) {
2341                                 rtl92e_writeb(dev, rOFDM0_RxDetector3, 0x95);
2342
2343                                 reg_c38_State = RegC38_Fsync_AP_BCM;
2344                         }
2345                 }
2346         } else {
2347                 switch (priv->rtllib->fsync_state) {
2348                 case HW_Fsync:
2349                         _rtl92e_dm_end_hw_fsync(dev);
2350                         priv->rtllib->fsync_state = Default_Fsync;
2351                         break;
2352                 case SW_Fsync:
2353                         _rtl92e_dm_end_sw_fsync(dev);
2354                         priv->rtllib->fsync_state = Default_Fsync;
2355                         break;
2356                 case Default_Fsync:
2357                 default:
2358                         break;
2359                 }
2360
2361                 if (priv->framesyncMonitor) {
2362                         if (priv->rtllib->state == RTLLIB_LINKED) {
2363                                 if (priv->undecorated_smoothed_pwdb <=
2364                                     RegC38_TH) {
2365                                         if (reg_c38_State !=
2366                                             RegC38_NonFsync_Other_AP) {
2367                                                 rtl92e_writeb(dev,
2368                                                               rOFDM0_RxDetector3,
2369                                                               0x90);
2370
2371                                                 reg_c38_State =
2372                                                      RegC38_NonFsync_Other_AP;
2373                                         }
2374                                 } else if (priv->undecorated_smoothed_pwdb >=
2375                                            (RegC38_TH+5)) {
2376                                         if (reg_c38_State) {
2377                                                 rtl92e_writeb(dev,
2378                                                         rOFDM0_RxDetector3,
2379                                                         priv->framesync);
2380                                                 reg_c38_State = RegC38_Default;
2381                                         }
2382                                 }
2383                         } else {
2384                                 if (reg_c38_State) {
2385                                         rtl92e_writeb(dev, rOFDM0_RxDetector3,
2386                                                       priv->framesync);
2387                                         reg_c38_State = RegC38_Default;
2388                                 }
2389                         }
2390                 }
2391         }
2392         if (priv->framesyncMonitor) {
2393                 if (priv->reset_count != reset_cnt) {
2394                         rtl92e_writeb(dev, rOFDM0_RxDetector3,
2395                                        priv->framesync);
2396                         reg_c38_State = RegC38_Default;
2397                         reset_cnt = priv->reset_count;
2398                 }
2399         } else {
2400                 if (reg_c38_State) {
2401                         rtl92e_writeb(dev, rOFDM0_RxDetector3,
2402                                        priv->framesync);
2403                         reg_c38_State = RegC38_Default;
2404                 }
2405         }
2406 }
2407
2408 /*---------------------------Define function prototype------------------------*/
2409 static void _rtl92e_dm_init_dynamic_tx_power(struct net_device *dev)
2410 {
2411         struct r8192_priv *priv = rtllib_priv(dev);
2412
2413         priv->rtllib->bdynamic_txpower_enable = true;
2414         priv->bLastDTPFlag_High = false;
2415         priv->bLastDTPFlag_Low = false;
2416         priv->bDynamicTxHighPower = false;
2417         priv->bDynamicTxLowPower = false;
2418 }
2419
2420 static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev)
2421 {
2422         struct r8192_priv *priv = rtllib_priv(dev);
2423         unsigned int txhipower_threshhold = 0;
2424         unsigned int txlowpower_threshold = 0;
2425
2426         if (priv->rtllib->bdynamic_txpower_enable != true) {
2427                 priv->bDynamicTxHighPower = false;
2428                 priv->bDynamicTxLowPower = false;
2429                 return;
2430         }
2431         if ((priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_ATHEROS) &&
2432             (priv->rtllib->mode == IEEE_G)) {
2433                 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
2434                 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
2435         } else {
2436                 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
2437                 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
2438         }
2439
2440         RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n",
2441                  priv->undecorated_smoothed_pwdb);
2442
2443         if (priv->rtllib->state == RTLLIB_LINKED) {
2444                 if (priv->undecorated_smoothed_pwdb >= txhipower_threshhold) {
2445                         priv->bDynamicTxHighPower = true;
2446                         priv->bDynamicTxLowPower = false;
2447                 } else {
2448                         if (priv->undecorated_smoothed_pwdb <
2449                             txlowpower_threshold && priv->bDynamicTxHighPower)
2450                                 priv->bDynamicTxHighPower = false;
2451                         if (priv->undecorated_smoothed_pwdb < 35)
2452                                 priv->bDynamicTxLowPower = true;
2453                         else if (priv->undecorated_smoothed_pwdb >= 40)
2454                                 priv->bDynamicTxLowPower = false;
2455                 }
2456         } else {
2457                 priv->bDynamicTxHighPower = false;
2458                 priv->bDynamicTxLowPower = false;
2459         }
2460
2461         if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) ||
2462             (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) {
2463                 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190()  channel = %d\n",
2464                          priv->rtllib->current_network.channel);
2465
2466                 rtl92e_set_tx_power(dev, priv->rtllib->current_network.channel);
2467         }
2468         priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
2469         priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
2470
2471 }
2472
2473 static void _rtl92e_dm_check_txrateandretrycount(struct net_device *dev)
2474 {
2475         struct r8192_priv *priv = rtllib_priv(dev);
2476         struct rtllib_device *ieee = priv->rtllib;
2477
2478         ieee->softmac_stats.CurrentShowTxate = rtl92e_readb(dev,
2479                                                  Current_Tx_Rate_Reg);
2480
2481         ieee->softmac_stats.last_packet_rate = rtl92e_readb(dev,
2482                                                  Initial_Tx_Rate_Reg);
2483
2484         ieee->softmac_stats.txretrycount = rtl92e_readl(dev,
2485                                                  Tx_Retry_Count_Reg);
2486 }
2487
2488 static void _rtl92e_dm_send_rssi_to_fw(struct net_device *dev)
2489 {
2490         struct r8192_priv *priv = rtllib_priv(dev);
2491
2492         rtl92e_writeb(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
2493 }