drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * Based on the r8180 driver, which is:
   5  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * The full GNU General Public License is included in this distribution in the
  16  * file called LICENSE.
  17  *
  18  * Contact Information:
  19  * wlanfae <wlanfae@realtek.com>
  20 ******************************************************************************/
  21 #include "rtl_core.h"
  22 #include "r8192E_phy.h"
  23 #include "r8192E_phyreg.h"
  24 #include "r8190P_rtl8256.h"
  25 #include "r8192E_cmdpkt.h"
  26 #include "rtl_dm.h"
  27 #include "rtl_wx.h"
  28
  29 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
  30                              EDCAPARA_VO};
  31
  32 void rtl92e_start_beacon(struct net_device *dev)
  33 {
  34         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
  35         struct rtllib_network *net = &priv->rtllib->current_network;
  36         u16 BcnTimeCfg = 0;
  37         u16 BcnCW = 6;
  38         u16 BcnIFS = 0xf;
  39
  40         rtl92e_irq_disable(dev);
  41
  42         rtl92e_writew(dev, ATIMWND, 2);
  43
  44         rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
  45         rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
  46         rtl92e_writew(dev, BCN_DMATIME, 256);
  47
  48         rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
  49
  50         BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
  51         BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
  52         rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
  53         rtl92e_irq_enable(dev);
  54 }
  55
  56 static void _rtl92e_update_msr(struct net_device *dev)
  57 {
  58         struct r8192_priv *priv = rtllib_priv(dev);
  59         u8 msr;
  60         enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
  61
  62         msr  = rtl92e_readb(dev, MSR);
  63         msr &= ~MSR_LINK_MASK;
  64
  65         switch (priv->rtllib->iw_mode) {
  66         case IW_MODE_INFRA:
  67                 if (priv->rtllib->state == RTLLIB_LINKED)
  68                         msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
  69                 else
  70                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  71                 LedAction = LED_CTL_LINK;
  72                 break;
  73         case IW_MODE_ADHOC:
  74                 if (priv->rtllib->state == RTLLIB_LINKED)
  75                         msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
  76                 else
  77                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  78                 break;
  79         case IW_MODE_MASTER:
  80                 if (priv->rtllib->state == RTLLIB_LINKED)
  81                         msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
  82                 else
  83                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  84                 break;
  85         default:
  86                 break;
  87         }
  88
  89         rtl92e_writeb(dev, MSR, msr);
  90         if (priv->rtllib->LedControlHandler)
  91                 priv->rtllib->LedControlHandler(dev, LedAction);
  92 }
  93
  94 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
  95 {
  96         struct r8192_priv *priv = rtllib_priv(dev);
  97
  98         switch (variable) {
  99         case HW_VAR_BSSID:
 100                 /* BSSIDR 2 byte alignment */
 101                 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
 102                 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
 103                 break;
 104
 105         case HW_VAR_MEDIA_STATUS:
 106         {
 107                 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
 108                 u8 btMsr = rtl92e_readb(dev, MSR);
 109
 110                 btMsr &= 0xfc;
 111
 112                 switch (OpMode) {
 113                 case RT_OP_MODE_INFRASTRUCTURE:
 114                         btMsr |= MSR_INFRA;
 115                         break;
 116
 117                 case RT_OP_MODE_IBSS:
 118                         btMsr |= MSR_ADHOC;
 119                         break;
 120
 121                 case RT_OP_MODE_AP:
 122                         btMsr |= MSR_AP;
 123                         break;
 124
 125                 default:
 126                         btMsr |= MSR_NOLINK;
 127                         break;
 128                 }
 129
 130                 rtl92e_writeb(dev, MSR, btMsr);
 131
 132         }
 133         break;
 134
 135         case HW_VAR_CECHK_BSSID:
 136         {
 137                 u32     RegRCR, Type;
 138
 139                 Type = ((u8 *)(val))[0];
 140                 RegRCR = rtl92e_readl(dev, RCR);
 141                 priv->ReceiveConfig = RegRCR;
 142
 143                 if (Type == true)
 144                         RegRCR |= (RCR_CBSSID);
 145                 else if (Type == false)
 146                         RegRCR &= (~RCR_CBSSID);
 147
 148                 rtl92e_writel(dev, RCR, RegRCR);
 149                 priv->ReceiveConfig = RegRCR;
 150
 151         }
 152         break;
 153
 154         case HW_VAR_SLOT_TIME:
 155
 156                 priv->slot_time = val[0];
 157                 rtl92e_writeb(dev, SLOT_TIME, val[0]);
 158
 159                 break;
 160
 161         case HW_VAR_ACK_PREAMBLE:
 162         {
 163                 u32 regTmp;
 164
 165                 priv->short_preamble = (bool)(*(u8 *)val);
 166                 regTmp = priv->basic_rate;
 167                 if (priv->short_preamble)
 168                         regTmp |= BRSR_AckShortPmb;
 169                 rtl92e_writel(dev, RRSR, regTmp);
 170                 break;
 171         }
 172
 173         case HW_VAR_CPU_RST:
 174                 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
 175                 break;
 176
 177         case HW_VAR_AC_PARAM:
 178         {
 179                 u8      pAcParam = *((u8 *)val);
 180                 u32     eACI = pAcParam;
 181                 u8              u1bAIFS;
 182                 u32             u4bAcParam;
 183                 u8 mode = priv->rtllib->mode;
 184                 struct rtllib_qos_parameters *qop =
 185                          &priv->rtllib->current_network.qos_data.parameters;
 186
 187                 u1bAIFS = qop->aifs[pAcParam] *
 188                           ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
 189
 190                 rtl92e_dm_init_edca_turbo(dev);
 191
 192                 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
 193                               AC_PARAM_TXOP_LIMIT_OFFSET) |
 194                                 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
 195                                  AC_PARAM_ECW_MAX_OFFSET) |
 196                                 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
 197                                  AC_PARAM_ECW_MIN_OFFSET) |
 198                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
 199
 200                 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
 201                          __func__, eACI, u4bAcParam);
 202                 switch (eACI) {
 203                 case AC1_BK:
 204                         rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
 205                         break;
 206
 207                 case AC0_BE:
 208                         rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
 209                         break;
 210
 211                 case AC2_VI:
 212                         rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
 213                         break;
 214
 215                 case AC3_VO:
 216                         rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
 217                         break;
 218
 219                 default:
 220                         netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
 221                                     eACI);
 222                         break;
 223                 }
 224                 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
 225                                               (u8 *)(&pAcParam));
 226                 break;
 227         }
 228
 229         case HW_VAR_ACM_CTRL:
 230         {
 231                 struct rtllib_qos_parameters *qos_parameters =
 232                          &priv->rtllib->current_network.qos_data.parameters;
 233                 u8 pAcParam = *((u8 *)val);
 234                 u32 eACI = pAcParam;
 235                 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
 236                                               (qos_parameters->aifs[0]);
 237                 u8 acm = pAciAifsn->f.acm;
 238                 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
 239
 240                 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
 241                          __func__, eACI);
 242                 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
 243
 244                 if (acm) {
 245                         switch (eACI) {
 246                         case AC0_BE:
 247                                 AcmCtrl |= AcmHw_BeqEn;
 248                                 break;
 249
 250                         case AC2_VI:
 251                                 AcmCtrl |= AcmHw_ViqEn;
 252                                 break;
 253
 254                         case AC3_VO:
 255                                 AcmCtrl |= AcmHw_VoqEn;
 256                                 break;
 257
 258                         default:
 259                                 RT_TRACE(COMP_QOS,
 260                                          "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
 261                                          eACI);
 262                                 break;
 263                         }
 264                 } else {
 265                         switch (eACI) {
 266                         case AC0_BE:
 267                                 AcmCtrl &= (~AcmHw_BeqEn);
 268                                 break;
 269
 270                         case AC2_VI:
 271                                 AcmCtrl &= (~AcmHw_ViqEn);
 272                                 break;
 273
 274                         case AC3_VO:
 275                                 AcmCtrl &= (~AcmHw_BeqEn);
 276                                 break;
 277
 278                         default:
 279                                 break;
 280                         }
 281                 }
 282
 283                 RT_TRACE(COMP_QOS,
 284                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 285                          AcmCtrl);
 286                 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
 287                 break;
 288         }
 289
 290         case HW_VAR_SIFS:
 291                 rtl92e_writeb(dev, SIFS, val[0]);
 292                 rtl92e_writeb(dev, SIFS+1, val[0]);
 293                 break;
 294
 295         case HW_VAR_RF_TIMING:
 296         {
 297                 u8 Rf_Timing = *((u8 *)val);
 298
 299                 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
 300                 break;
 301         }
 302
 303         default:
 304                 break;
 305         }
 306
 307 }
 308
 309 static void _rtl92e_read_eeprom_info(struct net_device *dev)
 310 {
 311         struct r8192_priv *priv = rtllib_priv(dev);
 312         const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
 313         u8 tempval;
 314         u8 ICVer8192, ICVer8256;
 315         u16 i, usValue, IC_Version;
 316         u16 EEPROMId;
 317
 318         RT_TRACE(COMP_INIT, "====> _rtl92e_read_eeprom_info\n");
 319
 320         EEPROMId = rtl92e_eeprom_read(dev, 0);
 321         if (EEPROMId != RTL8190_EEPROM_ID) {
 322                 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
 323                            EEPROMId);
 324                 priv->AutoloadFailFlag = true;
 325         } else {
 326                 priv->AutoloadFailFlag = false;
 327         }
 328
 329         if (!priv->AutoloadFailFlag) {
 330                 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
 331                 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
 332
 333                 usValue = rtl92e_eeprom_read(dev,
 334                                              (u16)(EEPROM_Customer_ID>>1)) >> 8;
 335                 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
 336                 usValue = rtl92e_eeprom_read(dev,
 337                                              EEPROM_ICVersion_ChannelPlan>>1);
 338                 priv->eeprom_ChannelPlan = usValue&0xff;
 339                 IC_Version = (usValue & 0xff00)>>8;
 340
 341                 ICVer8192 = (IC_Version&0xf);
 342                 ICVer8256 = (IC_Version & 0xf0)>>4;
 343                 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
 344                 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
 345                 if (ICVer8192 == 0x2) {
 346                         if (ICVer8256 == 0x5)
 347                                 priv->card_8192_version = VERSION_8190_BE;
 348                 }
 349                 switch (priv->card_8192_version) {
 350                 case VERSION_8190_BD:
 351                 case VERSION_8190_BE:
 352                         break;
 353                 default:
 354                         priv->card_8192_version = VERSION_8190_BD;
 355                         break;
 356                 }
 357                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
 358                           priv->card_8192_version);
 359         } else {
 360                 priv->card_8192_version = VERSION_8190_BD;
 361                 priv->eeprom_vid = 0;
 362                 priv->eeprom_did = 0;
 363                 priv->eeprom_CustomerID = 0;
 364                 priv->eeprom_ChannelPlan = 0;
 365                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
 366         }
 367
 368         RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
 369         RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
 370         RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
 371                  priv->eeprom_CustomerID);
 372
 373         if (!priv->AutoloadFailFlag) {
 374                 for (i = 0; i < 6; i += 2) {
 375                         usValue = rtl92e_eeprom_read(dev,
 376                                  (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
 377                         *(u16 *)(&dev->dev_addr[i]) = usValue;
 378                 }
 379         } else {
 380                 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
 381         }
 382
 383         RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
 384                  dev->dev_addr);
 385
 386         if (priv->card_8192_version > VERSION_8190_BD)
 387                 priv->bTXPowerDataReadFromEEPORM = true;
 388         else
 389                 priv->bTXPowerDataReadFromEEPORM = false;
 390
 391         priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
 392
 393         if (priv->card_8192_version > VERSION_8190_BD) {
 394                 if (!priv->AutoloadFailFlag) {
 395                         tempval = (rtl92e_eeprom_read(dev,
 396                                                       (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
 397                         priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
 398
 399                         if (tempval&0x80)
 400                                 priv->rf_type = RF_1T2R;
 401                         else
 402                                 priv->rf_type = RF_2T4R;
 403                 } else {
 404                         priv->EEPROMLegacyHTTxPowerDiff = 0x04;
 405                 }
 406                 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
 407                         priv->EEPROMLegacyHTTxPowerDiff);
 408
 409                 if (!priv->AutoloadFailFlag)
 410                         priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev,
 411                                                    (EEPROM_ThermalMeter>>1))) &
 412                                                    0xff00)>>8);
 413                 else
 414                         priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
 415                 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
 416                          priv->EEPROMThermalMeter);
 417                 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
 418
 419                 if (priv->epromtype == EEPROM_93C46) {
 420                         if (!priv->AutoloadFailFlag) {
 421                                 usValue = rtl92e_eeprom_read(dev,
 422                                           EEPROM_TxPwDiff_CrystalCap >> 1);
 423                                 priv->EEPROMAntPwDiff = (usValue&0x0fff);
 424                                 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
 425                                                          >> 12);
 426                         } else {
 427                                 priv->EEPROMAntPwDiff =
 428                                          EEPROM_Default_AntTxPowerDiff;
 429                                 priv->EEPROMCrystalCap =
 430                                          EEPROM_Default_TxPwDiff_CrystalCap;
 431                         }
 432                         RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
 433                                  priv->EEPROMAntPwDiff);
 434                         RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
 435                                  priv->EEPROMCrystalCap);
 436
 437                         for (i = 0; i < 14; i += 2) {
 438                                 if (!priv->AutoloadFailFlag)
 439                                         usValue = rtl92e_eeprom_read(dev,
 440                                                   (u16)((EEPROM_TxPwIndex_CCK +
 441                                                   i) >> 1));
 442                                 else
 443                                         usValue = EEPROM_Default_TxPower;
 444                                 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
 445                                                                  usValue;
 446                                 RT_TRACE(COMP_INIT,
 447                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 448                                          i, priv->EEPROMTxPowerLevelCCK[i]);
 449                                 RT_TRACE(COMP_INIT,
 450                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 451                                          i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
 452                         }
 453                         for (i = 0; i < 14; i += 2) {
 454                                 if (!priv->AutoloadFailFlag)
 455                                         usValue = rtl92e_eeprom_read(dev,
 456                                                 (u16)((EEPROM_TxPwIndex_OFDM_24G
 457                                                 + i) >> 1));
 458                                 else
 459                                         usValue = EEPROM_Default_TxPower;
 460                                 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
 461                                                          = usValue;
 462                                 RT_TRACE(COMP_INIT,
 463                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 464                                          i, priv->EEPROMTxPowerLevelOFDM24G[i]);
 465                                 RT_TRACE(COMP_INIT,
 466                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 467                                          i + 1,
 468                                          priv->EEPROMTxPowerLevelOFDM24G[i+1]);
 469                         }
 470                 }
 471                 if (priv->epromtype == EEPROM_93C46) {
 472                         for (i = 0; i < 14; i++) {
 473                                 priv->TxPowerLevelCCK[i] =
 474                                          priv->EEPROMTxPowerLevelCCK[i];
 475                                 priv->TxPowerLevelOFDM24G[i] =
 476                                          priv->EEPROMTxPowerLevelOFDM24G[i];
 477                         }
 478                         priv->LegacyHTTxPowerDiff =
 479                                          priv->EEPROMLegacyHTTxPowerDiff;
 480                         priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
 481                                                     0xf);
 482                         priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
 483                                                         0xf0) >> 4;
 484                         priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
 485                                                         0xf00) >> 8;
 486                         priv->CrystalCap = priv->EEPROMCrystalCap;
 487                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 488                                                  0xf);
 489                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 490                                                      0xf0) >> 4;
 491                 } else if (priv->epromtype == EEPROM_93C56) {
 492
 493                         for (i = 0; i < 3; i++) {
 494                                 priv->TxPowerLevelCCK_A[i] =
 495                                          priv->EEPROMRfACCKChnl1TxPwLevel[0];
 496                                 priv->TxPowerLevelOFDM24G_A[i] =
 497                                          priv->EEPROMRfAOfdmChnlTxPwLevel[0];
 498                                 priv->TxPowerLevelCCK_C[i] =
 499                                          priv->EEPROMRfCCCKChnl1TxPwLevel[0];
 500                                 priv->TxPowerLevelOFDM24G_C[i] =
 501                                          priv->EEPROMRfCOfdmChnlTxPwLevel[0];
 502                         }
 503                         for (i = 3; i < 9; i++) {
 504                                 priv->TxPowerLevelCCK_A[i]  =
 505                                          priv->EEPROMRfACCKChnl1TxPwLevel[1];
 506                                 priv->TxPowerLevelOFDM24G_A[i] =
 507                                          priv->EEPROMRfAOfdmChnlTxPwLevel[1];
 508                                 priv->TxPowerLevelCCK_C[i] =
 509                                          priv->EEPROMRfCCCKChnl1TxPwLevel[1];
 510                                 priv->TxPowerLevelOFDM24G_C[i] =
 511                                          priv->EEPROMRfCOfdmChnlTxPwLevel[1];
 512                         }
 513                         for (i = 9; i < 14; i++) {
 514                                 priv->TxPowerLevelCCK_A[i]  =
 515                                          priv->EEPROMRfACCKChnl1TxPwLevel[2];
 516                                 priv->TxPowerLevelOFDM24G_A[i] =
 517                                          priv->EEPROMRfAOfdmChnlTxPwLevel[2];
 518                                 priv->TxPowerLevelCCK_C[i] =
 519                                          priv->EEPROMRfCCCKChnl1TxPwLevel[2];
 520                                 priv->TxPowerLevelOFDM24G_C[i] =
 521                                          priv->EEPROMRfCOfdmChnlTxPwLevel[2];
 522                         }
 523                         for (i = 0; i < 14; i++)
 524                                 RT_TRACE(COMP_INIT,
 525                                          "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
 526                                          i, priv->TxPowerLevelCCK_A[i]);
 527                         for (i = 0; i < 14; i++)
 528                                 RT_TRACE(COMP_INIT,
 529                                          "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
 530                                          i, priv->TxPowerLevelOFDM24G_A[i]);
 531                         for (i = 0; i < 14; i++)
 532                                 RT_TRACE(COMP_INIT,
 533                                          "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
 534                                          i, priv->TxPowerLevelCCK_C[i]);
 535                         for (i = 0; i < 14; i++)
 536                                 RT_TRACE(COMP_INIT,
 537                                          "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
 538                                          i, priv->TxPowerLevelOFDM24G_C[i]);
 539                         priv->LegacyHTTxPowerDiff =
 540                                  priv->EEPROMLegacyHTTxPowerDiff;
 541                         priv->AntennaTxPwDiff[0] = 0;
 542                         priv->AntennaTxPwDiff[1] = 0;
 543                         priv->AntennaTxPwDiff[2] = 0;
 544                         priv->CrystalCap = priv->EEPROMCrystalCap;
 545                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 546                                                  0xf);
 547                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 548                                                      0xf0) >> 4;
 549                 }
 550         }
 551
 552         if (priv->rf_type == RF_1T2R) {
 553                 /* no matter what checkpatch says, the braces are needed */
 554                 RT_TRACE(COMP_INIT, "\n1T2R config\n");
 555         } else if (priv->rf_type == RF_2T4R) {
 556                 RT_TRACE(COMP_INIT, "\n2T4R config\n");
 557         }
 558
 559         rtl92e_init_adaptive_rate(dev);
 560
 561         priv->rf_chip = RF_8256;
 562
 563         if (priv->RegChannelPlan == 0xf)
 564                 priv->ChannelPlan = priv->eeprom_ChannelPlan;
 565         else
 566                 priv->ChannelPlan = priv->RegChannelPlan;
 567
 568         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 569                 priv->CustomerID =  RT_CID_DLINK;
 570
 571         switch (priv->eeprom_CustomerID) {
 572         case EEPROM_CID_DEFAULT:
 573                 priv->CustomerID = RT_CID_DEFAULT;
 574                 break;
 575         case EEPROM_CID_CAMEO:
 576                 priv->CustomerID = RT_CID_819x_CAMEO;
 577                 break;
 578         case  EEPROM_CID_RUNTOP:
 579                 priv->CustomerID = RT_CID_819x_RUNTOP;
 580                 break;
 581         case EEPROM_CID_NetCore:
 582                 priv->CustomerID = RT_CID_819x_Netcore;
 583                 break;
 584         case EEPROM_CID_TOSHIBA:
 585                 priv->CustomerID = RT_CID_TOSHIBA;
 586                 if (priv->eeprom_ChannelPlan&0x80)
 587                         priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
 588                 else
 589                         priv->ChannelPlan = 0x0;
 590                 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
 591                         priv->ChannelPlan);
 592                 break;
 593         case EEPROM_CID_Nettronix:
 594                 priv->ScanDelay = 100;
 595                 priv->CustomerID = RT_CID_Nettronix;
 596                 break;
 597         case EEPROM_CID_Pronet:
 598                 priv->CustomerID = RT_CID_PRONET;
 599                 break;
 600         case EEPROM_CID_DLINK:
 601                 priv->CustomerID = RT_CID_DLINK;
 602                 break;
 603
 604         case EEPROM_CID_WHQL:
 605                 break;
 606         default:
 607                 break;
 608         }
 609
 610         if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
 611                 priv->ChannelPlan = 0;
 612         priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
 613
 614         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 615                 priv->rtllib->bSupportRemoteWakeUp = true;
 616         else
 617                 priv->rtllib->bSupportRemoteWakeUp = false;
 618
 619         RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
 620         RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
 621         RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
 622 }
 623
 624 void rtl92e_get_eeprom_size(struct net_device *dev)
 625 {
 626         u16 curCR;
 627         struct r8192_priv *priv = rtllib_priv(dev);
 628
 629         RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
 630         curCR = rtl92e_readw(dev, EPROM_CMD);
 631         RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
 632                  curCR);
 633         priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
 634                           EEPROM_93C46;
 635         RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
 636                  priv->epromtype);
 637         _rtl92e_read_eeprom_info(dev);
 638 }
 639
 640 static void _rtl92e_hwconfig(struct net_device *dev)
 641 {
 642         u32 regRATR = 0, regRRSR = 0;
 643         u8 regBwOpMode = 0, regTmp = 0;
 644         struct r8192_priv *priv = rtllib_priv(dev);
 645
 646         switch (priv->rtllib->mode) {
 647         case WIRELESS_MODE_B:
 648                 regBwOpMode = BW_OPMODE_20MHZ;
 649                 regRATR = RATE_ALL_CCK;
 650                 regRRSR = RATE_ALL_CCK;
 651                 break;
 652         case WIRELESS_MODE_A:
 653                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 654                 regRATR = RATE_ALL_OFDM_AG;
 655                 regRRSR = RATE_ALL_OFDM_AG;
 656                 break;
 657         case WIRELESS_MODE_G:
 658                 regBwOpMode = BW_OPMODE_20MHZ;
 659                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 660                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 661                 break;
 662         case WIRELESS_MODE_AUTO:
 663         case WIRELESS_MODE_N_24G:
 664                 regBwOpMode = BW_OPMODE_20MHZ;
 665                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 666                                   RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 667                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 668                 break;
 669         case WIRELESS_MODE_N_5G:
 670                 regBwOpMode = BW_OPMODE_5G;
 671                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 672                           RATE_ALL_OFDM_2SS;
 673                 regRRSR = RATE_ALL_OFDM_AG;
 674                 break;
 675         default:
 676                 regBwOpMode = BW_OPMODE_20MHZ;
 677                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 678                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 679                 break;
 680         }
 681
 682         rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
 683         {
 684                 u32 ratr_value = 0;
 685
 686                 ratr_value = regRATR;
 687                 if (priv->rf_type == RF_1T2R)
 688                         ratr_value &= ~(RATE_ALL_OFDM_2SS);
 689                 rtl92e_writel(dev, RATR0, ratr_value);
 690                 rtl92e_writeb(dev, UFWP, 1);
 691         }
 692         regTmp = rtl92e_readb(dev, 0x313);
 693         regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
 694         rtl92e_writel(dev, RRSR, regRRSR);
 695
 696         rtl92e_writew(dev, RETRY_LIMIT,
 697                       priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
 698                       priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
 699 }
 700
 701 bool rtl92e_start_adapter(struct net_device *dev)
 702 {
 703         struct r8192_priv *priv = rtllib_priv(dev);
 704         u32 ulRegRead;
 705         bool rtStatus = true;
 706         u8 tmpvalue;
 707         u8 ICVersion, SwitchingRegulatorOutput;
 708         bool bfirmwareok = true;
 709         u32 tmpRegA, tmpRegC, TempCCk;
 710         int i = 0;
 711         u32 retry_times = 0;
 712
 713         RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
 714         priv->being_init_adapter = true;
 715
 716 start:
 717         rtl92e_reset_desc_ring(dev);
 718         priv->Rf_Mode = RF_OP_By_SW_3wire;
 719         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 720                 rtl92e_writeb(dev, ANAPAR, 0x37);
 721                 mdelay(500);
 722         }
 723         priv->pFirmware->status = FW_STATUS_0_INIT;
 724
 725         if (priv->RegRfOff)
 726                 priv->rtllib->eRFPowerState = eRfOff;
 727
 728         ulRegRead = rtl92e_readl(dev, CPU_GEN);
 729         if (priv->pFirmware->status == FW_STATUS_0_INIT)
 730                 ulRegRead |= CPU_GEN_SYSTEM_RESET;
 731         else if (priv->pFirmware->status == FW_STATUS_5_READY)
 732                 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
 733         else
 734                 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
 735                            __func__, priv->pFirmware->status);
 736
 737         rtl92e_writel(dev, CPU_GEN, ulRegRead);
 738
 739         ICVersion = rtl92e_readb(dev, IC_VERRSION);
 740         if (ICVersion >= 0x4) {
 741                 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
 742                 if (SwitchingRegulatorOutput  != 0xb8) {
 743                         rtl92e_writeb(dev, SWREGULATOR, 0xa8);
 744                         mdelay(1);
 745                         rtl92e_writeb(dev, SWREGULATOR, 0xb8);
 746                 }
 747         }
 748         RT_TRACE(COMP_INIT, "BB Config Start!\n");
 749         rtStatus = rtl92e_config_bb(dev);
 750         if (!rtStatus) {
 751                 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
 752                 return rtStatus;
 753         }
 754         RT_TRACE(COMP_INIT, "BB Config Finished!\n");
 755
 756         priv->LoopbackMode = RTL819X_NO_LOOPBACK;
 757         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 758                 ulRegRead = rtl92e_readl(dev, CPU_GEN);
 759                 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
 760                         ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
 761                                      CPU_GEN_NO_LOOPBACK_SET);
 762                 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
 763                         ulRegRead |= CPU_CCK_LOOPBACK;
 764                 else
 765                         netdev_err(dev, "%s: Invalid loopback mode setting.\n",
 766                                    __func__);
 767
 768                 rtl92e_writel(dev, CPU_GEN, ulRegRead);
 769
 770                 udelay(500);
 771         }
 772         _rtl92e_hwconfig(dev);
 773         rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
 774
 775         rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
 776                                   (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
 777         rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
 778         rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
 779         rtl92e_writel(dev, RCR, priv->ReceiveConfig);
 780
 781         rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
 782                       RSVD_FW_QUEUE_PAGE_BK_SHIFT |
 783                       NUM_OF_PAGE_IN_FW_QUEUE_BE <<
 784                       RSVD_FW_QUEUE_PAGE_BE_SHIFT |
 785                       NUM_OF_PAGE_IN_FW_QUEUE_VI <<
 786                       RSVD_FW_QUEUE_PAGE_VI_SHIFT |
 787                       NUM_OF_PAGE_IN_FW_QUEUE_VO <<
 788                       RSVD_FW_QUEUE_PAGE_VO_SHIFT);
 789         rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
 790                       RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
 791         rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
 792                       NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
 793                       RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
 794                       NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
 795                       RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
 796
 797         rtl92e_tx_enable(dev);
 798         rtl92e_rx_enable(dev);
 799         ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR))  |
 800                      RATE_ALL_OFDM_AG | RATE_ALL_CCK;
 801         rtl92e_writel(dev, RRSR, ulRegRead);
 802         rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
 803
 804         rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
 805
 806         if (priv->ResetProgress == RESET_TYPE_NORESET)
 807                 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
 808         rtl92e_cam_reset(dev);
 809         {
 810                 u8 SECR_value = 0x0;
 811
 812                 SECR_value |= SCR_TxEncEnable;
 813                 SECR_value |= SCR_RxDecEnable;
 814                 SECR_value |= SCR_NoSKMC;
 815                 rtl92e_writeb(dev, SECR, SECR_value);
 816         }
 817         rtl92e_writew(dev, ATIMWND, 2);
 818         rtl92e_writew(dev, BCN_INTERVAL, 100);
 819         {
 820                 int i;
 821
 822                 for (i = 0; i < QOS_QUEUE_NUM; i++)
 823                         rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
 824         }
 825         rtl92e_writeb(dev, 0xbe, 0xc0);
 826
 827         rtl92e_config_mac(dev);
 828
 829         if (priv->card_8192_version > (u8) VERSION_8190_BD) {
 830                 rtl92e_get_tx_power(dev);
 831                 rtl92e_set_tx_power(dev, priv->chan);
 832         }
 833
 834         tmpvalue = rtl92e_readb(dev, IC_VERRSION);
 835         priv->IC_Cut = tmpvalue;
 836         RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
 837         if (priv->IC_Cut >= IC_VersionCut_D) {
 838                 if (priv->IC_Cut == IC_VersionCut_D) {
 839                         /* no matter what checkpatch says, braces are needed */
 840                         RT_TRACE(COMP_INIT, "D-cut\n");
 841                 } else if (priv->IC_Cut == IC_VersionCut_E) {
 842                         RT_TRACE(COMP_INIT, "E-cut\n");
 843                 }
 844         } else {
 845                 RT_TRACE(COMP_INIT, "Before C-cut\n");
 846         }
 847
 848         RT_TRACE(COMP_INIT, "Load Firmware!\n");
 849         bfirmwareok = rtl92e_init_fw(dev);
 850         if (!bfirmwareok) {
 851                 if (retry_times < 10) {
 852                         retry_times++;
 853                         goto start;
 854                 } else {
 855                         rtStatus = false;
 856                         goto end;
 857                 }
 858         }
 859         RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
 860         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 861                 RT_TRACE(COMP_INIT, "RF Config Started!\n");
 862                 rtStatus = rtl92e_config_phy(dev);
 863                 if (!rtStatus) {
 864                         netdev_info(dev, "RF Config failed\n");
 865                         return rtStatus;
 866                 }
 867                 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
 868         }
 869
 870         rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
 871         rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
 872
 873         rtl92e_writeb(dev, 0x87, 0x0);
 874
 875         if (priv->RegRfOff) {
 876                 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
 877                           "%s(): Turn off RF for RegRfOff ----------\n",
 878                           __func__);
 879                 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW);
 880         } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
 881                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 882                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 883                          __func__, priv->rtllib->RfOffReason);
 884                 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
 885         } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
 886                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 887                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 888                          __func__, priv->rtllib->RfOffReason);
 889                 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
 890         } else {
 891                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
 892                           __func__);
 893                 priv->rtllib->eRFPowerState = eRfOn;
 894                 priv->rtllib->RfOffReason = 0;
 895         }
 896
 897         if (priv->rtllib->FwRWRF)
 898                 priv->Rf_Mode = RF_OP_By_FW;
 899         else
 900                 priv->Rf_Mode = RF_OP_By_SW_3wire;
 901
 902         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 903                 rtl92e_dm_init_txpower_tracking(dev);
 904
 905                 if (priv->IC_Cut >= IC_VersionCut_D) {
 906                         tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
 907                                                     bMaskDWord);
 908                         tmpRegC = rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance,
 909                                                     bMaskDWord);
 910                         for (i = 0; i < TxBBGainTableLength; i++) {
 911                                 if (tmpRegA == dm_tx_bb_gain[i]) {
 912                                         priv->rfa_txpowertrackingindex = (u8)i;
 913                                         priv->rfa_txpowertrackingindex_real =
 914                                                  (u8)i;
 915                                         priv->rfa_txpowertracking_default =
 916                                                  priv->rfa_txpowertrackingindex;
 917                                         break;
 918                                 }
 919                         }
 920
 921                         TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
 922                                                     bMaskByte2);
 923
 924                         for (i = 0; i < CCKTxBBGainTableLength; i++) {
 925                                 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
 926                                         priv->CCKPresentAttentuation_20Mdefault = (u8)i;
 927                                         break;
 928                                 }
 929                         }
 930                         priv->CCKPresentAttentuation_40Mdefault = 0;
 931                         priv->CCKPresentAttentuation_difference = 0;
 932                         priv->CCKPresentAttentuation =
 933                                   priv->CCKPresentAttentuation_20Mdefault;
 934                         RT_TRACE(COMP_POWER_TRACKING,
 935                                  "priv->rfa_txpowertrackingindex_initial = %d\n",
 936                                  priv->rfa_txpowertrackingindex);
 937                         RT_TRACE(COMP_POWER_TRACKING,
 938                                  "priv->rfa_txpowertrackingindex_real__initial = %d\n",
 939                                  priv->rfa_txpowertrackingindex_real);
 940                         RT_TRACE(COMP_POWER_TRACKING,
 941                                  "priv->CCKPresentAttentuation_difference_initial = %d\n",
 942                                   priv->CCKPresentAttentuation_difference);
 943                         RT_TRACE(COMP_POWER_TRACKING,
 944                                  "priv->CCKPresentAttentuation_initial = %d\n",
 945                                  priv->CCKPresentAttentuation);
 946                         priv->btxpower_tracking = false;
 947                 }
 948         }
 949         rtl92e_irq_enable(dev);
 950 end:
 951         priv->being_init_adapter = false;
 952         return rtStatus;
 953 }
 954
 955 static void _rtl92e_net_update(struct net_device *dev)
 956 {
 957
 958         struct r8192_priv *priv = rtllib_priv(dev);
 959         struct rtllib_network *net;
 960         u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
 961         u16 rate_config = 0;
 962
 963         net = &priv->rtllib->current_network;
 964         rtl92e_config_rate(dev, &rate_config);
 965         priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
 966          priv->basic_rate = rate_config &= 0x15f;
 967         rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
 968         rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
 969
 970         if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
 971                 rtl92e_writew(dev, ATIMWND, 2);
 972                 rtl92e_writew(dev, BCN_DMATIME, 256);
 973                 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
 974                 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
 975                 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
 976
 977                 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
 978                 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
 979
 980                 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
 981         }
 982 }
 983
 984 void rtl92e_link_change(struct net_device *dev)
 985 {
 986         struct r8192_priv *priv = rtllib_priv(dev);
 987         struct rtllib_device *ieee = priv->rtllib;
 988
 989         if (!priv->up)
 990                 return;
 991
 992         if (ieee->state == RTLLIB_LINKED) {
 993                 _rtl92e_net_update(dev);
 994                 priv->ops->update_ratr_table(dev);
 995                 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
 996                     (ieee->pairwise_key_type == KEY_TYPE_WEP104))
 997                         rtl92e_enable_hw_security_config(dev);
 998         } else {
 999                 rtl92e_writeb(dev, 0x173, 0);
1000         }
1001         _rtl92e_update_msr(dev);
1002
1003         if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1004                 u32 reg = 0;
1005
1006                 reg = rtl92e_readl(dev, RCR);
1007                 if (priv->rtllib->state == RTLLIB_LINKED) {
1008                         if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1009                                 ;
1010                         else
1011                                 priv->ReceiveConfig = reg |= RCR_CBSSID;
1012                 } else
1013                         priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1014
1015                 rtl92e_writel(dev, RCR, reg);
1016         }
1017 }
1018
1019 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1020                              bool WriteIntoReg)
1021 {
1022         struct r8192_priv *priv = rtllib_priv(dev);
1023
1024         if (bAllowAllDA)
1025                 priv->ReceiveConfig |= RCR_AAP;
1026         else
1027                 priv->ReceiveConfig &= ~RCR_AAP;
1028
1029         if (WriteIntoReg)
1030                 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
1031 }
1032
1033 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
1034 {
1035         u8  ret = DESC90_RATE1M;
1036
1037         switch (rate) {
1038         case MGN_1M:
1039                 ret = DESC90_RATE1M;
1040                 break;
1041         case MGN_2M:
1042                 ret = DESC90_RATE2M;
1043                 break;
1044         case MGN_5_5M:
1045                 ret = DESC90_RATE5_5M;
1046                 break;
1047         case MGN_11M:
1048                 ret = DESC90_RATE11M;
1049                 break;
1050         case MGN_6M:
1051                 ret = DESC90_RATE6M;
1052                 break;
1053         case MGN_9M:
1054                 ret = DESC90_RATE9M;
1055                 break;
1056         case MGN_12M:
1057                 ret = DESC90_RATE12M;
1058                 break;
1059         case MGN_18M:
1060                 ret = DESC90_RATE18M;
1061                 break;
1062         case MGN_24M:
1063                 ret = DESC90_RATE24M;
1064                 break;
1065         case MGN_36M:
1066                 ret = DESC90_RATE36M;
1067                 break;
1068         case MGN_48M:
1069                 ret = DESC90_RATE48M;
1070                 break;
1071         case MGN_54M:
1072                 ret = DESC90_RATE54M;
1073                 break;
1074         case MGN_MCS0:
1075                 ret = DESC90_RATEMCS0;
1076                 break;
1077         case MGN_MCS1:
1078                 ret = DESC90_RATEMCS1;
1079                 break;
1080         case MGN_MCS2:
1081                 ret = DESC90_RATEMCS2;
1082                 break;
1083         case MGN_MCS3:
1084                 ret = DESC90_RATEMCS3;
1085                 break;
1086         case MGN_MCS4:
1087                 ret = DESC90_RATEMCS4;
1088                 break;
1089         case MGN_MCS5:
1090                 ret = DESC90_RATEMCS5;
1091                 break;
1092         case MGN_MCS6:
1093                 ret = DESC90_RATEMCS6;
1094                 break;
1095         case MGN_MCS7:
1096                 ret = DESC90_RATEMCS7;
1097                 break;
1098         case MGN_MCS8:
1099                 ret = DESC90_RATEMCS8;
1100                 break;
1101         case MGN_MCS9:
1102                 ret = DESC90_RATEMCS9;
1103                 break;
1104         case MGN_MCS10:
1105                 ret = DESC90_RATEMCS10;
1106                 break;
1107         case MGN_MCS11:
1108                 ret = DESC90_RATEMCS11;
1109                 break;
1110         case MGN_MCS12:
1111                 ret = DESC90_RATEMCS12;
1112                 break;
1113         case MGN_MCS13:
1114                 ret = DESC90_RATEMCS13;
1115                 break;
1116         case MGN_MCS14:
1117                 ret = DESC90_RATEMCS14;
1118                 break;
1119         case MGN_MCS15:
1120                 ret = DESC90_RATEMCS15;
1121                 break;
1122         case (0x80|0x20):
1123                 ret = DESC90_RATEMCS32;
1124                 break;
1125         default:
1126                 break;
1127         }
1128         return ret;
1129 }
1130
1131 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
1132                                        u8 priority)
1133 {
1134         u8 QueueSelect = 0x0;
1135
1136         switch (QueueID) {
1137         case BE_QUEUE:
1138                 QueueSelect = QSLT_BE;
1139                 break;
1140
1141         case BK_QUEUE:
1142                 QueueSelect = QSLT_BK;
1143                 break;
1144
1145         case VO_QUEUE:
1146                 QueueSelect = QSLT_VO;
1147                 break;
1148
1149         case VI_QUEUE:
1150                 QueueSelect = QSLT_VI;
1151                 break;
1152         case MGNT_QUEUE:
1153                 QueueSelect = QSLT_MGNT;
1154                 break;
1155         case BEACON_QUEUE:
1156                 QueueSelect = QSLT_BEACON;
1157                 break;
1158         case TXCMD_QUEUE:
1159                 QueueSelect = QSLT_CMD;
1160                 break;
1161         case HIGH_QUEUE:
1162                 QueueSelect = QSLT_HIGH;
1163                 break;
1164         default:
1165                 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1166                             __func__, QueueID);
1167                 break;
1168         }
1169         return QueueSelect;
1170 }
1171
1172 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1173 {
1174         u8   tmp_Short;
1175
1176         tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1177                         ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1178         if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1179                 tmp_Short = 0;
1180
1181         return tmp_Short;
1182 }
1183
1184 void  rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1185                           struct cb_desc *cb_desc, struct sk_buff *skb)
1186 {
1187         struct r8192_priv *priv = rtllib_priv(dev);
1188         dma_addr_t mapping;
1189         struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1190
1191         pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1192         memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1193         pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1194         pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->data_rate);
1195         pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1196         pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1197                                                   pTxFwInfo->TxRate, cb_desc);
1198
1199         if (cb_desc->bAMPDUEnable) {
1200                 pTxFwInfo->AllowAggregation = 1;
1201                 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1202                 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1203         } else {
1204                 pTxFwInfo->AllowAggregation = 0;
1205                 pTxFwInfo->RxMF = 0;
1206                 pTxFwInfo->RxAMD = 0;
1207         }
1208
1209         pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1210         pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1211         pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1212         pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1213         pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->rts_rate);
1214         pTxFwInfo->RtsBandwidth = 0;
1215         pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1216         pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1217                           (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1218                           (cb_desc->bRTSUseShortGI ? 1 : 0);
1219         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1220                 if (cb_desc->bPacketBW) {
1221                         pTxFwInfo->TxBandwidth = 1;
1222                         pTxFwInfo->TxSubCarrier = 0;
1223                 } else {
1224                         pTxFwInfo->TxBandwidth = 0;
1225                         pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1226                 }
1227         } else {
1228                 pTxFwInfo->TxBandwidth = 0;
1229                 pTxFwInfo->TxSubCarrier = 0;
1230         }
1231
1232         memset((u8 *)pdesc, 0, 12);
1233
1234         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1235                                  PCI_DMA_TODEVICE);
1236         if (pci_dma_mapping_error(priv->pdev, mapping)) {
1237                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1238                 return;
1239         }
1240
1241         pdesc->LINIP = 0;
1242         pdesc->CmdInit = 1;
1243         pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1244         pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1245
1246         pdesc->SecCAMID = 0;
1247         pdesc->RATid = cb_desc->RATRIndex;
1248
1249
1250         pdesc->NoEnc = 1;
1251         pdesc->SecType = 0x0;
1252         if (cb_desc->bHwSec) {
1253                 static u8 tmp;
1254
1255                 if (!tmp) {
1256                         RT_TRACE(COMP_DBG, "==>================hw sec\n");
1257                         tmp = 1;
1258                 }
1259                 switch (priv->rtllib->pairwise_key_type) {
1260                 case KEY_TYPE_WEP40:
1261                 case KEY_TYPE_WEP104:
1262                         pdesc->SecType = 0x1;
1263                         pdesc->NoEnc = 0;
1264                         break;
1265                 case KEY_TYPE_TKIP:
1266                         pdesc->SecType = 0x2;
1267                         pdesc->NoEnc = 0;
1268                         break;
1269                 case KEY_TYPE_CCMP:
1270                         pdesc->SecType = 0x3;
1271                         pdesc->NoEnc = 0;
1272                         break;
1273                 case KEY_TYPE_NA:
1274                         pdesc->SecType = 0x0;
1275                         pdesc->NoEnc = 1;
1276                         break;
1277                 }
1278         }
1279
1280         pdesc->PktId = 0x0;
1281
1282         pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1283                                                           cb_desc->queue_index,
1284                                                           cb_desc->priority);
1285         pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1286
1287         pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1288         pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1289
1290         pdesc->FirstSeg = 1;
1291         pdesc->LastSeg = 1;
1292         pdesc->TxBufferSize = skb->len;
1293
1294         pdesc->TxBuffAddr = mapping;
1295 }
1296
1297 void  rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1298                               struct cb_desc *cb_desc, struct sk_buff *skb)
1299 {
1300         struct r8192_priv *priv = rtllib_priv(dev);
1301         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1302                          PCI_DMA_TODEVICE);
1303
1304         if (pci_dma_mapping_error(priv->pdev, mapping))
1305                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1306         memset(entry, 0, 12);
1307         entry->LINIP = cb_desc->bLastIniPkt;
1308         entry->FirstSeg = 1;
1309         entry->LastSeg = 1;
1310         if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1311                 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1312         } else {
1313                 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1314
1315                 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1316                 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1317                 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1318                                       entry_tmp->Offset);
1319                 entry_tmp->QueueSelect = QSLT_CMD;
1320                 entry_tmp->TxFWInfoSize = 0x08;
1321                 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1322         }
1323         entry->TxBufferSize = skb->len;
1324         entry->TxBuffAddr = mapping;
1325         entry->OWN = 1;
1326 }
1327
1328 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1329 {
1330         u8  ret_rate = 0x02;
1331
1332         if (!bIsHT) {
1333                 switch (rate) {
1334                 case DESC90_RATE1M:
1335                         ret_rate = MGN_1M;
1336                         break;
1337                 case DESC90_RATE2M:
1338                         ret_rate = MGN_2M;
1339                         break;
1340                 case DESC90_RATE5_5M:
1341                         ret_rate = MGN_5_5M;
1342                         break;
1343                 case DESC90_RATE11M:
1344                         ret_rate = MGN_11M;
1345                         break;
1346                 case DESC90_RATE6M:
1347                         ret_rate = MGN_6M;
1348                         break;
1349                 case DESC90_RATE9M:
1350                         ret_rate = MGN_9M;
1351                         break;
1352                 case DESC90_RATE12M:
1353                         ret_rate = MGN_12M;
1354                         break;
1355                 case DESC90_RATE18M:
1356                         ret_rate = MGN_18M;
1357                         break;
1358                 case DESC90_RATE24M:
1359                         ret_rate = MGN_24M;
1360                         break;
1361                 case DESC90_RATE36M:
1362                         ret_rate = MGN_36M;
1363                         break;
1364                 case DESC90_RATE48M:
1365                         ret_rate = MGN_48M;
1366                         break;
1367                 case DESC90_RATE54M:
1368                         ret_rate = MGN_54M;
1369                         break;
1370
1371                 default:
1372                         RT_TRACE(COMP_RECV,
1373                                  "_rtl92e_rate_hw_to_mgn(): Non supportedRate [%x], bIsHT = %d!!!\n",
1374                                  rate, bIsHT);
1375                         break;
1376                 }
1377
1378         } else {
1379                 switch (rate) {
1380                 case DESC90_RATEMCS0:
1381                         ret_rate = MGN_MCS0;
1382                         break;
1383                 case DESC90_RATEMCS1:
1384                         ret_rate = MGN_MCS1;
1385                         break;
1386                 case DESC90_RATEMCS2:
1387                         ret_rate = MGN_MCS2;
1388                         break;
1389                 case DESC90_RATEMCS3:
1390                         ret_rate = MGN_MCS3;
1391                         break;
1392                 case DESC90_RATEMCS4:
1393                         ret_rate = MGN_MCS4;
1394                         break;
1395                 case DESC90_RATEMCS5:
1396                         ret_rate = MGN_MCS5;
1397                         break;
1398                 case DESC90_RATEMCS6:
1399                         ret_rate = MGN_MCS6;
1400                         break;
1401                 case DESC90_RATEMCS7:
1402                         ret_rate = MGN_MCS7;
1403                         break;
1404                 case DESC90_RATEMCS8:
1405                         ret_rate = MGN_MCS8;
1406                         break;
1407                 case DESC90_RATEMCS9:
1408                         ret_rate = MGN_MCS9;
1409                         break;
1410                 case DESC90_RATEMCS10:
1411                         ret_rate = MGN_MCS10;
1412                         break;
1413                 case DESC90_RATEMCS11:
1414                         ret_rate = MGN_MCS11;
1415                         break;
1416                 case DESC90_RATEMCS12:
1417                         ret_rate = MGN_MCS12;
1418                         break;
1419                 case DESC90_RATEMCS13:
1420                         ret_rate = MGN_MCS13;
1421                         break;
1422                 case DESC90_RATEMCS14:
1423                         ret_rate = MGN_MCS14;
1424                         break;
1425                 case DESC90_RATEMCS15:
1426                         ret_rate = MGN_MCS15;
1427                         break;
1428                 case DESC90_RATEMCS32:
1429                         ret_rate = (0x80|0x20);
1430                         break;
1431
1432                 default:
1433                         RT_TRACE(COMP_RECV,
1434                                  "_rtl92e_rate_hw_to_mgn(): Non supported Rate [%x], bIsHT = %d!!!\n",
1435                                  rate, bIsHT);
1436                         break;
1437                 }
1438         }
1439
1440         return ret_rate;
1441 }
1442
1443 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1444 {
1445         long retsig;
1446
1447         if (currsig >= 61 && currsig <= 100)
1448                 retsig = 90 + ((currsig - 60) / 4);
1449         else if (currsig >= 41 && currsig <= 60)
1450                 retsig = 78 + ((currsig - 40) / 2);
1451         else if (currsig >= 31 && currsig <= 40)
1452                 retsig = 66 + (currsig - 30);
1453         else if (currsig >= 21 && currsig <= 30)
1454                 retsig = 54 + (currsig - 20);
1455         else if (currsig >= 5 && currsig <= 20)
1456                 retsig = 42 + (((currsig - 5) * 2) / 3);
1457         else if (currsig == 4)
1458                 retsig = 36;
1459         else if (currsig == 3)
1460                 retsig = 27;
1461         else if (currsig == 2)
1462                 retsig = 18;
1463         else if (currsig == 1)
1464                 retsig = 9;
1465         else
1466                 retsig = currsig;
1467
1468         return retsig;
1469 }
1470
1471
1472 #define  rx_hal_is_cck_rate(_pdrvinfo)\
1473                         ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1474                         _pdrvinfo->RxRate == DESC90_RATE2M ||\
1475                         _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1476                         _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1477                         !_pdrvinfo->RxHT)
1478
1479 static void _rtl92e_query_rxphystatus(
1480         struct r8192_priv *priv,
1481         struct rtllib_rx_stats *pstats,
1482         struct rx_desc  *pdesc,
1483         struct rx_fwinfo   *pdrvinfo,
1484         struct rtllib_rx_stats *precord_stats,
1485         bool bpacket_match_bssid,
1486         bool bpacket_toself,
1487         bool bPacketBeacon,
1488         bool bToSelfBA
1489         )
1490 {
1491         struct phy_sts_ofdm_819xpci *pofdm_buf;
1492         struct phy_sts_cck_819xpci *pcck_buf;
1493         struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1494         u8 *prxpkt;
1495         u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1496         char rx_pwr[4], rx_pwr_all = 0;
1497         char rx_snrX, rx_evmX;
1498         u8 evm, pwdb_all;
1499         u32 RSSI, total_rssi = 0;
1500         u8 is_cck_rate = 0;
1501         u8 rf_rx_num = 0;
1502         static  u8 check_reg824;
1503         static  u32 reg824_bit9;
1504
1505         priv->stats.numqry_phystatus++;
1506
1507         is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1508         memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1509         pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1510                                     bpacket_match_bssid;
1511         pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1512         pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1513         pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1514         pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1515         if (check_reg824 == 0) {
1516                 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1517                                                 rFPGA0_XA_HSSIParameter2,
1518                                                 0x200);
1519                 check_reg824 = 1;
1520         }
1521
1522
1523         prxpkt = (u8 *)pdrvinfo;
1524
1525         prxpkt += sizeof(struct rx_fwinfo);
1526
1527         pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1528         pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1529
1530         pstats->RxMIMOSignalQuality[0] = -1;
1531         pstats->RxMIMOSignalQuality[1] = -1;
1532         precord_stats->RxMIMOSignalQuality[0] = -1;
1533         precord_stats->RxMIMOSignalQuality[1] = -1;
1534
1535         if (is_cck_rate) {
1536                 u8 report;
1537
1538                 priv->stats.numqry_phystatusCCK++;
1539                 if (!reg824_bit9) {
1540                         report = pcck_buf->cck_agc_rpt & 0xc0;
1541                         report >>= 6;
1542                         switch (report) {
1543                         case 0x3:
1544                                 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1545                                              0x3e);
1546                                 break;
1547                         case 0x2:
1548                                 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1549                                              0x3e);
1550                                 break;
1551                         case 0x1:
1552                                 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1553                                              0x3e);
1554                                 break;
1555                         case 0x0:
1556                                 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1557                                 break;
1558                         }
1559                 } else {
1560                         report = pcck_buf->cck_agc_rpt & 0x60;
1561                         report >>= 5;
1562                         switch (report) {
1563                         case 0x3:
1564                                 rx_pwr_all = -35 -
1565                                         ((pcck_buf->cck_agc_rpt &
1566                                         0x1f) << 1);
1567                                 break;
1568                         case 0x2:
1569                                 rx_pwr_all = -23 -
1570                                         ((pcck_buf->cck_agc_rpt &
1571                                          0x1f) << 1);
1572                                 break;
1573                         case 0x1:
1574                                 rx_pwr_all = -11 -
1575                                          ((pcck_buf->cck_agc_rpt &
1576                                          0x1f) << 1);
1577                                 break;
1578                         case 0x0:
1579                                 rx_pwr_all = -8 -
1580                                          ((pcck_buf->cck_agc_rpt &
1581                                          0x1f) << 1);
1582                                 break;
1583                         }
1584                 }
1585
1586                 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1587                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1588                 pstats->RecvSignalPower = rx_pwr_all;
1589
1590                 if (bpacket_match_bssid) {
1591                         u8      sq;
1592
1593                         if (pstats->RxPWDBAll > 40) {
1594                                 sq = 100;
1595                         } else {
1596                                 sq = pcck_buf->sq_rpt;
1597
1598                                 if (pcck_buf->sq_rpt > 64)
1599                                         sq = 0;
1600                                 else if (pcck_buf->sq_rpt < 20)
1601                                         sq = 100;
1602                                 else
1603                                         sq = ((64-sq) * 100) / 44;
1604                         }
1605                         pstats->SignalQuality = sq;
1606                         precord_stats->SignalQuality = sq;
1607                         pstats->RxMIMOSignalQuality[0] = sq;
1608                         precord_stats->RxMIMOSignalQuality[0] = sq;
1609                         pstats->RxMIMOSignalQuality[1] = -1;
1610                         precord_stats->RxMIMOSignalQuality[1] = -1;
1611                 }
1612         } else {
1613                 priv->stats.numqry_phystatusHT++;
1614                 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1615                         if (priv->brfpath_rxenable[i])
1616                                 rf_rx_num++;
1617
1618                         rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1619                                      2) - 110;
1620
1621                         tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1622                         rx_snrX = (char)(tmp_rxsnr);
1623                         rx_snrX /= 2;
1624                         priv->stats.rxSNRdB[i] = (long)rx_snrX;
1625
1626                         RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1627                         if (priv->brfpath_rxenable[i])
1628                                 total_rssi += RSSI;
1629
1630                         if (bpacket_match_bssid) {
1631                                 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1632                                 precord_stats->RxMIMOSignalStrength[i] =
1633                                                                 (u8) RSSI;
1634                         }
1635                 }
1636
1637
1638                 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1639                 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1640
1641                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1642                 pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1643                 pstats->RecvSignalPower = rx_pwr_all;
1644                 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1645                     pdrvinfo->RxRate <= DESC90_RATEMCS15)
1646                         max_spatial_stream = 2;
1647                 else
1648                         max_spatial_stream = 1;
1649
1650                 for (i = 0; i < max_spatial_stream; i++) {
1651                         tmp_rxevm = pofdm_buf->rxevm_X[i];
1652                         rx_evmX = (char)(tmp_rxevm);
1653
1654                         rx_evmX /= 2;
1655
1656                         evm = rtl92e_evm_db_to_percent(rx_evmX);
1657                         if (bpacket_match_bssid) {
1658                                 if (i == 0) {
1659                                         pstats->SignalQuality = (u8)(evm &
1660                                                                  0xff);
1661                                         precord_stats->SignalQuality = (u8)(evm
1662                                                                         & 0xff);
1663                                 }
1664                                 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1665                                                                  0xff);
1666                                 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1667                                                                         & 0xff);
1668                         }
1669                 }
1670
1671
1672                 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1673                 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1674                         &rxsc_sgien_exflg;
1675                 if (pdrvinfo->BW)
1676                         priv->stats.received_bwtype[1+prxsc->rxsc]++;
1677                 else
1678                         priv->stats.received_bwtype[0]++;
1679         }
1680
1681         if (is_cck_rate) {
1682                 pstats->SignalStrength = precord_stats->SignalStrength =
1683                                          (u8)(_rtl92e_signal_scale_mapping(priv,
1684                                          (long)pwdb_all));
1685
1686         } else {
1687                 if (rf_rx_num != 0)
1688                         pstats->SignalStrength = precord_stats->SignalStrength =
1689                                          (u8)(_rtl92e_signal_scale_mapping(priv,
1690                                          (long)(total_rssi /= rf_rx_num)));
1691         }
1692 }
1693
1694 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1695                                     struct rtllib_rx_stats *prev_st,
1696                                     struct rtllib_rx_stats *curr_st)
1697 {
1698         bool bcheck = false;
1699         u8      rfpath;
1700         u32 ij, tmp_val;
1701         static u32 slide_rssi_index, slide_rssi_statistics;
1702         static u32 slide_evm_index, slide_evm_statistics;
1703         static u32 last_rssi, last_evm;
1704         static u32 slide_beacon_adc_pwdb_index;
1705         static u32 slide_beacon_adc_pwdb_statistics;
1706         static u32 last_beacon_adc_pwdb;
1707         struct rtllib_hdr_3addr *hdr;
1708         u16 sc;
1709         unsigned int frag, seq;
1710
1711         hdr = (struct rtllib_hdr_3addr *)buffer;
1712         sc = le16_to_cpu(hdr->seq_ctl);
1713         frag = WLAN_GET_SEQ_FRAG(sc);
1714         seq = WLAN_GET_SEQ_SEQ(sc);
1715         curr_st->Seq_Num = seq;
1716         if (!prev_st->bIsAMPDU)
1717                 bcheck = true;
1718
1719         if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1720                 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1721                 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1722                 priv->stats.slide_rssi_total -= last_rssi;
1723         }
1724         priv->stats.slide_rssi_total += prev_st->SignalStrength;
1725
1726         priv->stats.slide_signal_strength[slide_rssi_index++] =
1727                                          prev_st->SignalStrength;
1728         if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1729                 slide_rssi_index = 0;
1730
1731         tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1732         priv->stats.signal_strength = rtl92e_translate_to_dbm(priv,
1733                                                               (u8)tmp_val);
1734         curr_st->rssi = priv->stats.signal_strength;
1735         if (!prev_st->bPacketMatchBSSID) {
1736                 if (!prev_st->bToSelfBA)
1737                         return;
1738         }
1739
1740         if (!bcheck)
1741                 return;
1742
1743         priv->stats.num_process_phyinfo++;
1744         if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1745                 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1746                         if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1747                                 continue;
1748                         RT_TRACE(COMP_DBG,
1749                                  "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath]  = %d\n",
1750                                  prev_st->RxMIMOSignalStrength[rfpath]);
1751                         if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1752                                 priv->stats.rx_rssi_percentage[rfpath] =
1753                                          prev_st->RxMIMOSignalStrength[rfpath];
1754                         }
1755                         if (prev_st->RxMIMOSignalStrength[rfpath]  >
1756                             priv->stats.rx_rssi_percentage[rfpath]) {
1757                                 priv->stats.rx_rssi_percentage[rfpath] =
1758                                         ((priv->stats.rx_rssi_percentage[rfpath]
1759                                         * (RX_SMOOTH - 1)) +
1760                                         (prev_st->RxMIMOSignalStrength
1761                                         [rfpath])) / (RX_SMOOTH);
1762                                 priv->stats.rx_rssi_percentage[rfpath] =
1763                                          priv->stats.rx_rssi_percentage[rfpath]
1764                                          + 1;
1765                         } else {
1766                                 priv->stats.rx_rssi_percentage[rfpath] =
1767                                    ((priv->stats.rx_rssi_percentage[rfpath] *
1768                                    (RX_SMOOTH-1)) +
1769                                    (prev_st->RxMIMOSignalStrength[rfpath])) /
1770                                    (RX_SMOOTH);
1771                         }
1772                         RT_TRACE(COMP_DBG,
1773                                  "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath]  = %d\n",
1774                                  priv->stats.rx_rssi_percentage[rfpath]);
1775                 }
1776         }
1777
1778
1779         if (prev_st->bPacketBeacon) {
1780                 if (slide_beacon_adc_pwdb_statistics++ >=
1781                     PHY_Beacon_RSSI_SLID_WIN_MAX) {
1782                         slide_beacon_adc_pwdb_statistics =
1783                                          PHY_Beacon_RSSI_SLID_WIN_MAX;
1784                         last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1785                                                [slide_beacon_adc_pwdb_index];
1786                         priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1787                 }
1788                 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1789                 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1790                                                          prev_st->RxPWDBAll;
1791                 slide_beacon_adc_pwdb_index++;
1792                 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1793                         slide_beacon_adc_pwdb_index = 0;
1794                 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1795                                      slide_beacon_adc_pwdb_statistics;
1796                 if (prev_st->RxPWDBAll >= 3)
1797                         prev_st->RxPWDBAll -= 3;
1798         }
1799
1800         RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1801                                 prev_st->bIsCCK ? "CCK" : "OFDM",
1802                                 prev_st->RxPWDBAll);
1803
1804         if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1805             prev_st->bToSelfBA) {
1806                 if (priv->undecorated_smoothed_pwdb < 0)
1807                         priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1808                 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1809                         priv->undecorated_smoothed_pwdb =
1810                                         (((priv->undecorated_smoothed_pwdb) *
1811                                         (RX_SMOOTH-1)) +
1812                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1813                         priv->undecorated_smoothed_pwdb =
1814                                          priv->undecorated_smoothed_pwdb + 1;
1815                 } else {
1816                         priv->undecorated_smoothed_pwdb =
1817                                         (((priv->undecorated_smoothed_pwdb) *
1818                                         (RX_SMOOTH-1)) +
1819                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1820                 }
1821                 rtl92e_update_rx_statistics(priv, prev_st);
1822         }
1823
1824         if (prev_st->SignalQuality != 0) {
1825                 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1826                     prev_st->bToSelfBA) {
1827                         if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1828                                 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1829                                 last_evm =
1830                                          priv->stats.slide_evm[slide_evm_index];
1831                                 priv->stats.slide_evm_total -= last_evm;
1832                         }
1833
1834                         priv->stats.slide_evm_total += prev_st->SignalQuality;
1835
1836                         priv->stats.slide_evm[slide_evm_index++] =
1837                                                  prev_st->SignalQuality;
1838                         if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1839                                 slide_evm_index = 0;
1840
1841                         tmp_val = priv->stats.slide_evm_total /
1842                                   slide_evm_statistics;
1843                         priv->stats.signal_quality = tmp_val;
1844                         priv->stats.last_signal_strength_inpercent = tmp_val;
1845                 }
1846
1847                 if (prev_st->bPacketToSelf ||
1848                     prev_st->bPacketBeacon ||
1849                     prev_st->bToSelfBA) {
1850                         for (ij = 0; ij < 2; ij++) {
1851                                 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1852                                         if (priv->stats.rx_evm_percentage[ij] == 0)
1853                                                 priv->stats.rx_evm_percentage[ij] =
1854                                                    prev_st->RxMIMOSignalQuality[ij];
1855                                         priv->stats.rx_evm_percentage[ij] =
1856                                           ((priv->stats.rx_evm_percentage[ij] *
1857                                           (RX_SMOOTH - 1)) +
1858                                           (prev_st->RxMIMOSignalQuality[ij])) /
1859                                           (RX_SMOOTH);
1860                                 }
1861                         }
1862                 }
1863         }
1864 }
1865
1866 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1867                                               struct sk_buff *skb,
1868                                               struct rtllib_rx_stats *pstats,
1869                                               struct rx_desc *pdesc,
1870                                               struct rx_fwinfo *pdrvinfo)
1871 {
1872         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1873         bool bpacket_match_bssid, bpacket_toself;
1874         bool bPacketBeacon = false;
1875         struct rtllib_hdr_3addr *hdr;
1876         bool bToSelfBA = false;
1877         static struct rtllib_rx_stats  previous_stats;
1878         u16 fc, type;
1879         u8 *tmp_buf;
1880         u8 *praddr;
1881
1882         tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1883
1884         hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1885         fc = le16_to_cpu(hdr->frame_ctl);
1886         type = WLAN_FC_GET_TYPE(fc);
1887         praddr = hdr->addr1;
1888
1889         bpacket_match_bssid =
1890                 ((type != RTLLIB_FTYPE_CTL) &&
1891                  ether_addr_equal(priv->rtllib->current_network.bssid,
1892                                   (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1893                                   (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1894                                   hdr->addr3) &&
1895                  (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1896         bpacket_toself = bpacket_match_bssid &&         /* check this */
1897                          ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1898         if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1899                 bPacketBeacon = true;
1900         if (bpacket_match_bssid)
1901                 priv->stats.numpacket_matchbssid++;
1902         if (bpacket_toself)
1903                 priv->stats.numpacket_toself++;
1904         _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1905         _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1906                                   &previous_stats, bpacket_match_bssid,
1907                                   bpacket_toself, bPacketBeacon, bToSelfBA);
1908         rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1909 }
1910
1911 static void _rtl92e_update_received_rate_histogram_stats(
1912                                            struct net_device *dev,
1913                                            struct rtllib_rx_stats *pstats)
1914 {
1915         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1916         u32 rcvType = 1;
1917         u32 rateIndex;
1918         u32 preamble_guardinterval;
1919
1920         if (pstats->bCRC)
1921                 rcvType = 2;
1922         else if (pstats->bICV)
1923                 rcvType = 3;
1924
1925         if (pstats->bShortPreamble)
1926                 preamble_guardinterval = 1;
1927         else
1928                 preamble_guardinterval = 0;
1929
1930         switch (pstats->rate) {
1931         case MGN_1M:
1932                 rateIndex = 0;
1933                 break;
1934         case MGN_2M:
1935                 rateIndex = 1;
1936                  break;
1937         case MGN_5_5M:
1938                 rateIndex = 2;
1939                 break;
1940         case MGN_11M:
1941                 rateIndex = 3;
1942                 break;
1943         case MGN_6M:
1944                 rateIndex = 4;
1945                 break;
1946         case MGN_9M:
1947                 rateIndex = 5;
1948                 break;
1949         case MGN_12M:
1950                 rateIndex = 6;
1951                 break;
1952         case MGN_18M:
1953                 rateIndex = 7;
1954                  break;
1955         case MGN_24M:
1956                 rateIndex = 8;
1957                 break;
1958         case MGN_36M:
1959                 rateIndex = 9;
1960                 break;
1961         case MGN_48M:
1962                 rateIndex = 10;
1963                 break;
1964         case MGN_54M:
1965                 rateIndex = 11;
1966                 break;
1967         case MGN_MCS0:
1968                 rateIndex = 12;
1969                 break;
1970         case MGN_MCS1:
1971                 rateIndex = 13;
1972                 break;
1973         case MGN_MCS2:
1974                 rateIndex = 14;
1975                 break;
1976         case MGN_MCS3:
1977                 rateIndex = 15;
1978                 break;
1979         case MGN_MCS4:
1980                 rateIndex = 16;
1981                 break;
1982         case MGN_MCS5:
1983                 rateIndex = 17;
1984                 break;
1985         case MGN_MCS6:
1986                 rateIndex = 18;
1987                 break;
1988         case MGN_MCS7:
1989                 rateIndex = 19;
1990                 break;
1991         case MGN_MCS8:
1992                 rateIndex = 20;
1993                 break;
1994         case MGN_MCS9:
1995                 rateIndex = 21;
1996                 break;
1997         case MGN_MCS10:
1998                 rateIndex = 22;
1999                 break;
2000         case MGN_MCS11:
2001                 rateIndex = 23;
2002                 break;
2003         case MGN_MCS12:
2004                 rateIndex = 24;
2005                 break;
2006         case MGN_MCS13:
2007                 rateIndex = 25;
2008                 break;
2009         case MGN_MCS14:
2010                 rateIndex = 26;
2011                 break;
2012         case MGN_MCS15:
2013                 rateIndex = 27;
2014                 break;
2015         default:
2016                 rateIndex = 28;
2017                 break;
2018         }
2019         priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2020         priv->stats.received_rate_histogram[0][rateIndex]++;
2021         priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2022 }
2023
2024 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2025                          struct rx_desc *pdesc, struct sk_buff *skb)
2026 {
2027         struct r8192_priv *priv = rtllib_priv(dev);
2028         struct rx_fwinfo *pDrvInfo = NULL;
2029
2030         stats->bICV = pdesc->ICV;
2031         stats->bCRC = pdesc->CRC32;
2032         stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2033
2034         stats->Length = pdesc->Length;
2035         if (stats->Length < 24)
2036                 stats->bHwError |= 1;
2037
2038         if (stats->bHwError) {
2039                 stats->bShift = false;
2040
2041                 if (pdesc->CRC32) {
2042                         if (pdesc->Length < 500)
2043                                 priv->stats.rxcrcerrmin++;
2044                         else if (pdesc->Length > 1000)
2045                                 priv->stats.rxcrcerrmax++;
2046                         else
2047                                 priv->stats.rxcrcerrmid++;
2048                 }
2049                 return false;
2050         }
2051
2052         stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2053         stats->RxBufShift = ((pdesc->Shift)&0x03);
2054         stats->Decrypted = !pdesc->SWDec;
2055
2056         pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2057
2058         stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
2059                                              (u8)pDrvInfo->RxRate);
2060         stats->bShortPreamble = pDrvInfo->SPLCP;
2061
2062         _rtl92e_update_received_rate_histogram_stats(dev, stats);
2063
2064         stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2065         stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2066                             (pDrvInfo->FirstAGGR == 1);
2067
2068         stats->TimeStampLow = pDrvInfo->TSFL;
2069         stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
2070
2071         rtl92e_update_rx_pkt_timestamp(dev, stats);
2072
2073         if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2074                 stats->bShift = 1;
2075
2076         stats->RxIs40MHzPacket = pDrvInfo->BW;
2077
2078         _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
2079
2080         if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2081                 RT_TRACE(COMP_RXDESC,
2082                          "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2083                          pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2084         skb_trim(skb, skb->len - 4/*sCrcLng*/);
2085
2086
2087         stats->packetlength = stats->Length-4;
2088         stats->fraglength = stats->packetlength;
2089         stats->fragoffset = 0;
2090         stats->ntotalfrag = 1;
2091         return true;
2092 }
2093
2094 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
2095 {
2096         struct r8192_priv *priv = rtllib_priv(dev);
2097         int i;
2098         u8      OpMode;
2099         u8      u1bTmp;
2100         u32     ulRegRead;
2101
2102         OpMode = RT_OP_MODE_NO_LINK;
2103         priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2104
2105         if (!priv->rtllib->bSupportRemoteWakeUp) {
2106                 u1bTmp = 0x0;
2107                 rtl92e_writeb(dev, CMDR, u1bTmp);
2108         }
2109
2110         mdelay(20);
2111
2112         if (!reset) {
2113                 mdelay(150);
2114
2115                 priv->bHwRfOffAction = 2;
2116
2117                 if (!priv->rtllib->bSupportRemoteWakeUp) {
2118                         rtl92e_set_rf_off(dev);
2119                         ulRegRead = rtl92e_readl(dev, CPU_GEN);
2120                         ulRegRead |= CPU_GEN_SYSTEM_RESET;
2121                         rtl92e_writel(dev, CPU_GEN, ulRegRead);
2122                 } else {
2123                         rtl92e_writel(dev, WFCRC0, 0xffffffff);
2124                         rtl92e_writel(dev, WFCRC1, 0xffffffff);
2125                         rtl92e_writel(dev, WFCRC2, 0xffffffff);
2126
2127
2128                         rtl92e_writeb(dev, PMR, 0x5);
2129                         rtl92e_writeb(dev, MacBlkCtrl, 0xa);
2130                 }
2131         }
2132
2133         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2134                 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2135         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2136                 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2137
2138         skb_queue_purge(&priv->skb_queue);
2139 }
2140
2141 void rtl92e_update_ratr_table(struct net_device *dev)
2142 {
2143         struct r8192_priv *priv = rtllib_priv(dev);
2144         struct rtllib_device *ieee = priv->rtllib;
2145         u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2146         u32 ratr_value = 0;
2147         u16 rate_config = 0;
2148         u8 rate_index = 0;
2149
2150         rtl92e_config_rate(dev, &rate_config);
2151         ratr_value = rate_config | *pMcsRate << 12;
2152         switch (ieee->mode) {
2153         case IEEE_A:
2154                 ratr_value &= 0x00000FF0;
2155                 break;
2156         case IEEE_B:
2157                 ratr_value &= 0x0000000F;
2158                 break;
2159         case IEEE_G:
2160         case IEEE_G|IEEE_B:
2161                 ratr_value &= 0x00000FF7;
2162                 break;
2163         case IEEE_N_24G:
2164         case IEEE_N_5G:
2165                 if (ieee->pHTInfo->PeerMimoPs == 0) {
2166                         ratr_value &= 0x0007F007;
2167                 } else {
2168                         if (priv->rf_type == RF_1T2R)
2169                                 ratr_value &= 0x000FF007;
2170                         else
2171                                 ratr_value &= 0x0F81F007;
2172                 }
2173                 break;
2174         default:
2175                 break;
2176         }
2177         ratr_value &= 0x0FFFFFFF;
2178         if (ieee->pHTInfo->bCurTxBW40MHz &&
2179             ieee->pHTInfo->bCurShortGI40MHz)
2180                 ratr_value |= 0x80000000;
2181         else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2182                   ieee->pHTInfo->bCurShortGI20MHz)
2183                 ratr_value |= 0x80000000;
2184         rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
2185         rtl92e_writeb(dev, UFWP, 1);
2186 }
2187
2188 void
2189 rtl92e_init_variables(struct net_device  *dev)
2190 {
2191         struct r8192_priv *priv = rtllib_priv(dev);
2192
2193         strcpy(priv->nick, "rtl8192E");
2194
2195         priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2196                 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2197                 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2198
2199         priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2200
2201         priv->ShortRetryLimit = 0x30;
2202         priv->LongRetryLimit = 0x30;
2203
2204         priv->ReceiveConfig = RCR_ADD3  |
2205                 RCR_AMF | RCR_ADF |
2206                 RCR_AICV |
2207                 RCR_AB | RCR_AM | RCR_APM |
2208                 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2209                 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2210
2211         priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2212                             IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2213                             IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2214                             IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2215                             IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2216                             IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2217
2218         priv->PwrDomainProtect = false;
2219
2220         priv->bfirst_after_down = false;
2221 }
2222
2223 void rtl92e_enable_irq(struct net_device *dev)
2224 {
2225         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2226
2227         priv->irq_enabled = 1;
2228
2229         rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
2230
2231 }
2232
2233 void rtl92e_disable_irq(struct net_device *dev)
2234 {
2235         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2236
2237         rtl92e_writel(dev, INTA_MASK, 0);
2238
2239         priv->irq_enabled = 0;
2240 }
2241
2242 void rtl92e_clear_irq(struct net_device *dev)
2243 {
2244         u32 tmp = 0;
2245
2246         tmp = rtl92e_readl(dev, ISR);
2247         rtl92e_writel(dev, ISR, tmp);
2248 }
2249
2250
2251 void rtl92e_enable_rx(struct net_device *dev)
2252 {
2253         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2254
2255         rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2256 }
2257
2258 static const u32 TX_DESC_BASE[] = {
2259         BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2260 };
2261
2262 void rtl92e_enable_tx(struct net_device *dev)
2263 {
2264         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2265         u32 i;
2266
2267         for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2268                 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2269 }
2270
2271
2272 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2273 {
2274         *p_inta = rtl92e_readl(dev, ISR);
2275         rtl92e_writel(dev, ISR, *p_inta);
2276 }
2277
2278 bool rtl92e_is_rx_stuck(struct net_device *dev)
2279 {
2280         struct r8192_priv *priv = rtllib_priv(dev);
2281         u16               RegRxCounter = rtl92e_readw(dev, 0x130);
2282         bool              bStuck = false;
2283         static u8         rx_chk_cnt;
2284         u32             SlotIndex = 0, TotalRxStuckCount = 0;
2285         u8              i;
2286         u8              SilentResetRxSoltNum = 4;
2287
2288         RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2289                  __func__, RegRxCounter, priv->RxCounter);
2290
2291         rx_chk_cnt++;
2292         if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2293                 rx_chk_cnt = 0;
2294         } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2295           && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2296           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2297           || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2298           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2299                 if (rx_chk_cnt < 2)
2300                         return bStuck;
2301                 rx_chk_cnt = 0;
2302         } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2303                   (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2304                 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2305                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2306                 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2307                 if (rx_chk_cnt < 4)
2308                         return bStuck;
2309                 rx_chk_cnt = 0;
2310         } else {
2311                 if (rx_chk_cnt < 8)
2312                         return bStuck;
2313                 rx_chk_cnt = 0;
2314         }
2315
2316
2317         SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2318
2319         if (priv->RxCounter == RegRxCounter) {
2320                 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2321
2322                 for (i = 0; i < SilentResetRxSoltNum; i++)
2323                         TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2324
2325                 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2326                         bStuck = true;
2327                         for (i = 0; i < SilentResetRxSoltNum; i++)
2328                                 TotalRxStuckCount +=
2329                                          priv->SilentResetRxStuckEvent[i];
2330                 }
2331
2332
2333         } else {
2334                 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2335         }
2336
2337         priv->RxCounter = RegRxCounter;
2338
2339         return bStuck;
2340 }
2341
2342 bool rtl92e_is_tx_stuck(struct net_device *dev)
2343 {
2344         struct r8192_priv *priv = rtllib_priv(dev);
2345         bool    bStuck = false;
2346         u16     RegTxCounter = rtl92e_readw(dev, 0x128);
2347
2348         RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2349                  __func__, RegTxCounter, priv->TxCounter);
2350
2351         if (priv->TxCounter == RegTxCounter)
2352                 bStuck = true;
2353
2354         priv->TxCounter = RegTxCounter;
2355
2356         return bStuck;
2357 }
2358
2359 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2360 {
2361         struct r8192_priv *priv = rtllib_priv(dev);
2362         struct rtllib_device *ieee = priv->rtllib;
2363
2364         if (ieee->rtllib_ap_sec_type &&
2365            (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2366                                      SEC_ALG_TKIP))) {
2367                 return false;
2368         } else {
2369                 return true;
2370         }
2371 }
2372
2373 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2374 {
2375         struct r8192_priv *priv = rtllib_priv(dev);
2376         struct rtllib_device *ieee = priv->rtllib;
2377
2378         return ieee->bHalfWirelessN24GMode;
2379 }