1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * The full GNU General Public License is included in this distribution in the
10 * file called LICENSE.
12 * Contact Information:
13 * wlanfae <wlanfae@realtek.com>
14 ******************************************************************************/
20 #include <linux/types.h>
22 #define MAX_SILENT_RESET_RX_SLOT_NUM 10
24 #define RX_MPDU_QUEUE 0
26 enum rtl819x_loopback {
27 RTL819X_NO_LOOPBACK = 0,
28 RTL819X_MAC_LOOPBACK = 1,
29 RTL819X_DMA_LOOPBACK = 2,
30 RTL819X_CCK_LOOPBACK = 3,
33 #define DESC90_RATE1M 0x00
34 #define DESC90_RATE2M 0x01
35 #define DESC90_RATE5_5M 0x02
36 #define DESC90_RATE11M 0x03
37 #define DESC90_RATE6M 0x04
38 #define DESC90_RATE9M 0x05
39 #define DESC90_RATE12M 0x06
40 #define DESC90_RATE18M 0x07
41 #define DESC90_RATE24M 0x08
42 #define DESC90_RATE36M 0x09
43 #define DESC90_RATE48M 0x0a
44 #define DESC90_RATE54M 0x0b
45 #define DESC90_RATEMCS0 0x00
46 #define DESC90_RATEMCS1 0x01
47 #define DESC90_RATEMCS2 0x02
48 #define DESC90_RATEMCS3 0x03
49 #define DESC90_RATEMCS4 0x04
50 #define DESC90_RATEMCS5 0x05
51 #define DESC90_RATEMCS6 0x06
52 #define DESC90_RATEMCS7 0x07
53 #define DESC90_RATEMCS8 0x08
54 #define DESC90_RATEMCS9 0x09
55 #define DESC90_RATEMCS10 0x0a
56 #define DESC90_RATEMCS11 0x0b
57 #define DESC90_RATEMCS12 0x0c
58 #define DESC90_RATEMCS13 0x0d
59 #define DESC90_RATEMCS14 0x0e
60 #define DESC90_RATEMCS15 0x0f
61 #define DESC90_RATEMCS32 0x20
63 #define SHORT_SLOT_TIME 9
64 #define NON_SHORT_SLOT_TIME 20
72 #define QSLT_BEACON 0x10
73 #define QSLT_HIGH 0x11
74 #define QSLT_MGNT 0x12
77 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
78 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
79 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
80 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
81 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
82 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
83 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
85 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
86 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
87 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
88 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
89 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
90 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
91 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
92 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
94 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
95 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
96 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
99 enum version_8190_loopback {
100 VERSION_8190_BD = 0x3,
104 #define IC_VersionCut_C 0x2
105 #define IC_VersionCut_D 0x3
106 #define IC_VersionCut_E 0x4
109 RF_OP_By_SW_3wire = 0,
114 struct bb_reg_definition {
132 u32 rfLSSIReadBackPi;
135 struct tx_fwinfo_8190pci {
145 u8 AllowAggregation:1;
155 u32 TxPerPktInfoFeedback:1;
167 struct log_int_8190 {
182 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
189 struct phy_sts_ofdm_819xpci {
205 struct phy_sts_cck_819xpci {
212 #define PHY_RSSI_SLID_WIN_MAX 100
213 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10