1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
16 #ifndef __ODM_REGDEFINE11N_H__
17 #define __ODM_REGDEFINE11N_H__
21 #define ODM_REG_RF_MODE_11N 0x00
22 #define ODM_REG_RF_0B_11N 0x0B
23 #define ODM_REG_CHNBW_11N 0x18
24 #define ODM_REG_T_METER_11N 0x24
25 #define ODM_REG_RF_25_11N 0x25
26 #define ODM_REG_RF_26_11N 0x26
27 #define ODM_REG_RF_27_11N 0x27
28 #define ODM_REG_RF_2B_11N 0x2B
29 #define ODM_REG_RF_2C_11N 0x2C
30 #define ODM_REG_RXRF_A3_11N 0x3C
31 #define ODM_REG_T_METER_92D_11N 0x42
32 #define ODM_REG_T_METER_88E_11N 0x42
38 #define ODM_REG_BB_CTRL_11N 0x800
39 #define ODM_REG_RF_PIN_11N 0x804
40 #define ODM_REG_PSD_CTRL_11N 0x808
41 #define ODM_REG_TX_ANT_CTRL_11N 0x80C
42 #define ODM_REG_BB_PWR_SAV5_11N 0x818
43 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824
44 #define ODM_REG_RX_DEFUALT_A_11N 0x858
45 #define ODM_REG_RX_DEFUALT_B_11N 0x85A
46 #define ODM_REG_BB_PWR_SAV3_11N 0x85C
47 #define ODM_REG_ANTSEL_CTRL_11N 0x860
48 #define ODM_REG_RX_ANT_CTRL_11N 0x864
49 #define ODM_REG_PIN_CTRL_11N 0x870
50 #define ODM_REG_BB_PWR_SAV1_11N 0x874
51 #define ODM_REG_ANTSEL_PATH_11N 0x878
52 #define ODM_REG_BB_3WIRE_11N 0x88C
53 #define ODM_REG_SC_CNT_11N 0x8C4
54 #define ODM_REG_PSD_DATA_11N 0x8B4
56 #define ODM_REG_ANT_MAPPING1_11N 0x914
57 #define ODM_REG_ANT_MAPPING2_11N 0x918
59 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
60 #define ODM_REG_CCK_CCA_11N 0xA0A
61 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
62 #define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
63 #define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
64 #define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
65 #define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
66 #define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
67 #define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
68 #define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
69 #define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
70 #define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
71 #define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
72 #define ODM_REG_CCK_FA_RST_11N 0xA2C
73 #define ODM_REG_CCK_FA_MSB_11N 0xA58
74 #define ODM_REG_CCK_FA_LSB_11N 0xA5C
75 #define ODM_REG_CCK_CCA_CNT_11N 0xA60
76 #define ODM_REG_BB_PWR_SAV4_11N 0xA74
78 #define ODM_REG_LNA_SWITCH_11N 0xB2C
79 #define ODM_REG_PATH_SWITCH_11N 0xB30
80 #define ODM_REG_RSSI_CTRL_11N 0xB38
81 #define ODM_REG_CONFIG_ANTA_11N 0xB68
82 #define ODM_REG_RSSI_BT_11N 0xB9C
84 #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
85 #define ODM_REG_RX_PATH_11N 0xC04
86 #define ODM_REG_TRMUX_11N 0xC08
87 #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
88 #define ODM_REG_RXIQI_MATRIX_11N 0xC14
89 #define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
90 #define ODM_REG_IGI_A_11N 0xC50
91 #define ODM_REG_ANTDIV_PARA2_11N 0xC54
92 #define ODM_REG_IGI_B_11N 0xC58
93 #define ODM_REG_ANTDIV_PARA3_11N 0xC5C
94 #define ODM_REG_BB_PWR_SAV2_11N 0xC70
95 #define ODM_REG_RX_OFF_11N 0xC7C
96 #define ODM_REG_TXIQK_MATRIXA_11N 0xC80
97 #define ODM_REG_TXIQK_MATRIXB_11N 0xC88
98 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
99 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
100 #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
101 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4
102 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
104 #define ODM_REG_OFDM_FA_RSTD_11N 0xD00
105 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
106 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
107 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
109 #define ODM_REG_TXAGC_A_6_18_11N 0xE00
110 #define ODM_REG_TXAGC_A_24_54_11N 0xE04
111 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
112 #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
113 #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
114 #define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
115 #define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
116 #define ODM_REG_FPGA0_IQK_11N 0xE28
117 #define ODM_REG_TXIQK_TONE_A_11N 0xE30
118 #define ODM_REG_RXIQK_TONE_A_11N 0xE34
119 #define ODM_REG_TXIQK_PI_A_11N 0xE38
120 #define ODM_REG_RXIQK_PI_A_11N 0xE3C
121 #define ODM_REG_TXIQK_11N 0xE40
122 #define ODM_REG_RXIQK_11N 0xE44
123 #define ODM_REG_IQK_AGC_PTS_11N 0xE48
124 #define ODM_REG_IQK_AGC_RSP_11N 0xE4C
125 #define ODM_REG_BLUETOOTH_11N 0xE6C
126 #define ODM_REG_RX_WAIT_CCA_11N 0xE70
127 #define ODM_REG_TX_CCK_RFON_11N 0xE74
128 #define ODM_REG_TX_CCK_BBON_11N 0xE78
129 #define ODM_REG_OFDM_RFON_11N 0xE7C
130 #define ODM_REG_OFDM_BBON_11N 0xE80
131 #define ODM_REG_TX2RX_11N 0xE84
132 #define ODM_REG_TX2TX_11N 0xE88
133 #define ODM_REG_RX_CCK_11N 0xE8C
134 #define ODM_REG_RX_OFDM_11N 0xED0
135 #define ODM_REG_RX_WAIT_RIFS_11N 0xED4
136 #define ODM_REG_RX2RX_11N 0xED8
137 #define ODM_REG_STANDBY_11N 0xEDC
138 #define ODM_REG_SLEEP_11N 0xEE0
139 #define ODM_REG_PMPD_ANAEN_11N 0xEEC
148 #define ODM_REG_BB_RST_11N 0x02
149 #define ODM_REG_ANTSEL_PIN_11N 0x4C
150 #define ODM_REG_EARLY_MODE_11N 0x4D0
151 #define ODM_REG_RSSI_MONITOR_11N 0x4FE
152 #define ODM_REG_EDCA_VO_11N 0x500
153 #define ODM_REG_EDCA_VI_11N 0x504
154 #define ODM_REG_EDCA_BE_11N 0x508
155 #define ODM_REG_EDCA_BK_11N 0x50C
156 #define ODM_REG_TXPAUSE_11N 0x522
157 #define ODM_REG_RESP_TX_11N 0x6D8
158 #define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
159 #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
163 #define ODM_BIT_IGI_11N 0x0000007F