drivers/staging/rtl8188eu/include/odm_HWConfig.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  *
  15  ******************************************************************************/
  16
  17 #ifndef __HALHWOUTSRC_H__
  18 #define __HALHWOUTSRC_H__
  19
  20 /*  Definition */
  21 /*  CCK Rates, TxHT = 0 */
  22 #define DESC92C_RATE1M                          0x00
  23 #define DESC92C_RATE2M                          0x01
  24 #define DESC92C_RATE5_5M                        0x02
  25 #define DESC92C_RATE11M                         0x03
  26
  27 /*  OFDM Rates, TxHT = 0 */
  28 #define DESC92C_RATE6M                          0x04
  29 #define DESC92C_RATE9M                          0x05
  30 #define DESC92C_RATE12M                         0x06
  31 #define DESC92C_RATE18M                         0x07
  32 #define DESC92C_RATE24M                         0x08
  33 #define DESC92C_RATE36M                         0x09
  34 #define DESC92C_RATE48M                         0x0a
  35 #define DESC92C_RATE54M                         0x0b
  36
  37 /*  MCS Rates, TxHT = 1 */
  38 #define DESC92C_RATEMCS0                        0x0c
  39 #define DESC92C_RATEMCS1                        0x0d
  40 #define DESC92C_RATEMCS2                        0x0e
  41 #define DESC92C_RATEMCS3                        0x0f
  42 #define DESC92C_RATEMCS4                        0x10
  43 #define DESC92C_RATEMCS5                        0x11
  44 #define DESC92C_RATEMCS6                        0x12
  45 #define DESC92C_RATEMCS7                        0x13
  46 #define DESC92C_RATEMCS8                        0x14
  47 #define DESC92C_RATEMCS9                        0x15
  48 #define DESC92C_RATEMCS10                       0x16
  49 #define DESC92C_RATEMCS11                       0x17
  50 #define DESC92C_RATEMCS12                       0x18
  51 #define DESC92C_RATEMCS13                       0x19
  52 #define DESC92C_RATEMCS14                       0x1a
  53 #define DESC92C_RATEMCS15                       0x1b
  54 #define DESC92C_RATEMCS15_SG                    0x1c
  55 #define DESC92C_RATEMCS32                       0x20
  56
  57 /*  structure and define */
  58
  59 struct phy_rx_agc_info {
  60         #ifdef __LITTLE_ENDIAN
  61                 u8      gain:7, trsw:1;
  62         #else
  63                 u8      trsw:1, gain:7;
  64         #endif
  65 };
  66
  67 struct phy_status_rpt {
  68         struct phy_rx_agc_info path_agc[RF_PATH_MAX];
  69         u8      ch_corr[2];
  70         u8      cck_sig_qual_ofdm_pwdb_all;
  71         u8      cck_agc_rpt_ofdm_cfosho_a;
  72         u8      cck_rpt_b_ofdm_cfosho_b;
  73         u8      rsvd_1;/* ch_corr_msb; */
  74         u8      noise_power_db_msb;
  75         u8      path_cfotail[2];
  76         u8      pcts_mask[2];
  77         s8      stream_rxevm[2];
  78         u8      path_rxsnr[3];
  79         u8      noise_power_db_lsb;
  80         u8      rsvd_2[3];
  81         u8      stream_csi[2];
  82         u8      stream_target_csi[2];
  83         s8      sig_evm;
  84         u8      rsvd_3;
  85
  86 #ifdef __LITTLE_ENDIAN
  87         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
  88         u8      sgi_en:1;
  89         u8      rxsc:2;
  90         u8      idle_long:1;
  91         u8      r_ant_train_en:1;
  92         u8      ant_sel_b:1;
  93         u8      ant_sel:1;
  94 #else   /*  _BIG_ENDIAN_ */
  95         u8      ant_sel:1;
  96         u8      ant_sel_b:1;
  97         u8      r_ant_train_en:1;
  98         u8      idle_long:1;
  99         u8      rxsc:2;
 100         u8      sgi_en:1;
 101         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
 102 #endif
 103 };
 104
 105 void odm_Init_RSSIForDM(struct odm_dm_struct *pDM_Odm);
 106
 107 void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm,
 108                         struct odm_phy_status_info *pPhyInfo,
 109                         u8 *pPhyStatus,
 110                         struct odm_per_pkt_info *pPktinfo);
 111
 112 void ODM_MacStatusQuery(struct odm_dm_struct *pDM_Odm,
 113                         u8 *pMacStatus,
 114                         u8      MacID,
 115                         bool    bPacketMatchBSSID,
 116                         bool    bPacketToSelf,
 117                         bool    bPacketBeacon);
 118
 119 #endif