drivers/staging/rtl8188eu/include/odm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7
   8 #ifndef __HALDMOUTSRC_H__
   9 #define __HALDMOUTSRC_H__
  10
  11 /*  Definition */
  12 /*  Define all team support ability. */
  13
  14 /*  Define for all teams. Please Define the constant in your precomp header. */
  15
  16 /* define               DM_ODM_SUPPORT_AP                       0 */
  17 /* define               DM_ODM_SUPPORT_ADSL                     0 */
  18 /* define               DM_ODM_SUPPORT_CE                       0 */
  19 /* define               DM_ODM_SUPPORT_MP                       1 */
  20
  21 /*  Define ODM SW team support flag. */
  22
  23 /*  Antenna Switch Relative Definition. */
  24
  25 /*  Add new function SwAntDivCheck8192C(). */
  26 /*  This is the main function of Antenna diversity function before link. */
  27 /*  Mainly, it just retains last scan result and scan again. */
  28 /*  After that, it compares the scan result to see which one gets better
  29  *  RSSI. It selects antenna with better receiving power and returns better
  30  *  scan result.
  31  */
  32
  33 #define TP_MODE                 0
  34 #define RSSI_MODE               1
  35 #define TRAFFIC_LOW             0
  36 #define TRAFFIC_HIGH            1
  37
  38 /* 3 Tx Power Tracking */
  39 /* 3============================================================ */
  40 #define         DPK_DELTA_MAPPING_NUM   13
  41 #define         index_mapping_HP_NUM    15
  42
  43 /*  */
  44 /* 3 PSD Handler */
  45 /* 3============================================================ */
  46
  47 #define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  48 #define MODE_40M        0       /* 0:20M, 1:40M */
  49 #define PSD_TH2         3
  50 #define PSD_CHM         20   /*  Minimum channel number for BT AFH */
  51 #define SIR_STEP_SIZE   3
  52 #define Smooth_Size_1   5
  53 #define Smooth_TH_1     3
  54 #define Smooth_Size_2   10
  55 #define Smooth_TH_2     4
  56 #define Smooth_Size_3   20
  57 #define Smooth_TH_3     4
  58 #define Smooth_Step_Size 5
  59 #define Adaptive_SIR    1
  60 #define PSD_RESCAN      4
  61 #define PSD_SCAN_INTERVAL       700 /* ms */
  62
  63 /* 8723A High Power IGI Setting */
  64 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  65 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  66 #define DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  67
  68 /*  LPS define */
  69 #define DM_DIG_FA_TH0_LPS               4 /*  4 in lps */
  70 #define DM_DIG_FA_TH1_LPS               15 /*  15 lps */
  71 #define DM_DIG_FA_TH2_LPS               30 /*  30 lps */
  72 #define RSSI_OFFSET_DIG                 0x05;
  73
  74 struct rtw_dig {
  75         u8              Dig_Enable_Flag;
  76         u8              Dig_Ext_Port_Stage;
  77
  78         int             RssiLowThresh;
  79         int             RssiHighThresh;
  80
  81         u32             FALowThresh;
  82         u32             FAHighThresh;
  83
  84         u8              CurSTAConnectState;
  85         u8              PreSTAConnectState;
  86         u8              CurMultiSTAConnectState;
  87
  88         u8              PreIGValue;
  89         u8              CurIGValue;
  90         u8              BackupIGValue;
  91
  92         s8              BackoffVal;
  93         s8              BackoffVal_range_max;
  94         s8              BackoffVal_range_min;
  95         u8              rx_gain_range_max;
  96         u8              rx_gain_range_min;
  97         u8              Rssi_val_min;
  98
  99         u8              PreCCK_CCAThres;
 100         u8              CurCCK_CCAThres;
 101         u8              PreCCKPDState;
 102         u8              CurCCKPDState;
 103
 104         u8              LargeFAHit;
 105         u8              ForbiddenIGI;
 106         u32             Recover_cnt;
 107
 108         u8              DIG_Dynamic_MIN_0;
 109         u8              DIG_Dynamic_MIN_1;
 110         bool            bMediaConnect_0;
 111         bool            bMediaConnect_1;
 112
 113         u32             AntDiv_RSSI_max;
 114         u32             RSSI_max;
 115 };
 116
 117 struct rtl_ps {
 118         u8              PreCCAState;
 119         u8              CurCCAState;
 120
 121         u8              PreRFState;
 122         u8              CurRFState;
 123
 124         int                 Rssi_val_min;
 125
 126         u8              initialize;
 127         u32             Reg874, RegC70, Reg85C, RegA74;
 128
 129 };
 130
 131 struct false_alarm_stats {
 132         u32     Cnt_Parity_Fail;
 133         u32     Cnt_Rate_Illegal;
 134         u32     Cnt_Crc8_fail;
 135         u32     Cnt_Mcs_fail;
 136         u32     Cnt_Ofdm_fail;
 137         u32     Cnt_Cck_fail;
 138         u32     Cnt_all;
 139         u32     Cnt_Fast_Fsync;
 140         u32     Cnt_SB_Search_fail;
 141         u32     Cnt_OFDM_CCA;
 142         u32     Cnt_CCK_CCA;
 143         u32     Cnt_CCA_all;
 144         u32     Cnt_BW_USC;     /* Gary */
 145         u32     Cnt_BW_LSC;     /* Gary */
 146 };
 147
 148 struct rx_hpc {
 149         u8              RXHP_flag;
 150         u8              PSD_func_trigger;
 151         u8              PSD_bitmap_RXHP[80];
 152         u8              Pre_IGI;
 153         u8              Cur_IGI;
 154         u8              Pre_pw_th;
 155         u8              Cur_pw_th;
 156         bool            First_time_enter;
 157         bool            RXHP_enable;
 158         u8              TP_Mode;
 159         struct timer_list PSDTimer;
 160 };
 161
 162 #define ASSOCIATE_ENTRY_NUM     32 /*  Max size of AsocEntry[]. */
 163 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
 164
 165 /*  This indicates two different steps. */
 166 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
 167  *  the signal on the air.
 168  */
 169 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
 170  *  SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
 171  *  switch antenna.
 172  */
 173
 174 #define SWAW_STEP_PEAK          0
 175 #define SWAW_STEP_DETERMINE     1
 176
 177 #define TP_MODE                 0
 178 #define RSSI_MODE               1
 179 #define TRAFFIC_LOW             0
 180 #define TRAFFIC_HIGH            1
 181
 182 struct sw_ant_switch {
 183         u8      try_flag;
 184         s32     PreRSSI;
 185         u8      CurAntenna;
 186         u8      PreAntenna;
 187         u8      RSSI_Trying;
 188         u8      TestMode;
 189         u8      bTriggerAntennaSwitch;
 190         u8      SelectAntennaMap;
 191         u8      RSSI_target;
 192
 193         /*  Before link Antenna Switch check */
 194         u8      SWAS_NoLink_State;
 195         u32     SWAS_NoLink_BK_Reg860;
 196         bool    ANTA_ON;        /* To indicate Ant A is or not */
 197         bool    ANTB_ON;        /* To indicate Ant B is on or not */
 198
 199         s32     RSSI_sum_A;
 200         s32     RSSI_sum_B;
 201         s32     RSSI_cnt_A;
 202         s32     RSSI_cnt_B;
 203         u64     lastTxOkCnt;
 204         u64     lastRxOkCnt;
 205         u64     TXByteCnt_A;
 206         u64     TXByteCnt_B;
 207         u64     RXByteCnt_A;
 208         u64     RXByteCnt_B;
 209         u8      TrafficLoad;
 210         struct timer_list SwAntennaSwitchTimer;
 211         /* Hybrid Antenna Diversity */
 212         u32     CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 213         u32     CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 214         u32     OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 215         u32     OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 216         u32     RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
 217         u32     RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
 218         u8      TxAnt[ASSOCIATE_ENTRY_NUM];
 219         u8      TargetSTA;
 220         u8      antsel;
 221         u8      RxIdleAnt;
 222 };
 223
 224 struct edca_turbo {
 225         bool bCurrentTurboEDCA;
 226         bool bIsCurRDLState;
 227         u32     prv_traffic_idx; /*  edca turbo */
 228 };
 229
 230 struct odm_rate_adapt {
 231         u8      Type;           /*  DM_Type_ByFW/DM_Type_ByDriver */
 232         u8      HighRSSIThresh; /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 233         u8      LowRSSIThresh;  /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 234         u8      RATRState;      /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 235         u32     LastRATR;       /*  RATR Register Content */
 236 };
 237
 238 #define IQK_MAC_REG_NUM         4
 239 #define IQK_ADDA_REG_NUM        16
 240 #define IQK_BB_REG_NUM          9
 241 #define HP_THERMAL_NUM          8
 242
 243 #define AVG_THERMAL_NUM         8
 244 #define IQK_Matrix_REG_NUM      8
 245 #define IQK_Matrix_Settings_NUM (1 + 24 + 21)
 246
 247 #define DM_Type_ByFWi           0
 248 #define DM_Type_ByDriver        1
 249
 250 /*  Declare for common info */
 251
 252 struct odm_phy_status_info {
 253         u8      RxPWDBAll;
 254         u8      SignalQuality;   /*  in 0-100 index. */
 255         u8      RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
 256         u8      RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/*  in 0~100 index */
 257         s8      RxPower; /*  in dBm Translate from PWdB */
 258         s8      RecvSignalPower;/*  Real power in dBm for this packet, no
 259                                  * beautification and aggregation. Keep this raw
 260                                  * info to be used for the other procedures.
 261                                  */
 262         u8      BTRxRSSIPercentage;
 263         u8      SignalStrength; /*  in 0-100 index. */
 264         u8      RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
 265         u8      RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
 266 };
 267
 268 struct odm_phy_dbg_info {
 269         /* ODM Write,debug info */
 270         s8      RxSNRdB[MAX_PATH_NUM_92CS];
 271         u64     NumQryPhyStatus;
 272         u64     NumQryPhyStatusCCK;
 273         u64     NumQryPhyStatusOFDM;
 274         /* Others */
 275         s32     RxEVM[MAX_PATH_NUM_92CS];
 276 };
 277
 278 struct odm_per_pkt_info {
 279         s8      Rate;
 280         u8      StationID;
 281         bool    bPacketMatchBSSID;
 282         bool    bPacketToSelf;
 283         bool    bPacketBeacon;
 284 };
 285
 286 struct odm_mac_status_info {
 287         u8      test;
 288 };
 289
 290 enum odm_ability {
 291         /*  BB Team */
 292         ODM_DIG                 = 0x00000001,
 293         ODM_HIGH_POWER          = 0x00000002,
 294         ODM_CCK_CCA_TH          = 0x00000004,
 295         ODM_FA_STATISTICS       = 0x00000008,
 296         ODM_RAMASK              = 0x00000010,
 297         ODM_RSSI_MONITOR        = 0x00000020,
 298         ODM_SW_ANTDIV           = 0x00000040,
 299         ODM_HW_ANTDIV           = 0x00000080,
 300         ODM_BB_PWRSV            = 0x00000100,
 301         ODM_2TPATHDIV           = 0x00000200,
 302         ODM_1TPATHDIV           = 0x00000400,
 303         ODM_PSD2AFH             = 0x00000800
 304 };
 305
 306 /*  2011/10/20 MH Define Common info enum for all team. */
 307
 308 enum odm_common_info_def {
 309         /*  Fixed value: */
 310
 311         /* HOOK BEFORE REG INIT----------- */
 312         ODM_CMNINFO_PLATFORM = 0,
 313         ODM_CMNINFO_ABILITY,            /* ODM_ABILITY_E */
 314         ODM_CMNINFO_INTERFACE,          /* ODM_INTERFACE_E */
 315         ODM_CMNINFO_MP_TEST_CHIP,
 316         ODM_CMNINFO_IC_TYPE,            /* ODM_IC_TYPE_E */
 317         ODM_CMNINFO_CUT_VER,            /* ODM_CUT_VERSION_E */
 318         ODM_CMNINFO_RF_TYPE,            /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
 319         ODM_CMNINFO_BOARD_TYPE,         /* ODM_BOARD_TYPE_E */
 320         ODM_CMNINFO_EXT_LNA,            /* true */
 321         ODM_CMNINFO_EXT_PA,
 322         ODM_CMNINFO_EXT_TRSW,
 323         ODM_CMNINFO_PATCH_ID,           /* CUSTOMER ID */
 324         ODM_CMNINFO_BINHCT_TEST,
 325         ODM_CMNINFO_BWIFI_TEST,
 326         ODM_CMNINFO_SMART_CONCURRENT,
 327         /* HOOK BEFORE REG INIT-----------  */
 328
 329         /*  Dynamic value: */
 330 /*  POINTER REFERENCE-----------  */
 331         ODM_CMNINFO_MAC_PHY_MODE,       /*  ODM_MAC_PHY_MODE_E */
 332         ODM_CMNINFO_TX_UNI,
 333         ODM_CMNINFO_RX_UNI,
 334         ODM_CMNINFO_WM_MODE,            /*  ODM_WIRELESS_MODE_E */
 335         ODM_CMNINFO_BAND,               /*  ODM_BAND_TYPE_E */
 336         ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
 337         ODM_CMNINFO_SEC_MODE,           /*  ODM_SECURITY_E */
 338         ODM_CMNINFO_BW,                 /*  ODM_BW_E */
 339         ODM_CMNINFO_CHNL,
 340
 341         ODM_CMNINFO_DMSP_GET_VALUE,
 342         ODM_CMNINFO_BUDDY_ADAPTOR,
 343         ODM_CMNINFO_DMSP_IS_MASTER,
 344         ODM_CMNINFO_SCAN,
 345         ODM_CMNINFO_POWER_SAVING,
 346         ODM_CMNINFO_ONE_PATH_CCA,       /*  ODM_CCA_PATH_E */
 347         ODM_CMNINFO_DRV_STOP,
 348         ODM_CMNINFO_PNP_IN,
 349         ODM_CMNINFO_INIT_ON,
 350         ODM_CMNINFO_ANT_TEST,
 351         ODM_CMNINFO_NET_CLOSED,
 352         ODM_CMNINFO_MP_MODE,
 353 /*  POINTER REFERENCE----------- */
 354
 355 /* CALL BY VALUE------------- */
 356         ODM_CMNINFO_WIFI_DIRECT,
 357         ODM_CMNINFO_WIFI_DISPLAY,
 358         ODM_CMNINFO_LINK,
 359         ODM_CMNINFO_RSSI_MIN,
 360         ODM_CMNINFO_DBG_COMP,                   /*  u64 */
 361         ODM_CMNINFO_DBG_LEVEL,                  /*  u32 */
 362         ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 363         ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 364         ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 365         ODM_CMNINFO_BT_DISABLED,
 366         ODM_CMNINFO_BT_OPERATION,
 367         ODM_CMNINFO_BT_DIG,
 368         ODM_CMNINFO_BT_BUSY,                    /* Check Bt is using or not */
 369         ODM_CMNINFO_BT_DISABLE_EDCA,
 370 /* CALL BY VALUE-------------*/
 371
 372         /*  Dynamic ptr array hook itms. */
 373         ODM_CMNINFO_STA_STATUS,
 374         ODM_CMNINFO_PHY_STATUS,
 375         ODM_CMNINFO_MAC_STATUS,
 376         ODM_CMNINFO_MAX,
 377 };
 378
 379 /*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
 380
 381 enum odm_ability_def {
 382         /*  BB ODM section BIT 0-15 */
 383         ODM_BB_DIG                      = BIT(0),
 384         ODM_BB_RA_MASK                  = BIT(1),
 385         ODM_BB_DYNAMIC_TXPWR            = BIT(2),
 386         ODM_BB_FA_CNT                   = BIT(3),
 387         ODM_BB_RSSI_MONITOR             = BIT(4),
 388         ODM_BB_CCK_PD                   = BIT(5),
 389         ODM_BB_ANT_DIV                  = BIT(6),
 390         ODM_BB_PWR_SAVE                 = BIT(7),
 391         ODM_BB_PWR_TRA                  = BIT(8),
 392         ODM_BB_RATE_ADAPTIVE            = BIT(9),
 393         ODM_BB_PATH_DIV                 = BIT(10),
 394         ODM_BB_PSD                      = BIT(11),
 395         ODM_BB_RXHP                     = BIT(12),
 396
 397         /*  MAC DM section BIT 16-23 */
 398         ODM_MAC_EDCA_TURBO              = BIT(16),
 399         ODM_MAC_EARLY_MODE              = BIT(17),
 400
 401         /*  RF ODM section BIT 24-31 */
 402         ODM_RF_TX_PWR_TRACK             = BIT(24),
 403         ODM_RF_RX_GAIN_TRACK            = BIT(25),
 404         ODM_RF_CALIBRATION              = BIT(26),
 405 };
 406
 407 #define ODM_RTL8188E            BIT(4)
 408
 409 /* ODM_CMNINFO_CUT_VER */
 410 enum odm_cut_version {
 411         ODM_CUT_A       =       1,
 412         ODM_CUT_B       =       2,
 413         ODM_CUT_C       =       3,
 414         ODM_CUT_D       =       4,
 415         ODM_CUT_E       =       5,
 416         ODM_CUT_F       =       6,
 417         ODM_CUT_TEST    =       7,
 418 };
 419
 420 /*  ODM_CMNINFO_RF_TYPE */
 421 /*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
 422 enum odm_rf_path {
 423         ODM_RF_TX_A     =       BIT(0),
 424         ODM_RF_TX_B     =       BIT(1),
 425         ODM_RF_TX_C     =       BIT(2),
 426         ODM_RF_TX_D     =       BIT(3),
 427         ODM_RF_RX_A     =       BIT(4),
 428         ODM_RF_RX_B     =       BIT(5),
 429         ODM_RF_RX_C     =       BIT(6),
 430         ODM_RF_RX_D     =       BIT(7),
 431 };
 432
 433 enum odm_rf_type {
 434         ODM_1T1R        =       0,
 435         ODM_1T2R        =       1,
 436         ODM_2T2R        =       2,
 437         ODM_2T3R        =       3,
 438         ODM_2T4R        =       4,
 439         ODM_3T3R        =       5,
 440         ODM_3T4R        =       6,
 441         ODM_4T4R        =       7,
 442 };
 443
 444 /*  ODM Dynamic common info value definition */
 445
 446 enum odm_mac_phy_mode {
 447         ODM_SMSP        = 0,
 448         ODM_DMSP        = 1,
 449         ODM_DMDP        = 2,
 450 };
 451
 452 enum odm_bt_coexist {
 453         ODM_BT_BUSY             = 1,
 454         ODM_BT_ON               = 2,
 455         ODM_BT_OFF              = 3,
 456         ODM_BT_NONE             = 4,
 457 };
 458
 459 /*  ODM_CMNINFO_OP_MODE */
 460 enum odm_operation_mode {
 461         ODM_NO_LINK             = BIT(0),
 462         ODM_LINK                = BIT(1),
 463         ODM_SCAN                = BIT(2),
 464         ODM_POWERSAVE           = BIT(3),
 465         ODM_AP_MODE             = BIT(4),
 466         ODM_CLIENT_MODE         = BIT(5),
 467         ODM_AD_HOC              = BIT(6),
 468         ODM_WIFI_DIRECT         = BIT(7),
 469         ODM_WIFI_DISPLAY        = BIT(8),
 470 };
 471
 472 /*  ODM_CMNINFO_WM_MODE */
 473 enum odm_wireless_mode {
 474         ODM_WM_UNKNOWN  = 0x0,
 475         ODM_WM_B        = BIT(0),
 476         ODM_WM_G        = BIT(1),
 477         ODM_WM_A        = BIT(2),
 478         ODM_WM_N24G     = BIT(3),
 479         ODM_WM_N5G      = BIT(4),
 480         ODM_WM_AUTO     = BIT(5),
 481         ODM_WM_AC       = BIT(6),
 482 };
 483
 484 /*  ODM_CMNINFO_BAND */
 485 enum odm_band_type {
 486         ODM_BAND_2_4G   = BIT(0),
 487         ODM_BAND_5G     = BIT(1),
 488 };
 489
 490 /*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 491 enum odm_sec_chnl_offset {
 492         ODM_DONT_CARE   = 0,
 493         ODM_BELOW       = 1,
 494         ODM_ABOVE       = 2
 495 };
 496
 497 /*  ODM_CMNINFO_SEC_MODE */
 498 enum odm_security {
 499         ODM_SEC_OPEN            = 0,
 500         ODM_SEC_WEP40           = 1,
 501         ODM_SEC_TKIP            = 2,
 502         ODM_SEC_RESERVE         = 3,
 503         ODM_SEC_AESCCMP         = 4,
 504         ODM_SEC_WEP104          = 5,
 505         ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 506         ODM_SEC_SMS4            = 7,
 507 };
 508
 509 /*  ODM_CMNINFO_BW */
 510 enum odm_bw {
 511         ODM_BW20M               = 0,
 512         ODM_BW40M               = 1,
 513         ODM_BW80M               = 2,
 514         ODM_BW160M              = 3,
 515         ODM_BW10M               = 4,
 516 };
 517
 518 /*  ODM_CMNINFO_BOARD_TYPE */
 519 enum odm_board_type {
 520         ODM_BOARD_NORMAL        = 0,
 521         ODM_BOARD_HIGHPWR       = 1,
 522         ODM_BOARD_MINICARD      = 2,
 523         ODM_BOARD_SLIM          = 3,
 524         ODM_BOARD_COMBO         = 4,
 525 };
 526
 527 /*  ODM_CMNINFO_ONE_PATH_CCA */
 528 enum odm_cca_path {
 529         ODM_CCA_2R              = 0,
 530         ODM_CCA_1R_A            = 1,
 531         ODM_CCA_1R_B            = 2,
 532 };
 533
 534 struct odm_ra_info {
 535         u8 RateID;
 536         u32 RateMask;
 537         u32 RAUseRate;
 538         u8 RateSGI;
 539         u8 RssiStaRA;
 540         u8 PreRssiStaRA;
 541         u8 SGIEnable;
 542         u8 DecisionRate;
 543         u8 PreRate;
 544         u8 HighestRate;
 545         u8 LowestRate;
 546         u32 NscUp;
 547         u32 NscDown;
 548         u16 RTY[5];
 549         u32 TOTAL;
 550         u16 DROP;
 551         u8 Active;
 552         u16 RptTime;
 553         u8 RAWaitingCounter;
 554         u8 RAPendingCounter;
 555         u8 PTActive;    /*  on or off */
 556         u8 PTTryState;  /*  0 trying state, 1 for decision state */
 557         u8 PTStage;     /*  0~6 */
 558         u8 PTStopCount; /* Stop PT counter */
 559         u8 PTPreRate;   /*  if rate change do PT */
 560         u8 PTPreRssi;   /*  if RSSI change 5% do PT */
 561         u8 PTModeSS;    /*  decide whitch rate should do PT */
 562         u8 RAstage;     /*  StageRA, decide how many times RA will be done
 563                          * between PT
 564                          */
 565         u8 PTSmoothFactor;
 566 };
 567
 568 struct ijk_matrix_regs_set {
 569         bool    bIQKDone;
 570         s32     Value[1][IQK_Matrix_REG_NUM];
 571 };
 572
 573 struct odm_rf_cal {
 574         /* for tx power tracking */
 575         u32     RegA24; /*  for TempCCK */
 576         s32     RegE94;
 577         s32     RegE9C;
 578         s32     RegEB4;
 579         s32     RegEBC;
 580
 581         u8      TXPowercount;
 582         bool    bTXPowerTracking;
 583         u8      TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
 584                                       * as default
 585                                       */
 586         u8      TM_Trigger;
 587         u8      InternalPA5G[2];        /* pathA / pathB */
 588
 589         u8      ThermalMeter[2];    /* ThermalMeter, index 0 for RFIC0,
 590                                      * and 1 for RFIC1
 591                                      */
 592         u8      ThermalValue;
 593         u8      ThermalValue_LCK;
 594         u8      ThermalValue_IQK;
 595         u8      ThermalValue_DPK;
 596         u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 597         u8      ThermalValue_AVG_index;
 598         u8      ThermalValue_RxGain;
 599         u8      ThermalValue_Crystal;
 600         u8      ThermalValue_DPKstore;
 601         u8      ThermalValue_DPKtrack;
 602         bool    TxPowerTrackingInProgress;
 603         bool    bDPKenable;
 604
 605         bool    bReloadtxpowerindex;
 606         u8      bRfPiEnable;
 607         u32     TXPowerTrackingCallbackCnt; /* cosa add for debug */
 608
 609         u8      bCCKinCH14;
 610         u8      CCK_index;
 611         u8      OFDM_index[2];
 612         bool bDoneTxpower;
 613
 614         u8      ThermalValue_HP[HP_THERMAL_NUM];
 615         u8      ThermalValue_HP_index;
 616         struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 617
 618         u8      Delta_IQK;
 619         u8      Delta_LCK;
 620
 621         /* for IQK */
 622         u32     RegC04;
 623         u32     Reg874;
 624         u32     RegC08;
 625         u32     RegB68;
 626         u32     RegB6C;
 627         u32     Reg870;
 628         u32     Reg860;
 629         u32     Reg864;
 630
 631         bool    bIQKInitialized;
 632         bool    bLCKInProgress;
 633         bool    bAntennaDetected;
 634         u32     ADDA_backup[IQK_ADDA_REG_NUM];
 635         u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 636         u32     IQK_BB_backup_recover[9];
 637         u32     IQK_BB_backup[IQK_BB_REG_NUM];
 638
 639         /* for APK */
 640         u32     APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 641         u8      bAPKdone;
 642         u8      bAPKThermalMeterIgnore;
 643         u8      bDPdone;
 644         u8      bDPPathAOK;
 645         u8      bDPPathBOK;
 646 };
 647
 648 /*  ODM Dynamic common info value definition */
 649
 650 struct fast_ant_train {
 651         u8      Bssid[6];
 652         u8      antsel_rx_keep_0;
 653         u8      antsel_rx_keep_1;
 654         u8      antsel_rx_keep_2;
 655         u32     antSumRSSI[7];
 656         u32     antRSSIcnt[7];
 657         u32     antAveRSSI[7];
 658         u8      FAT_State;
 659         u32     TrainIdx;
 660         u8      antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 661         u8      antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 662         u8      antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 663         u32     MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 664         u32     AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 665         u32     MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 666         u32     AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 667         u8      RxIdleAnt;
 668         bool    bBecomeLinked;
 669 };
 670
 671 enum fat_state {
 672         FAT_NORMAL_STATE                = 0,
 673         FAT_TRAINING_STATE              = 1,
 674 };
 675
 676 enum ant_div_type {
 677         NO_ANTDIV                       = 0xFF,
 678         CG_TRX_HW_ANTDIV                = 0x01,
 679         CGCS_RX_HW_ANTDIV               = 0x02,
 680         FIXED_HW_ANTDIV                 = 0x03,
 681         CG_TRX_SMART_ANTDIV             = 0x04,
 682         CGCS_RX_SW_ANTDIV               = 0x05,
 683 };
 684
 685 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
 686 struct odm_dm_struct {
 687         /*      Add for different team use temporarily */
 688         struct adapter *Adapter;        /*  For CE/NIC team */
 689         struct rtl8192cd_priv *priv;    /*  For AP/ADSL team */
 690         /*  WHen you use above pointers, they must be initialized. */
 691         bool    odm_ready;
 692
 693         struct rtl8192cd_priv *fake_priv;
 694         u64     DebugComponents;
 695         u32     DebugLevel;
 696
 697 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 698         bool    bCckHighPower;
 699         u8      RFPathRxEnable;         /*  ODM_CMNINFO_RFPATH_ENABLE */
 700         u8      ControlChannel;
 701 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 702
 703 /* 1  COMMON INFORMATION */
 704         /*  Init Value */
 705 /* HOOK BEFORE REG INIT----------- */
 706         /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
 707         u8      SupportPlatform;
 708         /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */
 709         u32     SupportAbility;
 710         /*  ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
 711         u8      SupportInterface;
 712         /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
 713          *  other type = 1/2/3/...
 714          */
 715         u32     SupportICType;
 716         /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 717         u8      CutVersion;
 718         /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
 719         u8      BoardType;
 720         /*  with external LNA  NO/Yes = 0/1 */
 721         u8      ExtLNA;
 722         /*  with external PA  NO/Yes = 0/1 */
 723         u8      ExtPA;
 724         /*  with external TRSW  NO/Yes = 0/1 */
 725         u8      ExtTRSW;
 726         u8      PatchID; /* Customer ID */
 727         bool    bInHctTest;
 728         bool    bWIFITest;
 729
 730         bool    bDualMacSmartConcurrent;
 731         u32     BK_SupportAbility;
 732         u8      AntDivType;
 733 /* HOOK BEFORE REG INIT----------- */
 734
 735         /*  Dynamic Value */
 736 /*  POINTER REFERENCE----------- */
 737
 738         u8      u8_temp;
 739         bool    bool_temp;
 740         struct adapter *adapter_temp;
 741
 742         /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 743         u8      *pMacPhyMode;
 744         /* TX Unicast byte count */
 745         u64     *pNumTxBytesUnicast;
 746         /* RX Unicast byte count */
 747         u64     *pNumRxBytesUnicast;
 748         /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
 749         u8      *pWirelessMode; /* ODM_WIRELESS_MODE_E */
 750         /*  Frequence band 2.4G/5G = 0/1 */
 751         u8      *pBandType;
 752         /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 753         u8      *pSecChOffset;
 754         /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 755         u8      *pSecurity;
 756         /*  BW info 20M/40M/80M = 0/1/2 */
 757         u8      *pBandWidth;
 758         /*  Central channel location Ch1/Ch2/.... */
 759         u8      *pChannel;      /* central channel number */
 760         /*  Common info for 92D DMSP */
 761
 762         bool    *pbGetValueFromOtherMac;
 763         struct adapter **pBuddyAdapter;
 764         bool    *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 765         /*  Common info for Status */
 766         bool    *pbScanInProcess;
 767         bool    *pbPowerSaving;
 768         /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
 769         u8      *pOnePathCCA;
 770         /* pMgntInfo->AntennaTest */
 771         u8      *pAntennaTest;
 772         bool    *pbNet_closed;
 773 /*  POINTER REFERENCE----------- */
 774         /*  */
 775 /* CALL BY VALUE------------- */
 776         bool    bWIFI_Direct;
 777         bool    bWIFI_Display;
 778         bool    bLinked;
 779         u8      RSSI_Min;
 780         u8      InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
 781         bool    bIsMPChip;
 782         bool    bOneEntryOnly;
 783         /*  Common info for BTDM */
 784         bool    bBtDisabled;    /*  BT is disabled */
 785         bool    bBtHsOperation; /*  BT HS mode is under progress */
 786         u8      btHsDigVal;     /*  use BT rssi to decide the DIG value */
 787         bool    bBtDisableEdcaTurbo;/* Under some condition, don't enable the
 788                                      * EDCA Turbo
 789                                      */
 790         bool    bBtBusy;                        /*  BT is busy. */
 791 /* CALL BY VALUE------------- */
 792
 793         /* 2 Define STA info. */
 794         /*  _ODM_STA_INFO */
 795         /*  For MP, we need to reduce one array pointer for default port.??*/
 796         struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
 797
 798         u16     CurrminRptTime;
 799         struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
 800                                                              * array index. STA MacID=0,
 801                                                              * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1}
 802                                                              */
 803         /*  */
 804         /*  2012/02/14 MH Add to share 88E ra with other SW team. */
 805         /*  We need to colelct all support abilit to a proper area. */
 806         /*  */
 807         bool    RaSupport88E;
 808
 809         /*  Define ........... */
 810
 811         /*  Latest packet phy info (ODM write) */
 812         struct odm_phy_dbg_info PhyDbgInfo;
 813
 814         /*  Latest packet phy info (ODM write) */
 815         struct odm_mac_status_info *pMacInfo;
 816
 817         /*  Different Team independt structure?? */
 818
 819         /* ODM Structure */
 820         struct fast_ant_train DM_FatTable;
 821         struct rtw_dig  DM_DigTable;
 822         struct rtl_ps   DM_PSTable;
 823         struct rx_hpc   DM_RXHP_Table;
 824         struct false_alarm_stats FalseAlmCnt;
 825         struct false_alarm_stats FlaseAlmCntBuddyAdapter;
 826         struct sw_ant_switch DM_SWAT_Table;
 827         bool            RSSI_test;
 828
 829         struct edca_turbo DM_EDCA_Table;
 830         u32             WMMEDCA_BE;
 831         /*  Copy from SD4 structure */
 832         /*  */
 833         /*  ================================================== */
 834         /*  */
 835
 836         bool    *pbDriverStopped;
 837         bool    *pbDriverIsGoingToPnpSetPowerSleep;
 838         bool    *pinit_adpt_in_progress;
 839
 840         /* PSD */
 841         bool    bUserAssignLevel;
 842         struct timer_list PSDTimer;
 843         u8      RSSI_BT;                        /* come from BT */
 844         bool    bPSDinProcess;
 845         bool    bDMInitialGainEnable;
 846
 847         /* for rate adaptive, in fact,  88c/92c fw will handle this */
 848         u8      bUseRAMask;
 849
 850         struct odm_rate_adapt RateAdaptive;
 851
 852         struct odm_rf_cal RFCalibrateInfo;
 853
 854         /*  TX power tracking */
 855         u8      BbSwingIdxOfdm;
 856         u8      BbSwingIdxOfdmCurrent;
 857         u8      BbSwingIdxOfdmBase;
 858         bool    BbSwingFlagOfdm;
 859         u8      BbSwingIdxCck;
 860         u8      BbSwingIdxCckCurrent;
 861         u8      BbSwingIdxCckBase;
 862         bool    BbSwingFlagCck;
 863         u8      *mp_mode;
 864         /*  ODM system resource. */
 865
 866         /*  ODM relative time. */
 867         struct timer_list PathDivSwitchTimer;
 868         /* 2011.09.27 add for Path Diversity */
 869         struct timer_list CCKPathDiversityTimer;
 870         struct timer_list FastAntTrainingTimer;
 871 };              /*  DM_Dynamic_Mechanism_Structure */
 872
 873 #define ODM_RF_PATH_MAX 3
 874
 875 enum ODM_RF_CONTENT {
 876         odm_radioa_txt = 0x1000,
 877         odm_radiob_txt = 0x1001,
 878         odm_radioc_txt = 0x1002,
 879         odm_radiod_txt = 0x1003
 880 };
 881
 882 /*  Status code */
 883 enum rt_status {
 884         RT_STATUS_SUCCESS,
 885         RT_STATUS_FAILURE,
 886         RT_STATUS_PENDING,
 887         RT_STATUS_RESOURCE,
 888         RT_STATUS_INVALID_CONTEXT,
 889         RT_STATUS_INVALID_PARAMETER,
 890         RT_STATUS_NOT_SUPPORT,
 891         RT_STATUS_OS_API_FAILED,
 892 };
 893
 894 /* 3=========================================================== */
 895 /* 3 DIG */
 896 /* 3=========================================================== */
 897
 898 enum dm_dig_op {
 899         RT_TYPE_THRESH_HIGH     = 0,
 900         RT_TYPE_THRESH_LOW      = 1,
 901         RT_TYPE_BACKOFF         = 2,
 902         RT_TYPE_RX_GAIN_MIN     = 3,
 903         RT_TYPE_RX_GAIN_MAX     = 4,
 904         RT_TYPE_ENABLE          = 5,
 905         RT_TYPE_DISABLE         = 6,
 906         DIG_OP_TYPE_MAX
 907 };
 908
 909 #define         DM_DIG_THRESH_HIGH      40
 910 #define         DM_DIG_THRESH_LOW       35
 911
 912 #define         DM_SCAN_RSSI_TH         0x14 /* scan return issue for LC */
 913
 914 #define         DM_false_ALARM_THRESH_LOW       400
 915 #define         DM_false_ALARM_THRESH_HIGH      1000
 916
 917 #define         DM_DIG_MAX_NIC                  0x4e
 918 #define         DM_DIG_MIN_NIC                  0x1e /* 0x22/0x1c */
 919
 920 #define         DM_DIG_MAX_AP                   0x32
 921 #define         DM_DIG_MIN_AP                   0x20
 922
 923 #define         DM_DIG_MAX_NIC_HP               0x46
 924 #define         DM_DIG_MIN_NIC_HP               0x2e
 925
 926 #define         DM_DIG_MAX_AP_HP                0x42
 927 #define         DM_DIG_MIN_AP_HP                0x30
 928
 929 /* vivi 92c&92d has different definition, 20110504 */
 930 /* this is for 92c */
 931 #define         DM_DIG_FA_TH0                   0x200/* 0x20 */
 932 #define         DM_DIG_FA_TH1                   0x300/* 0x100 */
 933 #define         DM_DIG_FA_TH2                   0x400/* 0x200 */
 934 /* this is for 92d */
 935 #define         DM_DIG_FA_TH0_92D               0x100
 936 #define         DM_DIG_FA_TH1_92D               0x400
 937 #define         DM_DIG_FA_TH2_92D               0x600
 938
 939 #define         DM_DIG_BACKOFF_MAX              12
 940 #define         DM_DIG_BACKOFF_MIN              -4
 941 #define         DM_DIG_BACKOFF_DEFAULT          10
 942
 943 /* 3=========================================================== */
 944 /* 3 AGC RX High Power Mode */
 945 /* 3=========================================================== */
 946 #define   LNA_Low_Gain_1                0x64
 947 #define   LNA_Low_Gain_2                0x5A
 948 #define   LNA_Low_Gain_3                0x58
 949
 950 #define   FA_RXHP_TH1                   5000
 951 #define   FA_RXHP_TH2                   1500
 952 #define   FA_RXHP_TH3                   800
 953 #define   FA_RXHP_TH4                   600
 954 #define   FA_RXHP_TH5                   500
 955
 956 /* 3=========================================================== */
 957 /* 3 EDCA */
 958 /* 3=========================================================== */
 959
 960 /* 3=========================================================== */
 961 /* 3 Dynamic Tx Power */
 962 /* 3=========================================================== */
 963 /* Dynamic Tx Power Control Threshold */
 964 #define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
 965 #define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
 966 #define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F
 967
 968 #define         TxHighPwrLevel_Normal           0
 969 #define         TxHighPwrLevel_Level1           1
 970 #define         TxHighPwrLevel_Level2           2
 971 #define         TxHighPwrLevel_BT1              3
 972 #define         TxHighPwrLevel_BT2              4
 973 #define         TxHighPwrLevel_15               5
 974 #define         TxHighPwrLevel_35               6
 975 #define         TxHighPwrLevel_50               7
 976 #define         TxHighPwrLevel_70               8
 977 #define         TxHighPwrLevel_100              9
 978
 979 /* 3=========================================================== */
 980 /* 3 Rate Adaptive */
 981 /* 3=========================================================== */
 982 #define         DM_RATR_STA_INIT                0
 983 #define         DM_RATR_STA_HIGH                1
 984 #define         DM_RATR_STA_MIDDLE              2
 985 #define         DM_RATR_STA_LOW                 3
 986
 987 /* 3=========================================================== */
 988 /* 3 BB Power Save */
 989 /* 3=========================================================== */
 990
 991 enum dm_1r_cca {
 992         CCA_1R = 0,
 993         CCA_2R = 1,
 994         CCA_MAX = 2,
 995 };
 996
 997 enum dm_rf {
 998         RF_Save = 0,
 999         RF_Normal = 1,
1000         RF_MAX = 2,
1001 };
1002
1003 /* 3=========================================================== */
1004 /* 3 Antenna Diversity */
1005 /* 3=========================================================== */
1006 enum dm_swas {
1007         Antenna_A = 1,
1008         Antenna_B = 2,
1009         Antenna_MAX = 3,
1010 };
1011
1012 /*  Maximal number of antenna detection mechanism needs to perform. */
1013 #define MAX_ANTENNA_DETECTION_CNT       10
1014
1015 /*  Extern Global Variables. */
1016 #define OFDM_TABLE_SIZE_92C     37
1017 #define OFDM_TABLE_SIZE_92D     43
1018 #define CCK_TABLE_SIZE          33
1019
1020 extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1021 extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1022 extern  u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1023
1024 /*  check Sta pointer valid or not */
1025 #define IS_STA_VALID(pSta)              (pSta)
1026 /*  20100514 Joseph: Add definition for antenna switching test after link. */
1027 /*  This indicates two different the steps. */
1028 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1029  *  signal on the air.
1030  */
1031 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1032  *  SWAW_STEP_PEAK
1033  */
1034 /*  with original RSSI to determine if it is necessary to switch antenna. */
1035 #define SWAW_STEP_PEAK          0
1036 #define SWAW_STEP_DETERMINE     1
1037
1038 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1039 #define dm_RF_Saving    ODM_RF_Saving
1040
1041 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1042 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1043 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1044 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1045                       bool bForceUpdate, u8 *pRATRState);
1046 u32 ConvertTo_dB(u32 Value);
1047 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1048                         u32 ra_mask, u8 rssi_level);
1049 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1050                      enum odm_common_info_def CmnInfo, u32 Value);
1051 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1052 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1053                      enum odm_common_info_def CmnInfo, void *pValue);
1054 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1055                              enum odm_common_info_def CmnInfo,
1056                              u16 Index, void *pValue);
1057 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1058 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1059 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1060
1061 #endif