1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
17 #ifndef __HALDMOUTSRC_H__
18 #define __HALDMOUTSRC_H__
21 /* Define all team support ability. */
23 /* Define for all teams. Please Define the constant in your precomp header. */
25 /* define DM_ODM_SUPPORT_AP 0 */
26 /* define DM_ODM_SUPPORT_ADSL 0 */
27 /* define DM_ODM_SUPPORT_CE 0 */
28 /* define DM_ODM_SUPPORT_MP 1 */
30 /* Define ODM SW team support flag. */
32 /* Antenna Switch Relative Definition. */
34 /* Add new function SwAntDivCheck8192C(). */
35 /* This is the main function of Antenna diversity function before link. */
36 /* Mainly, it just retains last scan result and scan again. */
37 /* After that, it compares the scan result to see which one gets better
38 * RSSI. It selects antenna with better receiving power and returns better
44 #define TRAFFIC_HIGH 1
46 /* 3 Tx Power Tracking */
47 /* 3============================================================ */
48 #define DPK_DELTA_MAPPING_NUM 13
49 #define index_mapping_HP_NUM 15
54 /* 3============================================================ */
56 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
57 #define MODE_40M 0 /* 0:20M, 1:40M */
59 #define PSD_CHM 20 /* Minimum channel number for BT AFH */
60 #define SIR_STEP_SIZE 3
61 #define Smooth_Size_1 5
63 #define Smooth_Size_2 10
65 #define Smooth_Size_3 20
67 #define Smooth_Step_Size 5
68 #define Adaptive_SIR 1
70 #define PSD_SCAN_INTERVAL 700 /* ms */
72 /* 8723A High Power IGI Setting */
73 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
74 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
75 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
78 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
79 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
80 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
81 #define RSSI_OFFSET_DIG 0x05;
85 u8 Dig_Ext_Port_Stage;
93 u8 CurSTAConnectState;
94 u8 PreSTAConnectState;
95 u8 CurMultiSTAConnectState;
102 s8 BackoffVal_range_max;
103 s8 BackoffVal_range_min;
104 u8 rx_gain_range_max;
105 u8 rx_gain_range_min;
117 u8 DIG_Dynamic_MIN_0;
118 u8 DIG_Dynamic_MIN_1;
119 bool bMediaConnect_0;
120 bool bMediaConnect_1;
136 u32 Reg874, RegC70, Reg85C, RegA74;
140 struct false_alarm_stats {
142 u32 Cnt_Rate_Illegal;
149 u32 Cnt_SB_Search_fail;
153 u32 Cnt_BW_USC; /* Gary */
154 u32 Cnt_BW_LSC; /* Gary */
160 u8 PSD_bitmap_RXHP[80];
165 bool First_time_enter;
168 struct timer_list PSDTimer;
171 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
172 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
174 /* This indicates two different steps. */
175 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
176 * the signal on the air. */
177 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
178 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
181 #define SWAW_STEP_PEAK 0
182 #define SWAW_STEP_DETERMINE 1
186 #define TRAFFIC_LOW 0
187 #define TRAFFIC_HIGH 1
189 struct sw_ant_switch {
196 u8 bTriggerAntennaSwitch;
200 /* Before link Antenna Switch check */
201 u8 SWAS_NoLink_State;
202 u32 SWAS_NoLink_BK_Reg860;
203 bool ANTA_ON; /* To indicate Ant A is or not */
204 bool ANTB_ON; /* To indicate Ant B is on or not */
217 struct timer_list SwAntennaSwitchTimer;
218 /* Hybrid Antenna Diversity */
219 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
220 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
221 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
222 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
223 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
224 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
225 u8 TxAnt[ASSOCIATE_ENTRY_NUM];
232 bool bCurrentTurboEDCA;
234 u32 prv_traffic_idx; /* edca turbo */
237 struct odm_rate_adapt {
238 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
239 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
240 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
241 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
242 u32 LastRATR; /* RATR Register Content */
245 #define IQK_MAC_REG_NUM 4
246 #define IQK_ADDA_REG_NUM 16
247 #define IQK_BB_REG_NUM_MAX 10
248 #define IQK_BB_REG_NUM 9
249 #define HP_THERMAL_NUM 8
251 #define AVG_THERMAL_NUM 8
252 #define IQK_Matrix_REG_NUM 8
253 #define IQK_Matrix_Settings_NUM 1+24+21
255 #define DM_Type_ByFWi 0
256 #define DM_Type_ByDriver 1
258 /* Declare for common info */
260 struct odm_phy_status_info {
262 u8 SignalQuality; /* in 0-100 index. */
263 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
264 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
265 s8 RxPower; /* in dBm Translate from PWdB */
266 s8 RecvSignalPower;/* Real power in dBm for this packet, no
267 * beautification and aggregation. Keep this raw
268 * info to be used for the other procedures. */
269 u8 BTRxRSSIPercentage;
270 u8 SignalStrength; /* in 0-100 index. */
271 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
272 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
275 struct odm_phy_dbg_info {
276 /* ODM Write,debug info */
277 s8 RxSNRdB[MAX_PATH_NUM_92CS];
279 u64 NumQryPhyStatusCCK;
280 u64 NumQryPhyStatusOFDM;
282 s32 RxEVM[MAX_PATH_NUM_92CS];
285 struct odm_per_pkt_info {
288 bool bPacketMatchBSSID;
293 struct odm_mac_status_info {
299 ODM_DIG = 0x00000001,
300 ODM_HIGH_POWER = 0x00000002,
301 ODM_CCK_CCA_TH = 0x00000004,
302 ODM_FA_STATISTICS = 0x00000008,
303 ODM_RAMASK = 0x00000010,
304 ODM_RSSI_MONITOR = 0x00000020,
305 ODM_SW_ANTDIV = 0x00000040,
306 ODM_HW_ANTDIV = 0x00000080,
307 ODM_BB_PWRSV = 0x00000100,
308 ODM_2TPATHDIV = 0x00000200,
309 ODM_1TPATHDIV = 0x00000400,
310 ODM_PSD2AFH = 0x00000800
313 /* 2011/10/20 MH Define Common info enum for all team. */
315 enum odm_common_info_def {
318 /* HOOK BEFORE REG INIT----------- */
319 ODM_CMNINFO_PLATFORM = 0,
320 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
321 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
322 ODM_CMNINFO_MP_TEST_CHIP,
323 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
324 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
325 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
326 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
327 ODM_CMNINFO_EXT_LNA, /* true */
329 ODM_CMNINFO_EXT_TRSW,
330 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
331 ODM_CMNINFO_BINHCT_TEST,
332 ODM_CMNINFO_BWIFI_TEST,
333 ODM_CMNINFO_SMART_CONCURRENT,
334 /* HOOK BEFORE REG INIT----------- */
337 /* POINTER REFERENCE----------- */
338 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
341 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
342 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
343 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
344 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
345 ODM_CMNINFO_BW, /* ODM_BW_E */
348 ODM_CMNINFO_DMSP_GET_VALUE,
349 ODM_CMNINFO_BUDDY_ADAPTOR,
350 ODM_CMNINFO_DMSP_IS_MASTER,
352 ODM_CMNINFO_POWER_SAVING,
353 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
354 ODM_CMNINFO_DRV_STOP,
357 ODM_CMNINFO_ANT_TEST,
358 ODM_CMNINFO_NET_CLOSED,
360 /* POINTER REFERENCE----------- */
362 /* CALL BY VALUE------------- */
363 ODM_CMNINFO_WIFI_DIRECT,
364 ODM_CMNINFO_WIFI_DISPLAY,
366 ODM_CMNINFO_RSSI_MIN,
367 ODM_CMNINFO_DBG_COMP, /* u64 */
368 ODM_CMNINFO_DBG_LEVEL, /* u32 */
369 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
370 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
371 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
372 ODM_CMNINFO_BT_DISABLED,
373 ODM_CMNINFO_BT_OPERATION,
375 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
376 ODM_CMNINFO_BT_DISABLE_EDCA,
377 /* CALL BY VALUE-------------*/
379 /* Dynamic ptr array hook itms. */
380 ODM_CMNINFO_STA_STATUS,
381 ODM_CMNINFO_PHY_STATUS,
382 ODM_CMNINFO_MAC_STATUS,
386 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
388 enum odm_ability_def {
389 /* BB ODM section BIT 0-15 */
391 ODM_BB_RA_MASK = BIT(1),
392 ODM_BB_DYNAMIC_TXPWR = BIT(2),
393 ODM_BB_FA_CNT = BIT(3),
394 ODM_BB_RSSI_MONITOR = BIT(4),
395 ODM_BB_CCK_PD = BIT(5),
396 ODM_BB_ANT_DIV = BIT(6),
397 ODM_BB_PWR_SAVE = BIT(7),
398 ODM_BB_PWR_TRA = BIT(8),
399 ODM_BB_RATE_ADAPTIVE = BIT(9),
400 ODM_BB_PATH_DIV = BIT(10),
401 ODM_BB_PSD = BIT(11),
402 ODM_BB_RXHP = BIT(12),
404 /* MAC DM section BIT 16-23 */
405 ODM_MAC_EDCA_TURBO = BIT(16),
406 ODM_MAC_EARLY_MODE = BIT(17),
408 /* RF ODM section BIT 24-31 */
409 ODM_RF_TX_PWR_TRACK = BIT(24),
410 ODM_RF_RX_GAIN_TRACK = BIT(25),
411 ODM_RF_CALIBRATION = BIT(26),
414 #define ODM_RTL8188E BIT(4)
416 /* ODM_CMNINFO_CUT_VER */
417 enum odm_cut_version {
427 /* ODM_CMNINFO_RF_TYPE */
428 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
430 ODM_RF_TX_A = BIT(0),
431 ODM_RF_TX_B = BIT(1),
432 ODM_RF_TX_C = BIT(2),
433 ODM_RF_TX_D = BIT(3),
434 ODM_RF_RX_A = BIT(4),
435 ODM_RF_RX_B = BIT(5),
436 ODM_RF_RX_C = BIT(6),
437 ODM_RF_RX_D = BIT(7),
451 /* ODM Dynamic common info value definition */
453 enum odm_mac_phy_mode {
459 enum odm_bt_coexist {
466 /* ODM_CMNINFO_OP_MODE */
467 enum odm_operation_mode {
468 ODM_NO_LINK = BIT(0),
471 ODM_POWERSAVE = BIT(3),
472 ODM_AP_MODE = BIT(4),
473 ODM_CLIENT_MODE = BIT(5),
475 ODM_WIFI_DIRECT = BIT(7),
476 ODM_WIFI_DISPLAY = BIT(8),
479 /* ODM_CMNINFO_WM_MODE */
480 enum odm_wireless_mode {
485 ODM_WM_N24G = BIT(3),
487 ODM_WM_AUTO = BIT(5),
491 /* ODM_CMNINFO_BAND */
493 ODM_BAND_2_4G = BIT(0),
494 ODM_BAND_5G = BIT(1),
497 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
498 enum odm_sec_chnl_offset {
504 /* ODM_CMNINFO_SEC_MODE */
512 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
525 /* ODM_CMNINFO_BOARD_TYPE */
526 enum odm_board_type {
527 ODM_BOARD_NORMAL = 0,
528 ODM_BOARD_HIGHPWR = 1,
529 ODM_BOARD_MINICARD = 2,
534 /* ODM_CMNINFO_ONE_PATH_CCA */
562 u8 PTActive; /* on or off */
563 u8 PTTryState; /* 0 trying state, 1 for decision state */
564 u8 PTStage; /* 0~6 */
565 u8 PTStopCount; /* Stop PT counter */
566 u8 PTPreRate; /* if rate change do PT */
567 u8 PTPreRssi; /* if RSSI change 5% do PT */
568 u8 PTModeSS; /* decide whitch rate should do PT */
569 u8 RAstage; /* StageRA, decide how many times RA will be done
574 struct ijk_matrix_regs_set {
576 s32 Value[1][IQK_Matrix_REG_NUM];
580 /* for tx power tracking */
581 u32 RegA24; /* for TempCCK */
588 bool bTXPowerTracking;
589 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
592 u8 InternalPA5G[2]; /* pathA / pathB */
594 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
600 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
601 u8 ThermalValue_AVG_index;
602 u8 ThermalValue_RxGain;
603 u8 ThermalValue_Crystal;
604 u8 ThermalValue_DPKstore;
605 u8 ThermalValue_DPKtrack;
606 bool TxPowerTrackingInProgress;
609 bool bReloadtxpowerindex;
611 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
618 u8 ThermalValue_HP[HP_THERMAL_NUM];
619 u8 ThermalValue_HP_index;
620 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
635 bool bIQKInitialized;
637 bool bAntennaDetected;
638 u32 ADDA_backup[IQK_ADDA_REG_NUM];
639 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
640 u32 IQK_BB_backup_recover[9];
641 u32 IQK_BB_backup[IQK_BB_REG_NUM];
644 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
646 u8 bAPKThermalMeterIgnore;
652 /* ODM Dynamic common info value definition */
654 struct fast_ant_train {
664 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
665 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
666 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
667 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
668 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
669 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
670 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
676 FAT_NORMAL_STATE = 0,
677 FAT_TRAINING_STATE = 1,
682 CG_TRX_HW_ANTDIV = 0x01,
683 CGCS_RX_HW_ANTDIV = 0x02,
684 FIXED_HW_ANTDIV = 0x03,
685 CG_TRX_SMART_ANTDIV = 0x04,
686 CGCS_RX_SW_ANTDIV = 0x05,
689 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
690 struct odm_dm_struct {
691 /* Add for different team use temporarily */
692 struct adapter *Adapter; /* For CE/NIC team */
693 struct rtl8192cd_priv *priv; /* For AP/ADSL team */
694 /* WHen you use above pointers, they must be initialized. */
697 struct rtl8192cd_priv *fake_priv;
701 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
703 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
705 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
707 /* 1 COMMON INFORMATION */
709 /* HOOK BEFORE REG INIT----------- */
710 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
712 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
714 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
716 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
717 * other type = 1/2/3/... */
719 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
721 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
723 /* with external LNA NO/Yes = 0/1 */
725 /* with external PA NO/Yes = 0/1 */
727 /* with external TRSW NO/Yes = 0/1 */
729 u8 PatchID; /* Customer ID */
733 bool bDualMacSmartConcurrent;
734 u32 BK_SupportAbility;
736 /* HOOK BEFORE REG INIT----------- */
739 /* POINTER REFERENCE----------- */
743 struct adapter *adapter_temp;
745 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
747 /* TX Unicast byte count */
748 u64 *pNumTxBytesUnicast;
749 /* RX Unicast byte count */
750 u64 *pNumRxBytesUnicast;
751 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
752 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
753 /* Frequence band 2.4G/5G = 0/1 */
755 /* Secondary channel offset don't_care/below/above = 0/1/2 */
757 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
759 /* BW info 20M/40M/80M = 0/1/2 */
761 /* Central channel location Ch1/Ch2/.... */
762 u8 *pChannel; /* central channel number */
763 /* Common info for 92D DMSP */
765 bool *pbGetValueFromOtherMac;
766 struct adapter **pBuddyAdapter;
767 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
768 /* Common info for Status */
769 bool *pbScanInProcess;
771 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
773 /* pMgntInfo->AntennaTest */
776 /* POINTER REFERENCE----------- */
778 /* CALL BY VALUE------------- */
783 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
786 /* Common info for BTDM */
787 bool bBtDisabled; /* BT is disabled */
788 bool bBtHsOperation; /* BT HS mode is under progress */
789 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
790 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the
792 bool bBtBusy; /* BT is busy. */
793 /* CALL BY VALUE------------- */
795 /* 2 Define STA info. */
797 /* For MP, we need to reduce one array pointer for default port.?? */
798 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
801 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
802 * array index. STA MacID=0,
803 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
805 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
806 /* We need to colelct all support abilit to a proper area. */
810 /* Define ........... */
812 /* Latest packet phy info (ODM write) */
813 struct odm_phy_dbg_info PhyDbgInfo;
815 /* Latest packet phy info (ODM write) */
816 struct odm_mac_status_info *pMacInfo;
818 /* Different Team independt structure?? */
821 struct fast_ant_train DM_FatTable;
822 struct rtw_dig DM_DigTable;
823 struct rtl_ps DM_PSTable;
824 struct rx_hpc DM_RXHP_Table;
825 struct false_alarm_stats FalseAlmCnt;
826 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
827 struct sw_ant_switch DM_SWAT_Table;
830 struct edca_turbo DM_EDCA_Table;
832 /* Copy from SD4 structure */
834 /* ================================================== */
837 bool *pbDriverStopped;
838 bool *pbDriverIsGoingToPnpSetPowerSleep;
839 bool *pinit_adpt_in_progress;
842 bool bUserAssignLevel;
843 struct timer_list PSDTimer;
844 u8 RSSI_BT; /* come from BT */
846 bool bDMInitialGainEnable;
848 /* for rate adaptive, in fact, 88c/92c fw will handle this */
851 struct odm_rate_adapt RateAdaptive;
853 struct odm_rf_cal RFCalibrateInfo;
855 /* TX power tracking */
857 u8 BbSwingIdxOfdmCurrent;
858 u8 BbSwingIdxOfdmBase;
859 bool BbSwingFlagOfdm;
861 u8 BbSwingIdxCckCurrent;
862 u8 BbSwingIdxCckBase;
865 /* ODM system resource. */
867 /* ODM relative time. */
868 struct timer_list PathDivSwitchTimer;
869 /* 2011.09.27 add for Path Diversity */
870 struct timer_list CCKPathDiversityTimer;
871 struct timer_list FastAntTrainingTimer;
872 }; /* DM_Dynamic_Mechanism_Structure */
874 #define ODM_RF_PATH_MAX 3
876 enum ODM_RF_CONTENT {
877 odm_radioa_txt = 0x1000,
878 odm_radiob_txt = 0x1001,
879 odm_radioc_txt = 0x1002,
880 odm_radiod_txt = 0x1003
889 RT_STATUS_INVALID_CONTEXT,
890 RT_STATUS_INVALID_PARAMETER,
891 RT_STATUS_NOT_SUPPORT,
892 RT_STATUS_OS_API_FAILED,
895 /* 3=========================================================== */
897 /* 3=========================================================== */
900 RT_TYPE_THRESH_HIGH = 0,
901 RT_TYPE_THRESH_LOW = 1,
903 RT_TYPE_RX_GAIN_MIN = 3,
904 RT_TYPE_RX_GAIN_MAX = 4,
910 #define DM_DIG_THRESH_HIGH 40
911 #define DM_DIG_THRESH_LOW 35
913 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
916 #define DM_false_ALARM_THRESH_LOW 400
917 #define DM_false_ALARM_THRESH_HIGH 1000
919 #define DM_DIG_MAX_NIC 0x4e
920 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
922 #define DM_DIG_MAX_AP 0x32
923 #define DM_DIG_MIN_AP 0x20
925 #define DM_DIG_MAX_NIC_HP 0x46
926 #define DM_DIG_MIN_NIC_HP 0x2e
928 #define DM_DIG_MAX_AP_HP 0x42
929 #define DM_DIG_MIN_AP_HP 0x30
931 /* vivi 92c&92d has different definition, 20110504 */
932 /* this is for 92c */
933 #define DM_DIG_FA_TH0 0x200/* 0x20 */
934 #define DM_DIG_FA_TH1 0x300/* 0x100 */
935 #define DM_DIG_FA_TH2 0x400/* 0x200 */
936 /* this is for 92d */
937 #define DM_DIG_FA_TH0_92D 0x100
938 #define DM_DIG_FA_TH1_92D 0x400
939 #define DM_DIG_FA_TH2_92D 0x600
941 #define DM_DIG_BACKOFF_MAX 12
942 #define DM_DIG_BACKOFF_MIN -4
943 #define DM_DIG_BACKOFF_DEFAULT 10
945 /* 3=========================================================== */
946 /* 3 AGC RX High Power Mode */
947 /* 3=========================================================== */
948 #define LNA_Low_Gain_1 0x64
949 #define LNA_Low_Gain_2 0x5A
950 #define LNA_Low_Gain_3 0x58
952 #define FA_RXHP_TH1 5000
953 #define FA_RXHP_TH2 1500
954 #define FA_RXHP_TH3 800
955 #define FA_RXHP_TH4 600
956 #define FA_RXHP_TH5 500
958 /* 3=========================================================== */
960 /* 3=========================================================== */
962 /* 3=========================================================== */
963 /* 3 Dynamic Tx Power */
964 /* 3=========================================================== */
965 /* Dynamic Tx Power Control Threshold */
966 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
967 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
968 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
970 #define TxHighPwrLevel_Normal 0
971 #define TxHighPwrLevel_Level1 1
972 #define TxHighPwrLevel_Level2 2
973 #define TxHighPwrLevel_BT1 3
974 #define TxHighPwrLevel_BT2 4
975 #define TxHighPwrLevel_15 5
976 #define TxHighPwrLevel_35 6
977 #define TxHighPwrLevel_50 7
978 #define TxHighPwrLevel_70 8
979 #define TxHighPwrLevel_100 9
981 /* 3=========================================================== */
982 /* 3 Rate Adaptive */
983 /* 3=========================================================== */
984 #define DM_RATR_STA_INIT 0
985 #define DM_RATR_STA_HIGH 1
986 #define DM_RATR_STA_MIDDLE 2
987 #define DM_RATR_STA_LOW 3
989 /* 3=========================================================== */
990 /* 3 BB Power Save */
991 /* 3=========================================================== */
1006 /* 3=========================================================== */
1007 /* 3 Antenna Diversity */
1008 /* 3=========================================================== */
1015 /* Maximal number of antenna detection mechanism needs to perform. */
1016 #define MAX_ANTENNA_DETECTION_CNT 10
1018 /* Extern Global Variables. */
1019 #define OFDM_TABLE_SIZE_92C 37
1020 #define OFDM_TABLE_SIZE_92D 43
1021 #define CCK_TABLE_SIZE 33
1023 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1024 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1025 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1027 /* check Sta pointer valid or not */
1028 #define IS_STA_VALID(pSta) (pSta)
1029 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1030 /* This indicates two different the steps. */
1031 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1032 * signal on the air. */
1033 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1035 /* with original RSSI to determine if it is necessary to switch antenna. */
1036 #define SWAW_STEP_PEAK 0
1037 #define SWAW_STEP_DETERMINE 1
1039 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1040 #define dm_RF_Saving ODM_RF_Saving
1042 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1043 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1044 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1045 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1046 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1047 bool bForceUpdate, u8 *pRATRState);
1048 u32 ConvertTo_dB(u32 Value);
1049 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1050 u32 ra_mask, u8 rssi_level);
1051 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1052 enum odm_common_info_def CmnInfo, u32 Value);
1053 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1054 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1055 enum odm_common_info_def CmnInfo, void *pValue);
1056 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1057 enum odm_common_info_def CmnInfo,
1058 u16 Index, void *pValue);
1059 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1060 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1061 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);