drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #ifndef __INC_HAL8188EPHYCFG_H__
   8 #define __INC_HAL8188EPHYCFG_H__
   9
  10 #define LOOP_LIMIT                      5
  11 #define MAX_STALL_TIME                  50              /* us */
  12 #define AntennaDiversityValue           0x80
  13 #define MAX_TXPWR_IDX_NMODE_92S         63
  14 #define Reset_Cnt_Limit                 3
  15
  16 #define MAX_AGGR_NUM                    0x07
  17
  18 enum sw_chnl_cmd_id {
  19         CmdID_End,
  20         CmdID_SetTxPowerLevel,
  21         CmdID_BBRegWrite10,
  22         CmdID_WritePortUlong,
  23         CmdID_WritePortUshort,
  24         CmdID_WritePortUchar,
  25         CmdID_RF_WriteReg,
  26 };
  27
  28 /* 1. Switch channel related */
  29 struct sw_chnl_cmd {
  30         enum sw_chnl_cmd_id CmdID;
  31         u32 Para1;
  32         u32 Para2;
  33         u32 msDelay;
  34 };
  35
  36 enum hw90_block {
  37         HW90_BLOCK_MAC = 0,
  38         HW90_BLOCK_PHY0 = 1,
  39         HW90_BLOCK_PHY1 = 2,
  40         HW90_BLOCK_RF = 3,
  41         HW90_BLOCK_MAXIMUM = 4, /*  Never use this */
  42 };
  43
  44 enum rf_radio_path {
  45         RF_PATH_A = 0,                  /* Radio Path A */
  46         RF_PATH_B = 1,                  /* Radio Path B */
  47 };
  48
  49 #define MAX_PG_GROUP 13
  50
  51 #define RF_PATH_MAX                     2
  52 #define         MAX_RF_PATH             RF_PATH_MAX
  53 #define         MAX_TX_COUNT            4 /* path numbers */
  54
  55 #define CHANNEL_MAX_NUMBER              14      /*  14 is the max chnl number */
  56 #define MAX_CHNL_GROUP_24G              6       /*  ch1~2, ch3~5, ch6~8,
  57                                                  *ch9~11, ch12~13, CH 14
  58                                                  * total three groups
  59                                                  */
  60 #define CHANNEL_GROUP_MAX_88E           6
  61
  62 enum wireless_mode {
  63         WIRELESS_MODE_UNKNOWN = 0x00,
  64         WIRELESS_MODE_A                 = BIT(2),
  65         WIRELESS_MODE_B                 = BIT(0),
  66         WIRELESS_MODE_G                 = BIT(1),
  67         WIRELESS_MODE_AUTO              = BIT(5),
  68         WIRELESS_MODE_N_24G             = BIT(3),
  69         WIRELESS_MODE_N_5G              = BIT(4),
  70         WIRELESS_MODE_AC                = BIT(6)
  71 };
  72
  73 enum phy_rate_tx_offset_area {
  74         RA_OFFSET_LEGACY_OFDM1,
  75         RA_OFFSET_LEGACY_OFDM2,
  76         RA_OFFSET_HT_OFDM1,
  77         RA_OFFSET_HT_OFDM2,
  78         RA_OFFSET_HT_OFDM3,
  79         RA_OFFSET_HT_OFDM4,
  80         RA_OFFSET_HT_CCK,
  81 };
  82
  83 struct bb_reg_def {
  84         u32 rfintfs;            /*  set software control: */
  85                                 /*      0x870~0x877[8 bytes] */
  86         u32 rfintfi;            /*  readback data: */
  87                                 /*      0x8e0~0x8e7[8 bytes] */
  88         u32 rfintfo;            /*  output data: */
  89                                 /*      0x860~0x86f [16 bytes] */
  90         u32 rfintfe;            /*  output enable: */
  91                                 /*      0x860~0x86f [16 bytes] */
  92         u32 rf3wireOffset;      /*  LSSI data: */
  93                                 /*      0x840~0x84f [16 bytes] */
  94         u32 rfLSSI_Select;      /*  BB Band Select: */
  95                                 /*      0x878~0x87f [8 bytes] */
  96         u32 rfTxGainStage;      /*  Tx gain stage: */
  97                                 /*      0x80c~0x80f [4 bytes] */
  98         u32 rfHSSIPara1;        /*  wire parameter control1 : */
  99                                 /*      0x820~0x823,0x828~0x82b,
 100                                  *      0x830~0x833, 0x838~0x83b [16 bytes]
 101                                  */
 102         u32 rfHSSIPara2;        /*  wire parameter control2 : */
 103                                 /*      0x824~0x827,0x82c~0x82f, 0x834~0x837,
 104                                  *      0x83c~0x83f [16 bytes]
 105                                  */
 106         u32 rfSwitchControl;    /* Tx Rx antenna control : */
 107                                 /*      0x858~0x85f [16 bytes] */
 108         u32 rfAGCControl1;      /* AGC parameter control1 : */
 109                                 /*      0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
 110                                  * 0xc68~0xc6b [16 bytes]
 111                                  */
 112         u32 rfAGCControl2;      /* AGC parameter control2 : */
 113                                 /*      0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
 114                                  *      0xc6c~0xc6f [16 bytes]
 115                                  */
 116         u32 rfRxIQImbalance;    /* OFDM Rx IQ imbalance matrix : */
 117                                 /*      0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
 118                                  *      0xc2c~0xc2f [16 bytes]
 119                                  */
 120         u32 rfRxAFE;            /* Rx IQ DC ofset and Rx digital filter,
 121                                  * Rx DC notch filter :
 122                                  */
 123                                 /*      0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
 124                                  *      0xc28~0xc2b [16 bytes]
 125                                  */
 126         u32 rfTxIQImbalance;    /* OFDM Tx IQ imbalance matrix */
 127                                 /*      0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
 128                                  *       0xc98~0xc9b [16 bytes]
 129                                  */
 130         u32 rfTxAFE;            /* Tx IQ DC Offset and Tx DFIR type */
 131                                 /*      0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
 132                                  *      0xc9c~0xc9f [16 bytes]
 133                                  */
 134         u32 rfLSSIReadBack;     /* LSSI RF readback data SI mode */
 135                                 /*      0x8a0~0x8af [16 bytes] */
 136         u32 rfLSSIReadBackPi;   /* LSSI RF readback data PI mode 0x8b8-8bc for
 137                                  * Path A and B
 138                                  */
 139 };
 140
 141 /* Read initi reg value for tx power setting. */
 142 void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
 143
 144 /*  BB TX Power R/W */
 145 void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
 146
 147 void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
 148
 149 /*  Call after initialization */
 150 void ChkFwCmdIoDone(struct adapter *adapter);
 151
 152 /*  BB/MAC/RF other monitor API */
 153 void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
 154
 155 void PHY_SwitchEphyParameter(struct adapter *adapter);
 156
 157 void PHY_EnableHostClkReq(struct adapter *adapter);
 158
 159 bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
 160
 161 #define PHY_SetMacReg   PHY_SetBBReg
 162
 163 #define SIC_HW_SUPPORT                  0
 164
 165 #define SIC_MAX_POLL_CNT                5
 166
 167 #define SIC_CMD_READY                   0
 168 #define SIC_CMD_WRITE                   1
 169 #define SIC_CMD_READ                    2
 170
 171 #define SIC_CMD_REG                     0x1EB           /*  1byte */
 172 #define SIC_ADDR_REG                    0x1E8           /*  1b9~1ba, 2 bytes */
 173 #define SIC_DATA_REG                    0x1EC           /*  1bc~1bf */
 174
 175 #endif  /*  __INC_HAL8192CPHYCFG_H */