1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
15 #ifndef __INC_HAL8188EPHYREG_H__
16 #define __INC_HAL8188EPHYREG_H__
17 /*--------------------------Define Parameters-------------------------------*/
19 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
20 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
21 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
22 /* 3. RF register 0x00-2E */
23 /* 4. Bit Mask for BB/RF register */
24 /* 5. Other definition for BB/RF R/W */
29 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
32 #define rPMAC_Reset 0x100
33 #define rPMAC_TxStart 0x104
34 #define rPMAC_TxLegacySIG 0x108
35 #define rPMAC_TxHTSIG1 0x10c
36 #define rPMAC_TxHTSIG2 0x110
37 #define rPMAC_PHYDebug 0x114
38 #define rPMAC_TxPacketNum 0x118
39 #define rPMAC_TxIdle 0x11c
40 #define rPMAC_TxMACHeader0 0x120
41 #define rPMAC_TxMACHeader1 0x124
42 #define rPMAC_TxMACHeader2 0x128
43 #define rPMAC_TxMACHeader3 0x12c
44 #define rPMAC_TxMACHeader4 0x130
45 #define rPMAC_TxMACHeader5 0x134
46 #define rPMAC_TxDataType 0x138
47 #define rPMAC_TxRandomSeed 0x13c
48 #define rPMAC_CCKPLCPPreamble 0x140
49 #define rPMAC_CCKPLCPHeader 0x144
50 #define rPMAC_CCKCRC16 0x148
51 #define rPMAC_OFDMRxCRC32OK 0x170
52 #define rPMAC_OFDMRxCRC32Er 0x174
53 #define rPMAC_OFDMRxParityEr 0x178
54 #define rPMAC_OFDMRxCRC8Er 0x17c
55 #define rPMAC_CCKCRxRC16Er 0x180
56 #define rPMAC_CCKCRxRC32Er 0x184
57 #define rPMAC_CCKCRxRC32OK 0x188
58 #define rPMAC_TxStatus 0x18c
61 /* The following two definition are only used for USB interface. */
62 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */
63 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */
66 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
68 #define rFPGA0_TxInfo 0x804 /* Status report?? */
69 #define rFPGA0_PSDFunction 0x808
71 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
73 #define rFPGA0_RFTiming1 0x810 /* Useless now */
74 #define rFPGA0_RFTiming2 0x814
76 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
77 #define rFPGA0_XA_HSSIParameter2 0x824
78 #define rFPGA0_XB_HSSIParameter1 0x828
79 #define rFPGA0_XB_HSSIParameter2 0x82c
81 #define rFPGA0_XA_LSSIParameter 0x840
82 #define rFPGA0_XB_LSSIParameter 0x844
84 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
85 #define rFPGA0_RFSleepUpParameter 0x854
87 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
88 #define rFPGA0_XCD_SwitchControl 0x85c
90 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
91 #define rFPGA0_XB_RFInterfaceOE 0x864
93 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */
94 #define rFPGA0_XCD_RFInterfaceSW 0x874
96 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
97 #define rFPGA0_XCD_RFParameter 0x87c
99 /* Crystal cap setting RF-R/W protection for parameter4?? */
100 #define rFPGA0_AnalogParameter1 0x880
101 #define rFPGA0_AnalogParameter2 0x884
102 #define rFPGA0_AnalogParameter3 0x888
103 /* enable ad/da clock1 for dual-phy */
104 #define rFPGA0_AdDaClockEn 0x888
105 #define rFPGA0_AnalogParameter4 0x88c
107 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
108 #define rFPGA0_XB_LSSIReadBack 0x8a4
109 #define rFPGA0_XC_LSSIReadBack 0x8a8
110 #define rFPGA0_XD_LSSIReadBack 0x8ac
112 #define rFPGA0_PSDReport 0x8b4 /* Useless now */
113 /* Transceiver A HSPI Readback */
114 #define TransceiverA_HSPI_Readback 0x8b8
115 /* Transceiver B HSPI Readback */
116 #define TransceiverB_HSPI_Readback 0x8bc
117 /* Useless now RF Interface Readback Value */
118 #define rFPGA0_XAB_RFInterfaceRB 0x8e0
119 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
121 /* 4. Page9(0x900) */
122 /* RF mode & OFDM TxSC RF BW Setting?? */
123 #define rFPGA1_RFMOD 0x900
125 #define rFPGA1_TxBlock 0x904 /* Useless now */
126 #define rFPGA1_DebugSelect 0x908 /* Useless now */
127 #define rFPGA1_TxInfo 0x90c /* Useless now Status report */
129 /* 5. PageA(0xA00) */
130 /* Set Control channel to upper or lower - required only for 40MHz */
131 #define rCCK0_System 0xa00
133 /* Disable init gain now Select RX path by RSSI */
134 #define rCCK0_AFESetting 0xa04
135 /* Disable init gain now Init gain */
136 #define rCCK0_CCA 0xa08
138 /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold,
139 * RX LNA Threshold useless now. Not the same as 90 series */
140 #define rCCK0_RxAGC1 0xa0c
141 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
143 #define rCCK0_RxHP 0xa14
145 /* Timing recovery & Channel estimation threshold */
146 #define rCCK0_DSPParameter1 0xa18
147 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
149 #define rCCK0_TxFilter1 0xa20
150 #define rCCK0_TxFilter2 0xa24
151 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
152 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now */
153 #define rCCK0_TRSSIReport 0xa50
154 #define rCCK0_RxReport 0xa54 /* 0xa57 */
155 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
156 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
161 #define rPdp_AntA 0xb00
162 #define rPdp_AntA_4 0xb04
163 #define rConfig_Pmpd_AntA 0xb28
164 #define rConfig_AntA 0xb68
165 #define rConfig_AntB 0xb6c
166 #define rPdp_AntB 0xb70
167 #define rPdp_AntB_4 0xb74
168 #define rConfig_Pmpd_AntB 0xb98
172 /* 6. PageC(0xC00) */
174 #define rOFDM0_LSTF 0xc00
176 #define rOFDM0_TRxPathEnable 0xc04
177 #define rOFDM0_TRMuxPar 0xc08
178 #define rOFDM0_TRSWIsolation 0xc0c
180 /* RxIQ DC offset, Rx digital filter, DC notch filter */
181 #define rOFDM0_XARxAFE 0xc10
182 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
183 #define rOFDM0_XBRxAFE 0xc18
184 #define rOFDM0_XBRxIQImbalance 0xc1c
185 #define rOFDM0_XCRxAFE 0xc20
186 #define rOFDM0_XCRxIQImbalance 0xc24
187 #define rOFDM0_XDRxAFE 0xc28
188 #define rOFDM0_XDRxIQImbalance 0xc2c
190 #define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/
191 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
192 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
193 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
195 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
196 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
197 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
198 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
200 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
201 #define rOFDM0_XAAGCCore2 0xc54
202 #define rOFDM0_XBAGCCore1 0xc58
203 #define rOFDM0_XBAGCCore2 0xc5c
204 #define rOFDM0_XCAGCCore1 0xc60
205 #define rOFDM0_XCAGCCore2 0xc64
206 #define rOFDM0_XDAGCCore1 0xc68
207 #define rOFDM0_XDAGCCore2 0xc6c
209 #define rOFDM0_AGCParameter1 0xc70
210 #define rOFDM0_AGCParameter2 0xc74
211 #define rOFDM0_AGCRSSITable 0xc78
212 #define rOFDM0_HTSTFAGC 0xc7c
214 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
215 #define rOFDM0_XATxAFE 0xc84
216 #define rOFDM0_XBTxIQImbalance 0xc88
217 #define rOFDM0_XBTxAFE 0xc8c
218 #define rOFDM0_XCTxIQImbalance 0xc90
219 #define rOFDM0_XCTxAFE 0xc94
220 #define rOFDM0_XDTxIQImbalance 0xc98
221 #define rOFDM0_XDTxAFE 0xc9c
223 #define rOFDM0_RxIQExtAnta 0xca0
224 #define rOFDM0_TxCoeff1 0xca4
225 #define rOFDM0_TxCoeff2 0xca8
226 #define rOFDM0_TxCoeff3 0xcac
227 #define rOFDM0_TxCoeff4 0xcb0
228 #define rOFDM0_TxCoeff5 0xcb4
229 #define rOFDM0_TxCoeff6 0xcb8
230 #define rOFDM0_RxHPParameter 0xce0
231 #define rOFDM0_TxPseudoNoiseWgt 0xce4
232 #define rOFDM0_FrameSync 0xcf0
233 #define rOFDM0_DFSReport 0xcf4
237 /* 7. PageD(0xD00) */
239 #define rOFDM1_LSTF 0xd00
240 #define rOFDM1_TRxPathEnable 0xd04
242 #define rOFDM1_CFO 0xd08 /* No setting now */
243 #define rOFDM1_CSI1 0xd10
244 #define rOFDM1_SBD 0xd14
245 #define rOFDM1_CSI2 0xd18
246 #define rOFDM1_CFOTracking 0xd2c
247 #define rOFDM1_TRxMesaure1 0xd34
248 #define rOFDM1_IntfDet 0xd3c
249 #define rOFDM1_PseudoNoiseStateAB 0xd50
250 #define rOFDM1_PseudoNoiseStateCD 0xd54
251 #define rOFDM1_RxPseudoNoiseWgt 0xd58
253 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
254 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
255 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
257 #define rOFDM_ShortCFOAB 0xdac /* No setting now */
258 #define rOFDM_ShortCFOCD 0xdb0
259 #define rOFDM_LongCFOAB 0xdb4
260 #define rOFDM_LongCFOCD 0xdb8
261 #define rOFDM_TailCFOAB 0xdbc
262 #define rOFDM_TailCFOCD 0xdc0
263 #define rOFDM_PWMeasure1 0xdc4
264 #define rOFDM_PWMeasure2 0xdc8
265 #define rOFDM_BWReport 0xdcc
266 #define rOFDM_AGCReport 0xdd0
267 #define rOFDM_RxSNR 0xdd4
268 #define rOFDM_RxEVMCSI 0xdd8
269 #define rOFDM_SIGReport 0xddc
273 /* 8. PageE(0xE00) */
275 #define rTxAGC_A_Rate18_06 0xe00
276 #define rTxAGC_A_Rate54_24 0xe04
277 #define rTxAGC_A_CCK1_Mcs32 0xe08
278 #define rTxAGC_A_Mcs03_Mcs00 0xe10
279 #define rTxAGC_A_Mcs07_Mcs04 0xe14
280 #define rTxAGC_A_Mcs11_Mcs08 0xe18
281 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
283 #define rTxAGC_B_Rate18_06 0x830
284 #define rTxAGC_B_Rate54_24 0x834
285 #define rTxAGC_B_CCK1_55_Mcs32 0x838
286 #define rTxAGC_B_Mcs03_Mcs00 0x83c
287 #define rTxAGC_B_Mcs07_Mcs04 0x848
288 #define rTxAGC_B_Mcs11_Mcs08 0x84c
289 #define rTxAGC_B_Mcs15_Mcs12 0x868
290 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
292 #define rFPGA0_IQK 0xe28
293 #define rTx_IQK_Tone_A 0xe30
294 #define rRx_IQK_Tone_A 0xe34
295 #define rTx_IQK_PI_A 0xe38
296 #define rRx_IQK_PI_A 0xe3c
298 #define rTx_IQK 0xe40
299 #define rRx_IQK 0xe44
300 #define rIQK_AGC_Pts 0xe48
301 #define rIQK_AGC_Rsp 0xe4c
302 #define rTx_IQK_Tone_B 0xe50
303 #define rRx_IQK_Tone_B 0xe54
304 #define rTx_IQK_PI_B 0xe58
305 #define rRx_IQK_PI_B 0xe5c
306 #define rIQK_AGC_Cont 0xe60
308 #define rBlue_Tooth 0xe6c
309 #define rRx_Wait_CCA 0xe70
310 #define rTx_CCK_RFON 0xe74
311 #define rTx_CCK_BBON 0xe78
312 #define rTx_OFDM_RFON 0xe7c
313 #define rTx_OFDM_BBON 0xe80
314 #define rTx_To_Rx 0xe84
315 #define rTx_To_Tx 0xe88
316 #define rRx_CCK 0xe8c
318 #define rTx_Power_Before_IQK_A 0xe94
319 #define rTx_Power_After_IQK_A 0xe9c
321 #define rRx_Power_Before_IQK_A 0xea0
322 #define rRx_Power_Before_IQK_A_2 0xea4
323 #define rRx_Power_After_IQK_A 0xea8
324 #define rRx_Power_After_IQK_A_2 0xeac
326 #define rTx_Power_Before_IQK_B 0xeb4
327 #define rTx_Power_After_IQK_B 0xebc
329 #define rRx_Power_Before_IQK_B 0xec0
330 #define rRx_Power_Before_IQK_B_2 0xec4
331 #define rRx_Power_After_IQK_B 0xec8
332 #define rRx_Power_After_IQK_B_2 0xecc
334 #define rRx_OFDM 0xed0
335 #define rRx_Wait_RIFS 0xed4
336 #define rRx_TO_Rx 0xed8
337 #define rStandby 0xedc
339 #define rPMPD_ANAEN 0xeec
342 /* 7. RF Register 0x00-0x2E (RF 8256) */
343 /* RF-0222D 0x00-3F */
346 #define rZebra1_HSSIEnable 0x0 /* Useless now */
347 #define rZebra1_TRxEnable1 0x1
348 #define rZebra1_TRxEnable2 0x2
349 #define rZebra1_AGC 0x4
350 #define rZebra1_ChargePump 0x5
351 #define rZebra1_Channel 0x7 /* RF channel switch */
354 #define rZebra1_TxGain 0x8 /* Useless now */
355 #define rZebra1_TxLPF 0x9
356 #define rZebra1_RxLPF 0xb
357 #define rZebra1_RxHPFCorner 0xc
360 #define rGlobalCtrl 0 /* Useless now */
361 #define rRTL8256_TxLPF 19
362 #define rRTL8256_RxLPF 11
365 #define rRTL8258_TxLPF 0x11 /* Useless now */
366 #define rRTL8258_RxLPF 0x13
367 #define rRTL8258_RSSILPF 0xa
370 /* RL6052 Register definition */
372 #define RF_AC 0x00 /* */
374 #define RF_IQADJ_G1 0x01 /* */
375 #define RF_IQADJ_G2 0x02 /* */
377 #define RF_POW_TRSW 0x05 /* */
379 #define RF_GAIN_RX 0x06 /* */
380 #define RF_GAIN_TX 0x07 /* */
382 #define RF_TXM_IDAC 0x08 /* */
383 #define RF_IPA_G 0x09 /* */
384 #define RF_TXBIAS_G 0x0A
385 #define RF_TXPA_AG 0x0B
386 #define RF_IPA_A 0x0C /* */
387 #define RF_TXBIAS_A 0x0D
388 #define RF_BS_PA_APSET_G9_G11 0x0E
389 #define RF_BS_IQGEN 0x0F /* */
391 #define RF_MODE1 0x10 /* */
392 #define RF_MODE2 0x11 /* */
394 #define RF_RX_AGC_HP 0x12 /* */
395 #define RF_TX_AGC 0x13 /* */
396 #define RF_BIAS 0x14 /* */
397 #define RF_IPA 0x15 /* */
398 #define RF_TXBIAS 0x16
399 #define RF_POW_ABILITY 0x17 /* */
400 #define RF_CHNLBW 0x18 /* RF channel and BW switch */
401 #define RF_TOP 0x19 /* */
403 #define RF_RX_G1 0x1A /* */
404 #define RF_RX_G2 0x1B /* */
406 #define RF_RX_BB2 0x1C /* */
407 #define RF_RX_BB1 0x1D /* */
409 #define RF_RCK1 0x1E /* */
410 #define RF_RCK2 0x1F /* */
412 #define RF_TX_G1 0x20 /* */
413 #define RF_TX_G2 0x21 /* */
414 #define RF_TX_G3 0x22 /* */
416 #define RF_TX_BB1 0x23 /* */
418 #define RF_T_METER_92D 0x42 /* */
419 #define RF_T_METER_88E 0x42 /* */
420 #define RF_T_METER 0x24 /* */
422 #define RF_SYN_G1 0x25 /* RF TX Power control */
423 #define RF_SYN_G2 0x26 /* RF TX Power control */
424 #define RF_SYN_G3 0x27 /* RF TX Power control */
425 #define RF_SYN_G4 0x28 /* RF TX Power control */
426 #define RF_SYN_G5 0x29 /* RF TX Power control */
427 #define RF_SYN_G6 0x2A /* RF TX Power control */
428 #define RF_SYN_G7 0x2B /* RF TX Power control */
429 #define RF_SYN_G8 0x2C /* RF TX Power control */
431 #define RF_RCK_OS 0x30 /* RF TX PA control */
432 #define RF_TXPA_G1 0x31 /* RF TX PA control */
433 #define RF_TXPA_G2 0x32 /* RF TX PA control */
434 #define RF_TXPA_G3 0x33 /* RF TX PA control */
435 #define RF_TX_BIAS_A 0x35
436 #define RF_TX_BIAS_D 0x36
437 #define RF_LOBF_9 0x38
438 #define RF_RXRF_A3 0x3C /* */
441 #define RF_TXRF_A2 0x41
442 #define RF_TXPA_G4 0x46
443 #define RF_TXPA_A4 0x4B
445 #define RF_WE_LUT 0xEF
451 /* 1. Page1(0x100) */
452 #define bBBResetB 0x100 /* Useless now? */
453 #define bGlobalResetB 0x200
454 #define bOFDMTxStart 0x4
455 #define bCCKTxStart 0x8
456 #define bCRC32Debug 0x100
457 #define bPMACLoopback 0x10
458 #define bTxLSIG 0xffffff
459 #define bOFDMTxRate 0xf
460 #define bOFDMTxReserved 0x10
461 #define bOFDMTxLength 0x1ffe0
462 #define bOFDMTxParity 0x20000
463 #define bTxHTSIG1 0xffffff
464 #define bTxHTMCSRate 0x7f
466 #define bTxHTLength 0xffff00
467 #define bTxHTSIG2 0xffffff
468 #define bTxHTSmoothing 0x1
469 #define bTxHTSounding 0x2
470 #define bTxHTReserved 0x4
471 #define bTxHTAggreation 0x8
472 #define bTxHTSTBC 0x30
473 #define bTxHTAdvanceCoding 0x40
474 #define bTxHTShortGI 0x80
475 #define bTxHTNumberHT_LTF 0x300
476 #define bTxHTCRC8 0x3fc00
477 #define bCounterReset 0x10000
478 #define bNumOfOFDMTx 0xffff
479 #define bNumOfCCKTx 0xffff0000
480 #define bTxIdleInterval 0xffff
481 #define bOFDMService 0xffff0000
482 #define bTxMACHeader 0xffffffff
483 #define bTxDataInit 0xff
484 #define bTxHTMode 0x100
485 #define bTxDataType 0x30000
486 #define bTxRandomSeed 0xffffffff
487 #define bCCKTxPreamble 0x1
488 #define bCCKTxSFD 0xffff0000
489 #define bCCKTxSIG 0xff
490 #define bCCKTxService 0xff00
491 #define bCCKLengthExt 0x8000
492 #define bCCKTxLength 0xffff0000
493 #define bCCKTxCRC16 0xffff
494 #define bCCKTxStatus 0x1
495 #define bOFDMTxStatus 0x2
497 #define IS_BB_REG_OFFSET_92S(_Offset) \
498 ((_Offset >= 0x800) && (_Offset <= 0xfff))
500 /* 2. Page8(0x800) */
501 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
502 #define bJapanMode 0x2
503 #define bCCKTxSC 0x30
504 #define bCCKEn 0x1000000
505 #define bOFDMEn 0x2000000
507 #define bOFDMRxADCPhase 0x10000 /* Useless now */
508 #define bOFDMTxDACPhase 0x40000
509 #define bXATxAGC 0x3f
511 #define bAntennaSelect 0x0300
513 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
514 #define bXCTxAGC 0xf000
515 #define bXDTxAGC 0xf0000
517 #define bPAStart 0xf0000000 /* Useless now */
518 #define bTRStart 0x00f00000
519 #define bRFStart 0x0000f000
520 #define bBBStart 0x000000f0
521 #define bBBCCKStart 0x0000000f
522 #define bPAEnd 0xf /* Reg0x814 */
523 #define bTREnd 0x0f000000
524 #define bRFEnd 0x000f0000
525 #define bCCAMask 0x000000f0 /* T2R */
526 #define bR2RCCAMask 0x00000f00
527 #define bHSSI_R2TDelay 0xf8000000
528 #define bHSSI_T2RDelay 0xf80000
529 #define bContTxHSSI 0x400 /* change gain at continue Tx */
530 #define bIGFromCCK 0x200
531 #define bAGCAddress 0x3f
532 #define bRxHPTx 0x7000
533 #define bRxHPT2R 0x38000
534 #define bRxHPCCKIni 0xc0000
535 #define bAGCTxCode 0xc00000
536 #define bAGCRxCode 0x300000
538 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
539 #define b3WireDataLength 0x800
540 #define b3WireAddressLength 0x400
542 #define b3WireRFPowerDown 0x1 /* Useless now */
543 #define b5GPAPEPolarity 0x40000000
544 #define b2GPAPEPolarity 0x80000000
545 #define bRFSW_TxDefaultAnt 0x3
546 #define bRFSW_TxOptionAnt 0x30
547 #define bRFSW_RxDefaultAnt 0x300
548 #define bRFSW_RxOptionAnt 0x3000
549 #define bRFSI_3WireData 0x1
550 #define bRFSI_3WireClock 0x2
551 #define bRFSI_3WireLoad 0x4
552 #define bRFSI_3WireRW 0x8
553 #define bRFSI_3Wire 0xf
555 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
557 #define bRFSI_TRSW 0x20 /* Useless now */
558 #define bRFSI_TRSWB 0x40
559 #define bRFSI_ANTSW 0x100
560 #define bRFSI_ANTSWB 0x200
561 #define bRFSI_PAPE 0x400
562 #define bRFSI_PAPE5G 0x800
563 #define bBandSelect 0x1
564 #define bHTSIG2_GI 0x80
565 #define bHTSIG2_Smoothing 0x01
566 #define bHTSIG2_Sounding 0x02
567 #define bHTSIG2_Aggreaton 0x08
568 #define bHTSIG2_STBC 0x30
569 #define bHTSIG2_AdvCoding 0x40
570 #define bHTSIG2_NumOfHTLTF 0x300
571 #define bHTSIG2_CRC8 0x3fc
572 #define bHTSIG1_MCS 0x7f
573 #define bHTSIG1_BandWidth 0x80
574 #define bHTSIG1_HTLength 0xffff
575 #define bLSIG_Rate 0xf
576 #define bLSIG_Reserved 0x10
577 #define bLSIG_Length 0x1fffe
578 #define bLSIG_Parity 0x20
579 #define bCCKRxPhase 0x4
581 #define bLSSIReadAddress 0x7f800000 /* T65 RF */
583 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
585 #define bLSSIReadBackData 0xfffff /* T65 RF */
587 #define bLSSIReadOKFlag 0x1000 /* Useless now */
588 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
589 #define bRegulator0Standby 0x1
590 #define bRegulatorPLLStandby 0x2
591 #define bRegulator1Standby 0x4
592 #define bPLLPowerUp 0x8
593 #define bDPLLPowerUp 0x10
594 #define bDA10PowerUp 0x20
595 #define bAD7PowerUp 0x200
596 #define bDA6PowerUp 0x2000
597 #define bXtalPowerUp 0x4000
598 #define b40MDClkPowerUP 0x8000
599 #define bDA6DebugMode 0x20000
600 #define bDA6Swing 0x380000
602 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
603 #define bADClkPhase 0x4000000
605 #define b80MClkDelay 0x18000000 /* Useless */
606 #define bAFEWatchDogEnable 0x20000000
608 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
609 #define bXtalCap01 0xc0000000
610 #define bXtalCap23 0x3
611 #define bXtalCap92x 0x0f000000
612 #define bXtalCap 0x0f000000
614 #define bIntDifClkEnable 0x400 /* Useless */
615 #define bExtSigClkEnable 0x800
616 #define bBandgapMbiasPowerUp 0x10000
617 #define bAD11SHGain 0xc0000
618 #define bAD11InputRange 0x700000
619 #define bAD11OPCurrent 0x3800000
620 #define bIPathLoopback 0x4000000
621 #define bQPathLoopback 0x8000000
622 #define bAFELoopback 0x10000000
623 #define bDA10Swing 0x7e0
624 #define bDA10Reverse 0x800
625 #define bDAClkSource 0x1000
626 #define bAD7InputRange 0x6000
627 #define bAD7Gain 0x38000
628 #define bAD7OutputCMMode 0x40000
629 #define bAD7InputCMMode 0x380000
630 #define bAD7Current 0xc00000
631 #define bRegulatorAdjust 0x7000000
632 #define bAD11PowerUpAtTx 0x1
633 #define bDA10PSAtTx 0x10
634 #define bAD11PowerUpAtRx 0x100
635 #define bDA10PSAtRx 0x1000
636 #define bCCKRxAGCFormat 0x200
637 #define bPSDFFTSamplepPoint 0xc000
638 #define bPSDAverageNum 0x3000
639 #define bIQPathControl 0xc00
640 #define bPSDFreq 0x3ff
641 #define bPSDAntennaPath 0x30
642 #define bPSDIQSwitch 0x40
643 #define bPSDRxTrigger 0x400000
644 #define bPSDTxTrigger 0x80000000
645 #define bPSDSineToneScale 0x7f000000
646 #define bPSDReport 0xffff
648 /* 3. Page9(0x900) */
649 #define bOFDMTxSC 0x30000000 /* Useless */
651 #define bOFDMTxOn 0x2
652 #define bDebugPage 0xfff /* reset debug page and HWord, LWord */
653 #define bDebugItem 0xff /* reset debug page and LWord */
655 #define bAntNonHT 0x100
656 #define bAntHT1 0x1000
657 #define bAntHT2 0x10000
658 #define bAntHT1S1 0x100000
659 #define bAntNonHTS1 0x1000000
661 /* 4. PageA(0xA00) */
662 #define bCCKBBMode 0x3 /* Useless */
663 #define bCCKTxPowerSaving 0x80
664 #define bCCKRxPowerSaving 0x40
666 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */
668 #define bCCKScramble 0x8 /* Useless */
669 #define bCCKAntDiversity 0x8000
670 #define bCCKCarrierRecovery 0x4000
671 #define bCCKTxRate 0x3000
672 #define bCCKDCCancel 0x0800
673 #define bCCKISICancel 0x0400
674 #define bCCKMatchFilter 0x0200
675 #define bCCKEqualizer 0x0100
676 #define bCCKPreambleDetect 0x800000
677 #define bCCKFastFalseCCA 0x400000
678 #define bCCKChEstStart 0x300000
679 #define bCCKCCACount 0x080000
680 #define bCCKcs_lim 0x070000
681 #define bCCKBistMode 0x80000000
682 #define bCCKCCAMask 0x40000000
683 #define bCCKTxDACPhase 0x4
684 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
685 #define bCCKr_cp_mode0 0x0100
686 #define bCCKTxDCOffset 0xf0
687 #define bCCKRxDCOffset 0xf
688 #define bCCKCCAMode 0xc000
689 #define bCCKFalseCS_lim 0x3f00
690 #define bCCKCS_ratio 0xc00000
691 #define bCCKCorgBit_sel 0x300000
692 #define bCCKPD_lim 0x0f0000
693 #define bCCKNewCCA 0x80000000
694 #define bCCKRxHPofIG 0x8000
695 #define bCCKRxIG 0x7f00
696 #define bCCKLNAPolarity 0x800000
697 #define bCCKRx1stGain 0x7f0000
698 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
699 #define bCCKRxAGCSatLevel 0x1f000000
700 #define bCCKRxAGCSatCount 0xe0
701 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
702 #define bCCKFixedRxAGC 0x8000
703 #define bCCKAntennaPolarity 0x2000
704 #define bCCKTxFilterType 0x0c00
705 #define bCCKRxAGCReportType 0x0300
706 #define bCCKRxDAGCEn 0x80000000
707 #define bCCKRxDAGCPeriod 0x20000000
708 #define bCCKRxDAGCSatLevel 0x1f000000
709 #define bCCKTimingRecovery 0x800000
710 #define bCCKTxC0 0x3f0000
711 #define bCCKTxC1 0x3f000000
712 #define bCCKTxC2 0x3f
713 #define bCCKTxC3 0x3f00
714 #define bCCKTxC4 0x3f0000
715 #define bCCKTxC5 0x3f000000
716 #define bCCKTxC6 0x3f
717 #define bCCKTxC7 0x3f00
718 #define bCCKDebugPort 0xff0000
719 #define bCCKDACDebug 0x0f000000
720 #define bCCKFalseAlarmEnable 0x8000
721 #define bCCKFalseAlarmRead 0x4000
722 #define bCCKTRSSI 0x7f
723 #define bCCKRxAGCReport 0xfe
724 #define bCCKRxReport_AntSel 0x80000000
725 #define bCCKRxReport_MFOff 0x40000000
726 #define bCCKRxRxReport_SQLoss 0x20000000
727 #define bCCKRxReport_Pktloss 0x10000000
728 #define bCCKRxReport_Lockedbit 0x08000000
729 #define bCCKRxReport_RateError 0x04000000
730 #define bCCKRxReport_RxRate 0x03000000
731 #define bCCKRxFACounterLower 0xff
732 #define bCCKRxFACounterUpper 0xff000000
733 #define bCCKRxHPAGCStart 0xe000
734 #define bCCKRxHPAGCFinal 0x1c00
735 #define bCCKRxFalseAlarmEnable 0x8000
736 #define bCCKFACounterFreeze 0x4000
737 #define bCCKTxPathSel 0x10000000
738 #define bCCKDefaultRxPath 0xc000000
739 #define bCCKOptionRxPath 0x3000000
741 /* 5. PageC(0xC00) */
742 #define bNumOfSTF 0x3 /* Useless */
743 #define bShift_L 0xc0
753 #define bTRSSIFreq 0x200
754 #define bADCBackoff 0x3000
755 #define bDFIRBackoff 0xc000
756 #define bTRSSILatchPhase 0x10000
757 #define bRxIDCOffset 0xff
758 #define bRxQDCOffset 0xff00
759 #define bRxDFIRMode 0x1800000
760 #define bRxDCNFType 0xe000000
761 #define bRXIQImb_A 0x3ff
762 #define bRXIQImb_B 0xfc00
763 #define bRXIQImb_C 0x3f0000
764 #define bRXIQImb_D 0xffc00000
765 #define bDC_dc_Notch 0x60000
766 #define bRxNBINotch 0x1f000000
768 #define bPD_TH_Opt2 0xc000
769 #define bPWED_TH 0x700
770 #define bIfMF_Win_L 0x800
771 #define bPD_Option 0x1000
772 #define bMF_Win_L 0xe000
773 #define bBW_Search_L 0x30000
774 #define bwin_enh_L 0xc0000
775 #define bBW_TH 0x700000
776 #define bED_TH2 0x3800000
777 #define bBW_option 0x4000000
778 #define bRatio_TH 0x18000000
779 #define bWindow_L 0xe0000000
780 #define bSBD_Option 0x1
781 #define bFrame_TH 0x1c
782 #define bFS_Option 0x60
783 #define bDC_Slope_check 0x80
784 #define bFGuard_Counter_DC_L 0xe00
785 #define bFrame_Weight_Short 0x7000
786 #define bSub_Tune 0xe00000
787 #define bFrame_DC_Length 0xe000000
788 #define bSBD_start_offset 0x30000000
789 #define bFrame_TH_2 0x7
790 #define bFrame_GI2_TH 0x38
791 #define bGI2_Sync_en 0x40
792 #define bSarch_Short_Early 0x300
793 #define bSarch_Short_Late 0xc00
794 #define bSarch_GI2_Late 0x70000
795 #define bCFOAntSum 0x1
797 #define bCFOStartOffset 0xc
798 #define bCFOLookBack 0x70
799 #define bCFOSumWeight 0x80
800 #define bDAGCEnable 0x10000
801 #define bTXIQImb_A 0x3ff
802 #define bTXIQImb_B 0xfc00
803 #define bTXIQImb_C 0x3f0000
804 #define bTXIQImb_D 0xffc00000
805 #define bTxIDCOffset 0xff
806 #define bTxQDCOffset 0xff00
807 #define bTxDFIRMode 0x10000
808 #define bTxPesudoNoiseOn 0x4000000
809 #define bTxPesudoNoise_A 0xff
810 #define bTxPesudoNoise_B 0xff00
811 #define bTxPesudoNoise_C 0xff0000
812 #define bTxPesudoNoise_D 0xff000000
813 #define bCCADropOption 0x20000
814 #define bCCADropThres 0xfff00000
816 #define bEDCCA_L 0xf0
817 #define bLambda_ED 0x300
818 #define bRxInitialGain 0x7f
819 #define bRxAntDivEn 0x80
820 #define bRxAGCAddressForLNA 0x7f00
821 #define bRxHighPowerFlow 0x8000
822 #define bRxAGCFreezeThres 0xc0000
823 #define bRxFreezeStep_AGC1 0x300000
824 #define bRxFreezeStep_AGC2 0xc00000
825 #define bRxFreezeStep_AGC3 0x3000000
826 #define bRxFreezeStep_AGC0 0xc000000
827 #define bRxRssi_Cmp_En 0x10000000
828 #define bRxQuickAGCEn 0x20000000
829 #define bRxAGCFreezeThresMode 0x40000000
830 #define bRxOverFlowCheckType 0x80000000
831 #define bRxAGCShift 0x7f
832 #define bTRSW_Tri_Only 0x80
833 #define bPowerThres 0x300
835 #define bRxAGCTogetherEn 0x2
836 #define bRxAGCMin 0x4
837 #define bRxHP_Ini 0x7
838 #define bRxHP_TRLNA 0x70
839 #define bRxHP_RSSI 0x700
840 #define bRxHP_BBP1 0x7000
841 #define bRxHP_BBP2 0x70000
842 #define bRxHP_BBP3 0x700000
843 #define bRSSI_H 0x7f0000 /* threshold for high power */
844 #define bRSSI_Gen 0x7f000000 /* threshold for ant diversity */
845 #define bRxSettle_TRSW 0x7
846 #define bRxSettle_LNA 0x38
847 #define bRxSettle_RSSI 0x1c0
848 #define bRxSettle_BBP 0xe00
849 #define bRxSettle_RxHP 0x7000
850 #define bRxSettle_AntSW_RSSI 0x38000
851 #define bRxSettle_AntSW 0xc0000
852 #define bRxProcessTime_DAGC 0x300000
853 #define bRxSettle_HSSI 0x400000
854 #define bRxProcessTime_BBPPW 0x800000
855 #define bRxAntennaPowerShift 0x3000000
856 #define bRSSITableSelect 0xc000000
857 #define bRxHP_Final 0x7000000
858 #define bRxHTSettle_BBP 0x7
859 #define bRxHTSettle_HSSI 0x8
860 #define bRxHTSettle_RxHP 0x70
861 #define bRxHTSettle_BBPPW 0x80
862 #define bRxHTSettle_Idle 0x300
863 #define bRxHTSettle_Reserved 0x1c00
864 #define bRxHTRxHPEn 0x8000
865 #define bRxHTAGCFreezeThres 0x30000
866 #define bRxHTAGCTogetherEn 0x40000
867 #define bRxHTAGCMin 0x80000
868 #define bRxHTAGCEn 0x100000
869 #define bRxHTDAGCEn 0x200000
870 #define bRxHTRxHP_BBP 0x1c00000
871 #define bRxHTRxHP_Final 0xe0000000
872 #define bRxPWRatioTH 0x3
873 #define bRxPWRatioEn 0x4
874 #define bRxMFHold 0x3800
875 #define bRxPD_Delay_TH1 0x38
876 #define bRxPD_Delay_TH2 0x1c0
877 #define bRxPD_DC_COUNT_MAX 0x600
878 #define bRxPD_Delay_TH 0x8000
879 #define bRxProcess_Delay 0xf0000
880 #define bRxSearchrange_GI2_Early 0x700000
881 #define bRxFrame_Guard_Counter_L 0x3800000
882 #define bRxSGI_Guard_L 0xc000000
883 #define bRxSGI_Search_L 0x30000000
884 #define bRxSGI_TH 0xc0000000
885 #define bDFSCnt0 0xff
886 #define bDFSCnt1 0xff00
887 #define bDFSFlag 0xf0000
888 #define bMFWeightSum 0x300000
889 #define bMinIdxTH 0x7f000000
890 #define bDAFormat 0x40000
891 #define bTxChEmuEnable 0x01000000
892 #define bTRSWIsolation_A 0x7f
893 #define bTRSWIsolation_B 0x7f00
894 #define bTRSWIsolation_C 0x7f0000
895 #define bTRSWIsolation_D 0x7f000000
896 #define bExtLNAGain 0x7c00
898 /* 6. PageE(0xE00) */
899 #define bSTBCEn 0x4 /* Useless */
900 #define bAntennaMapping 0x10
902 #define bCFOAntSumD 0x200
903 #define bPHYCounterReset 0x8000000
904 #define bCFOReportGet 0x4000000
905 #define bOFDMContinueTx 0x10000000
906 #define bOFDMSingleCarrier 0x20000000
907 #define bOFDMSingleTone 0x40000000
908 #define bHTDetect 0x100
909 #define bCFOEn 0x10000
910 #define bCFOValue 0xfff00000
911 #define bSigTone_Re 0x3f
912 #define bSigTone_Im 0x7f00
913 #define bCounter_CCA 0xffff
914 #define bCounter_ParityFail 0xffff0000
915 #define bCounter_RateIllegal 0xffff
916 #define bCounter_CRC8Fail 0xffff0000
917 #define bCounter_MCSNoSupport 0xffff
918 #define bCounter_FastSync 0xffff
919 #define bShortCFO 0xfff
920 #define bShortCFOTLength 12 /* total */
921 #define bShortCFOFLength 11 /* fraction */
922 #define bLongCFO 0x7ff
923 #define bLongCFOTLength 11
924 #define bLongCFOFLength 11
925 #define bTailCFO 0x1fff
926 #define bTailCFOTLength 13
927 #define bTailCFOFLength 12
928 #define bmax_en_pwdB 0xffff
929 #define bCC_power_dB 0xffff0000
930 #define bnoise_pwdB 0xffff
931 #define bPowerMeasTLength 10
932 #define bPowerMeasFLength 3
933 #define bRx_HT_BW 0x1
936 #define bNB_intf_det_on 0x1
937 #define bIntf_win_len_cfg 0x30
938 #define bNB_Intf_TH_cfg 0x1c0
940 #define bTableSel 0x40
942 #define bRxSNR_A 0xff
943 #define bRxSNR_B 0xff00
944 #define bRxSNR_C 0xff0000
945 #define bRxSNR_D 0xff000000
946 #define bSNREVMTLength 8
947 #define bSNREVMFLength 1
949 #define bCSI2nd 0xff00
950 #define bRxEVM1st 0xff0000
951 #define bRxEVM2nd 0xff000000
954 #define bSGIEN 0x10000
956 #define bSFactorQAM1 0xf /* Useless */
957 #define bSFactorQAM2 0xf0
958 #define bSFactorQAM3 0xf00
959 #define bSFactorQAM4 0xf000
960 #define bSFactorQAM5 0xf0000
961 #define bSFactorQAM6 0xf0000
962 #define bSFactorQAM7 0xf00000
963 #define bSFactorQAM8 0xf000000
964 #define bSFactorQAM9 0xf0000000
965 #define bCSIScheme 0x100000
967 #define bNoiseLvlTopSet 0x3 /* Useless */
968 #define bChSmooth 0x4
969 #define bChSmoothCfg1 0x38
970 #define bChSmoothCfg2 0x1c0
971 #define bChSmoothCfg3 0xe00
972 #define bChSmoothCfg4 0x7000
973 #define bMRCMode 0x800000
974 #define bTHEVMCfg 0x7000000
976 #define bLoopFitType 0x1 /* Useless */
978 #define bUpdCFOOffData 0x80
979 #define bAdvUpdCFO 0x100
980 #define bAdvTimeCtrl 0x800
981 #define bUpdClko 0x1000
983 #define bTrackingMode 0x8000
984 #define bPhCmpEnable 0x10000
985 #define bUpdClkoLTF 0x20000
986 #define bComChCFO 0x40000
987 #define bCSIEstiMode 0x80000
988 #define bAdvUpdEqz 0x100000
989 #define bUChCfg 0x7000000
990 #define bUpdEqz 0x8000000
992 /* Rx Pseduo noise */
993 #define bRxPesudoNoiseOn 0x20000000 /* Useless */
994 #define bRxPesudoNoise_A 0xff
995 #define bRxPesudoNoise_B 0xff00
996 #define bRxPesudoNoise_C 0xff0000
997 #define bRxPesudoNoise_D 0xff000000
998 #define bPesudoNoiseState_A 0xffff
999 #define bPesudoNoiseState_B 0xffff0000
1000 #define bPesudoNoiseState_C 0xffff
1001 #define bPesudoNoiseState_D 0xffff0000
1003 /* 7. RF Register */
1005 #define bZebra1_HSSIEnable 0x8 /* Useless */
1006 #define bZebra1_TRxControl 0xc00
1007 #define bZebra1_TRxGainSetting 0x07f
1008 #define bZebra1_RxCorner 0xc00
1009 #define bZebra1_TxChargePump 0x38
1010 #define bZebra1_RxChargePump 0x7
1011 #define bZebra1_ChannelNum 0xf80
1012 #define bZebra1_TxLPFBW 0x400
1013 #define bZebra1_RxLPFBW 0x600
1016 #define bRTL8256RegModeCtrl1 0x100 /* Useless */
1017 #define bRTL8256RegModeCtrl0 0x40
1018 #define bRTL8256_TxLPFBW 0x18
1019 #define bRTL8256_RxLPFBW 0x600
1022 #define bRTL8258_TxLPFBW 0xc /* Useless */
1023 #define bRTL8258_RxLPFBW 0xc00
1024 #define bRTL8258_RSSILPFBW 0xc0
1028 /* Other Definition */
1031 /* byte endable for sb_write */
1032 #define bByte0 0x1 /* Useless */
1040 /* for PutRegsetting & GetRegSetting BitMask */
1041 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1042 #define bMaskByte1 0xff00
1043 #define bMaskByte2 0xff0000
1044 #define bMaskByte3 0xff000000
1045 #define bMaskHWord 0xffff0000
1046 #define bMaskLWord 0x0000ffff
1047 #define bMaskDWord 0xffffffff
1048 #define bMask12Bits 0xfff
1049 #define bMaskH4Bits 0xf0000000
1050 #define bMaskOFDM_D 0xffc00000
1051 #define bMaskCCK 0x3f3f3f3f
1053 /* for PutRFRegsetting & GetRFRegSetting BitMask */
1054 #define bRFRegOffsetMask 0xfffff
1056 #define bEnable 0x1 /* Useless */
1057 #define bDisable 0x0
1059 #define LeftAntenna 0x0 /* Useless */
1060 #define RightAntenna 0x1
1062 #define tCheckTxStatus 500 /* 500ms Useless */
1063 #define tUpdateRxCounter 100 /* 100ms */
1065 #define rateCCK 0 /* Useless */
1069 /* define Register-End */
1070 #define bPMAC_End 0x1ff /* Useless */
1071 #define bFPGAPHY0_End 0x8ff
1072 #define bFPGAPHY1_End 0x9ff
1073 #define bCCKPHY0_End 0xaff
1074 #define bOFDMPHY0_End 0xcff
1075 #define bOFDMPHY1_End 0xdff
1077 #define bPMACControl 0x0 /* Useless */
1078 #define bWMACControl 0x1
1079 #define bWNICControl 0x2
1081 #define PathA 0x0 /* Useless */
1086 /*--------------------------Define Parameters-------------------------------*/