1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
16 #include "odm_precomp.h"
22 static u32 array_agc_tab_1t_8188e[] = {
153 static bool set_baseband_agc_config(struct adapter *adapt)
156 const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
157 u32 *array = array_agc_tab_1t_8188e;
159 for (i = 0; i < arraylen; i += 2) {
161 u32 v2 = array[i + 1];
163 if (v1 < 0xCDCDCDCD) {
164 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
173 static u32 array_phy_reg_1t_8188e[] = {
367 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
371 } else if (addr == 0xfd) {
373 } else if (addr == 0xfc) {
375 } else if (addr == 0xfb) {
377 } else if (addr == 0xfa) {
379 } else if (addr == 0xf9) {
382 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
383 /* Add 1us delay between BB/RF register setting. */
388 static bool set_baseband_phy_config(struct adapter *adapt)
391 const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
392 u32 *array = array_phy_reg_1t_8188e;
394 for (i = 0; i < arraylen; i += 2) {
396 u32 v2 = array[i + 1];
399 rtl_bb_delay(adapt, v1, v2);
406 static u32 array_phy_reg_pg_8188e[] = {
407 0xE00, 0xFFFFFFFF, 0x06070809,
408 0xE04, 0xFFFFFFFF, 0x02020405,
409 0xE08, 0x0000FF00, 0x00000006,
410 0x86C, 0xFFFFFF00, 0x00020400,
411 0xE10, 0xFFFFFFFF, 0x08090A0B,
412 0xE14, 0xFFFFFFFF, 0x01030607,
413 0xE18, 0xFFFFFFFF, 0x08090A0B,
414 0xE1C, 0xFFFFFFFF, 0x01030607,
415 0xE00, 0xFFFFFFFF, 0x00000000,
416 0xE04, 0xFFFFFFFF, 0x00000000,
417 0xE08, 0x0000FF00, 0x00000000,
418 0x86C, 0xFFFFFF00, 0x00000000,
419 0xE10, 0xFFFFFFFF, 0x00000000,
420 0xE14, 0xFFFFFFFF, 0x00000000,
421 0xE18, 0xFFFFFFFF, 0x00000000,
422 0xE1C, 0xFFFFFFFF, 0x00000000,
423 0xE00, 0xFFFFFFFF, 0x02020202,
424 0xE04, 0xFFFFFFFF, 0x00020202,
425 0xE08, 0x0000FF00, 0x00000000,
426 0x86C, 0xFFFFFF00, 0x00000000,
427 0xE10, 0xFFFFFFFF, 0x04040404,
428 0xE14, 0xFFFFFFFF, 0x00020404,
429 0xE18, 0xFFFFFFFF, 0x00000000,
430 0xE1C, 0xFFFFFFFF, 0x00000000,
431 0xE00, 0xFFFFFFFF, 0x02020202,
432 0xE04, 0xFFFFFFFF, 0x00020202,
433 0xE08, 0x0000FF00, 0x00000000,
434 0x86C, 0xFFFFFF00, 0x00000000,
435 0xE10, 0xFFFFFFFF, 0x04040404,
436 0xE14, 0xFFFFFFFF, 0x00020404,
437 0xE18, 0xFFFFFFFF, 0x00000000,
438 0xE1C, 0xFFFFFFFF, 0x00000000,
439 0xE00, 0xFFFFFFFF, 0x00000000,
440 0xE04, 0xFFFFFFFF, 0x00000000,
441 0xE08, 0x0000FF00, 0x00000000,
442 0x86C, 0xFFFFFF00, 0x00000000,
443 0xE10, 0xFFFFFFFF, 0x00000000,
444 0xE14, 0xFFFFFFFF, 0x00000000,
445 0xE18, 0xFFFFFFFF, 0x00000000,
446 0xE1C, 0xFFFFFFFF, 0x00000000,
447 0xE00, 0xFFFFFFFF, 0x02020202,
448 0xE04, 0xFFFFFFFF, 0x00020202,
449 0xE08, 0x0000FF00, 0x00000000,
450 0x86C, 0xFFFFFF00, 0x00000000,
451 0xE10, 0xFFFFFFFF, 0x04040404,
452 0xE14, 0xFFFFFFFF, 0x00020404,
453 0xE18, 0xFFFFFFFF, 0x00000000,
454 0xE1C, 0xFFFFFFFF, 0x00000000,
455 0xE00, 0xFFFFFFFF, 0x00000000,
456 0xE04, 0xFFFFFFFF, 0x00000000,
457 0xE08, 0x0000FF00, 0x00000000,
458 0x86C, 0xFFFFFF00, 0x00000000,
459 0xE10, 0xFFFFFFFF, 0x00000000,
460 0xE14, 0xFFFFFFFF, 0x00000000,
461 0xE18, 0xFFFFFFFF, 0x00000000,
462 0xE1C, 0xFFFFFFFF, 0x00000000,
463 0xE00, 0xFFFFFFFF, 0x00000000,
464 0xE04, 0xFFFFFFFF, 0x00000000,
465 0xE08, 0x0000FF00, 0x00000000,
466 0x86C, 0xFFFFFF00, 0x00000000,
467 0xE10, 0xFFFFFFFF, 0x00000000,
468 0xE14, 0xFFFFFFFF, 0x00000000,
469 0xE18, 0xFFFFFFFF, 0x00000000,
470 0xE1C, 0xFFFFFFFF, 0x00000000,
471 0xE00, 0xFFFFFFFF, 0x00000000,
472 0xE04, 0xFFFFFFFF, 0x00000000,
473 0xE08, 0x0000FF00, 0x00000000,
474 0x86C, 0xFFFFFF00, 0x00000000,
475 0xE10, 0xFFFFFFFF, 0x00000000,
476 0xE14, 0xFFFFFFFF, 0x00000000,
477 0xE18, 0xFFFFFFFF, 0x00000000,
478 0xE1C, 0xFFFFFFFF, 0x00000000,
479 0xE00, 0xFFFFFFFF, 0x00000000,
480 0xE04, 0xFFFFFFFF, 0x00000000,
481 0xE08, 0x0000FF00, 0x00000000,
482 0x86C, 0xFFFFFF00, 0x00000000,
483 0xE10, 0xFFFFFFFF, 0x00000000,
484 0xE14, 0xFFFFFFFF, 0x00000000,
485 0xE18, 0xFFFFFFFF, 0x00000000,
486 0xE1C, 0xFFFFFFFF, 0x00000000,
487 0xE00, 0xFFFFFFFF, 0x00000000,
488 0xE04, 0xFFFFFFFF, 0x00000000,
489 0xE08, 0x0000FF00, 0x00000000,
490 0x86C, 0xFFFFFF00, 0x00000000,
491 0xE10, 0xFFFFFFFF, 0x00000000,
492 0xE14, 0xFFFFFFFF, 0x00000000,
493 0xE18, 0xFFFFFFFF, 0x00000000,
494 0xE1C, 0xFFFFFFFF, 0x00000000,
498 static void store_pwrindex_offset(struct adapter *adapter,
499 u32 regaddr, u32 bitmask, u32 data)
501 struct hal_data_8188e *hal_data = adapter->HalData;
502 u32 * const power_level_offset =
503 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
505 if (regaddr == rTxAGC_A_Rate18_06)
506 power_level_offset[0] = data;
507 if (regaddr == rTxAGC_A_Rate54_24)
508 power_level_offset[1] = data;
509 if (regaddr == rTxAGC_A_CCK1_Mcs32)
510 power_level_offset[6] = data;
511 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
512 power_level_offset[7] = data;
513 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
514 power_level_offset[2] = data;
515 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
516 power_level_offset[3] = data;
517 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
518 power_level_offset[4] = data;
519 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
520 power_level_offset[5] = data;
521 hal_data->pwrGroupCnt++;
523 if (regaddr == rTxAGC_B_Rate18_06)
524 power_level_offset[8] = data;
525 if (regaddr == rTxAGC_B_Rate54_24)
526 power_level_offset[9] = data;
527 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
528 power_level_offset[14] = data;
529 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
530 power_level_offset[15] = data;
531 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
532 power_level_offset[10] = data;
533 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
534 power_level_offset[11] = data;
535 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
536 power_level_offset[12] = data;
537 if (regaddr == rTxAGC_B_Mcs15_Mcs12)
538 power_level_offset[13] = data;
541 static void rtl_addr_delay(struct adapter *adapt,
542 u32 addr, u32 bit_mask, u32 data)
564 store_pwrindex_offset(adapt, addr, bit_mask, data);
568 static bool config_bb_with_pgheader(struct adapter *adapt)
571 const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
572 u32 *array = array_phy_reg_pg_8188e;
574 for (i = 0; i < arraylen; i += 3) {
576 u32 v2 = array[i + 1];
577 u32 v3 = array[i + 2];
580 rtl_addr_delay(adapt, v1, v2, v3);
585 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
587 struct bb_reg_def *reg[4];
589 reg[RF_PATH_A] = &adapter->HalData->PHYRegDef[RF_PATH_A];
590 reg[RF_PATH_B] = &adapter->HalData->PHYRegDef[RF_PATH_B];
592 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
593 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
595 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
596 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
598 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
599 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
601 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
602 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
604 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
605 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
607 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
608 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
610 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
611 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
613 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
614 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
616 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
617 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
619 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
620 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
622 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
623 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
625 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
626 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
628 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
629 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
631 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
632 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
634 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
635 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
637 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
638 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
640 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
641 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
643 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
644 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
647 static bool config_parafile(struct adapter *adapt)
649 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
651 set_baseband_phy_config(adapt);
653 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
654 if (!eeprom->bautoload_fail_flag) {
655 adapt->HalData->pwrGroupCnt = 0;
656 config_bb_with_pgheader(adapt);
658 set_baseband_agc_config(adapt);
662 bool rtl88eu_phy_bb_config(struct adapter *adapt)
668 rtl88e_phy_init_bb_rf_register_definition(adapt);
670 /* Enable BB and RF */
671 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
672 usb_write16(adapt, REG_SYS_FUNC_EN,
673 (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
675 usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
677 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
678 FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
680 /* Config BB and AGC */
681 rtstatus = config_parafile(adapt);
683 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
684 crystal_cap = adapt->HalData->CrystalCap & 0x3F;
685 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
686 (crystal_cap | (crystal_cap << 6)));