2 * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
4 * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
5 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
8 * Some parts are based on spi-orion.c:
9 * Author: Shadi Ammouri <shadi@marvell.com>
10 * Copyright (C) 2007-2008 Marvell Ltd.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/delay.h>
23 #include <linux/reset.h>
24 #include <linux/spi/spi.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/swab.h>
29 #include <ralink_regs.h>
31 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
33 #define DRIVER_NAME "spi-mt7621"
35 #define RALINK_SPI_WAIT_MAX_LOOP 2000
37 /* SPISTAT register bit field */
38 #define SPISTAT_BUSY BIT(0)
40 #define MT7621_SPI_TRANS 0x00
41 #define SPITRANS_BUSY BIT(16)
43 #define MT7621_SPI_OPCODE 0x04
44 #define MT7621_SPI_DATA0 0x08
45 #define MT7621_SPI_DATA4 0x18
46 #define SPI_CTL_TX_RX_CNT_MASK 0xff
47 #define SPI_CTL_START BIT(8)
49 #define MT7621_SPI_POLAR 0x38
50 #define MT7621_SPI_MASTER 0x28
51 #define MT7621_SPI_MOREBUF 0x2c
52 #define MT7621_SPI_SPACE 0x3c
54 #define MT7621_CPHA BIT(5)
55 #define MT7621_CPOL BIT(4)
56 #define MT7621_LSB_FIRST BIT(3)
58 #define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | \
59 SPI_LSB_FIRST | SPI_CS_HIGH)
64 struct spi_master *master;
66 unsigned int sys_freq;
71 struct mt7621_spi_ops *ops;
74 static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
76 return spi_master_get_devdata(spi->master);
79 static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
81 return ioread32(rs->base + reg);
84 static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
86 iowrite32(val, rs->base + reg);
89 static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
91 u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
100 mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
101 rs->pending_write = 0;
104 static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
106 struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
107 int cs = spi->chip_select;
110 mt7621_spi_reset(rs, cs);
113 mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
116 static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
118 struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
122 dev_dbg(&spi->dev, "speed:%u\n", speed);
124 rate = DIV_ROUND_UP(rs->sys_freq, speed);
125 dev_dbg(&spi->dev, "rate-1:%u\n", rate);
133 reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
134 reg &= ~(0xfff << 16);
135 reg |= (rate - 2) << 16;
138 reg &= ~MT7621_LSB_FIRST;
139 if (spi->mode & SPI_LSB_FIRST)
140 reg |= MT7621_LSB_FIRST;
142 reg &= ~(MT7621_CPHA | MT7621_CPOL);
143 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
153 reg |= MT7621_CPOL | MT7621_CPHA;
156 mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
161 static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
165 for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
168 status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
169 if ((status & SPITRANS_BUSY) == 0)
178 static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
181 /* Combine with any pending write, and perform one or
182 * more half-duplex transactions reading 'len' bytes.
183 * Data to be written is already in MT7621_SPI_DATA*
185 int tx_len = rs->pending_write;
187 rs->pending_write = 0;
189 while (rx_len || tx_len) {
191 u32 val = (min(tx_len, 4) * 8) << 24;
192 int rx = min(rx_len, 32);
195 val |= (tx_len - 4) * 8;
196 val |= (rx * 8) << 12;
197 mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
201 val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
202 val |= SPI_CTL_START;
203 mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
205 mt7621_spi_wait_till_ready(rs);
207 for (i = 0; i < rx; i++) {
209 val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
217 static inline void mt7621_spi_flush(struct mt7621_spi *rs)
219 mt7621_spi_read_half_duplex(rs, 0, NULL);
222 static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
223 int tx_len, const u8 *buf)
226 int len = rs->pending_write;
229 val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
231 val <<= (4 - len) * 8;
238 rs->pending_write = len;
239 mt7621_spi_flush(rs);
243 val |= *buf++ << (8 * (len & 3));
245 if ((len & 3) == 0) {
247 /* The byte-order of the opcode is weird! */
249 mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
257 val >>= (4 - len) * 8;
259 mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
261 rs->pending_write = len;
264 static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
265 struct spi_message *m)
267 struct mt7621_spi *rs = spi_master_get_devdata(master);
268 struct spi_device *spi = m->spi;
269 unsigned int speed = spi->max_speed_hz;
270 struct spi_transfer *t = NULL;
273 mt7621_spi_wait_till_ready(rs);
275 list_for_each_entry(t, &m->transfers, transfer_list)
276 if (t->speed_hz < speed)
279 if (mt7621_spi_prepare(spi, speed)) {
284 mt7621_spi_set_cs(spi, 1);
285 m->actual_length = 0;
286 list_for_each_entry(t, &m->transfers, transfer_list) {
288 mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
290 mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
291 m->actual_length += t->len;
293 mt7621_spi_flush(rs);
295 mt7621_spi_set_cs(spi, 0);
298 spi_finalize_current_message(master);
303 static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
304 struct spi_message *m)
306 struct mt7621_spi *rs = spi_master_get_devdata(master);
307 struct spi_device *spi = m->spi;
308 unsigned int speed = spi->max_speed_hz;
309 struct spi_transfer *t = NULL;
316 mt7621_spi_wait_till_ready(rs);
318 list_for_each_entry(t, &m->transfers, transfer_list) {
319 const u8 *buf = t->tx_buf;
327 if (WARN_ON(len + t->len > 16)) {
332 for (i = 0; i < t->len; i++, len++)
333 data[len / 4] |= buf[i] << (8 * (len & 3));
334 if (speed > t->speed_hz)
338 if (WARN_ON(rx_len > 16)) {
343 if (mt7621_spi_prepare(spi, speed)) {
348 for (i = 0; i < len; i += 4)
349 mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
352 val |= (rx_len * 8) << 12;
353 mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
355 mt7621_spi_set_cs(spi, 1);
357 val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
358 val |= SPI_CTL_START;
359 mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
361 mt7621_spi_wait_till_ready(rs);
363 mt7621_spi_set_cs(spi, 0);
365 for (i = 0; i < rx_len; i += 4)
366 data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
368 m->actual_length = rx_len;
371 list_for_each_entry(t, &m->transfers, transfer_list) {
377 for (i = 0; i < t->len; i++, len++)
378 buf[i] = data[len / 4] >> (8 * (len & 3));
383 spi_finalize_current_message(master);
388 static int mt7621_spi_transfer_one_message(struct spi_master *master,
389 struct spi_message *m)
391 struct spi_device *spi = m->spi;
392 int cs = spi->chip_select;
395 return mt7621_spi_transfer_full_duplex(master, m);
396 return mt7621_spi_transfer_half_duplex(master, m);
399 static int mt7621_spi_setup(struct spi_device *spi)
401 struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
403 if ((spi->max_speed_hz == 0) ||
404 (spi->max_speed_hz > (rs->sys_freq / 2)))
405 spi->max_speed_hz = (rs->sys_freq / 2);
407 if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
408 dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
416 static const struct of_device_id mt7621_spi_match[] = {
417 { .compatible = "ralink,mt7621-spi" },
420 MODULE_DEVICE_TABLE(of, mt7621_spi_match);
422 static int mt7621_spi_probe(struct platform_device *pdev)
424 const struct of_device_id *match;
425 struct spi_master *master;
426 struct mt7621_spi *rs;
431 struct mt7621_spi_ops *ops;
434 match = of_match_device(mt7621_spi_match, &pdev->dev);
437 ops = (struct mt7621_spi_ops *)match->data;
439 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440 base = devm_ioremap_resource(&pdev->dev, r);
442 return PTR_ERR(base);
444 clk = devm_clk_get(&pdev->dev, NULL);
446 dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
451 status = clk_prepare_enable(clk);
455 master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
456 if (master == NULL) {
457 dev_info(&pdev->dev, "master allocation failed\n");
458 clk_disable_unprepare(clk);
462 master->mode_bits = RT2880_SPI_MODE_BITS;
464 master->setup = mt7621_spi_setup;
465 master->transfer_one_message = mt7621_spi_transfer_one_message;
466 master->bits_per_word_mask = SPI_BPW_MASK(8);
467 master->dev.of_node = pdev->dev.of_node;
468 master->num_chipselect = 2;
470 dev_set_drvdata(&pdev->dev, master);
472 rs = spi_master_get_devdata(master);
476 rs->sys_freq = clk_get_rate(rs->clk);
478 rs->pending_write = 0;
479 dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
481 ret = device_reset(&pdev->dev);
483 dev_err(&pdev->dev, "SPI reset failed!\n");
484 clk_disable_unprepare(clk);
488 mt7621_spi_reset(rs, 0);
490 ret = spi_register_master(master);
492 clk_disable_unprepare(clk);
497 static int mt7621_spi_remove(struct platform_device *pdev)
499 struct spi_master *master;
500 struct mt7621_spi *rs;
502 master = dev_get_drvdata(&pdev->dev);
503 rs = spi_master_get_devdata(master);
505 spi_unregister_master(master);
506 clk_disable_unprepare(rs->clk);
511 MODULE_ALIAS("platform:" DRIVER_NAME);
513 static struct platform_driver mt7621_spi_driver = {
516 .of_match_table = mt7621_spi_match,
518 .probe = mt7621_spi_probe,
519 .remove = mt7621_spi_remove,
522 module_platform_driver(mt7621_spi_driver);
524 MODULE_DESCRIPTION("MT7621 SPI driver");
525 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
526 MODULE_LICENSE("GPL");