1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/if_vlan.h>
18 #include <linux/of_net.h>
20 #include <asm/mach-ralink/ralink_regs.h>
22 #include "mtk_eth_soc.h"
23 #include "gsw_mt7620.h"
26 #define MT7620_CDMA_CSG_CFG 0x400
27 #define MT7621_CDMP_IG_CTRL (MT7620_CDMA_CSG_CFG + 0x00)
28 #define MT7621_CDMP_EG_CTRL (MT7620_CDMA_CSG_CFG + 0x04)
29 #define MT7621_RESET_FE BIT(6)
30 #define MT7621_L4_VALID BIT(24)
32 #define MT7621_TX_DMA_UDF BIT(19)
34 #define CDMA_ICS_EN BIT(2)
35 #define CDMA_UCS_EN BIT(1)
36 #define CDMA_TCS_EN BIT(0)
38 #define GDMA_ICS_EN BIT(22)
39 #define GDMA_TCS_EN BIT(21)
40 #define GDMA_UCS_EN BIT(20)
42 /* frame engine counters */
43 #define MT7621_REG_MIB_OFFSET 0x2000
44 #define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
45 #define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
46 #define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
48 #define GSW_REG_GDMA1_MAC_ADRL 0x508
49 #define GSW_REG_GDMA1_MAC_ADRH 0x50C
50 #define GSW_REG_GDMA2_MAC_ADRL 0x1508
51 #define GSW_REG_GDMA2_MAC_ADRH 0x150C
53 #define MT7621_MTK_RST_GL 0x04
54 #define MT7620_MTK_INT_STATUS2 0x08
56 /* MTK_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
57 * but after test it should be BIT(13).
59 #define MT7621_MTK_GDM1_AF BIT(28)
60 #define MT7621_MTK_GDM2_AF BIT(29)
62 static const u16 mt7621_reg_table[MTK_REG_COUNT] = {
63 [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
64 [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
65 [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
66 [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
67 [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
68 [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
69 [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
70 [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
71 [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
72 [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
73 [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
74 [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
75 [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
76 [MTK_REG_MTK_DMA_VID_BASE] = 0,
77 [MTK_REG_MTK_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
78 [MTK_REG_MTK_RST_GL] = MT7621_MTK_RST_GL,
79 [MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2,
82 static void mt7621_mtk_reset(struct mtk_eth *eth)
84 mtk_reset(eth, MT7621_RESET_FE);
87 static int mt7621_fwd_config(struct mtk_eth *eth)
89 /* Setup GMAC1 only, there is no support for GMAC2 yet */
90 mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) & ~0xffff,
91 MT7620_GDMA1_FWD_CFG);
93 /* Enable RX checksum */
94 mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
95 GDMA_TCS_EN | GDMA_UCS_EN),
96 MT7620_GDMA1_FWD_CFG);
98 /* Enable RX VLan Offloading */
99 mtk_w32(eth, 0, MT7621_CDMP_EG_CTRL);
104 static void mt7621_set_mac(struct mtk_mac *mac, unsigned char *hwaddr)
108 spin_lock_irqsave(&mac->hw->page_lock, flags);
110 mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1],
111 GSW_REG_GDMA1_MAC_ADRH);
112 mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
113 (hwaddr[4] << 8) | hwaddr[5],
114 GSW_REG_GDMA1_MAC_ADRL);
117 mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1],
118 GSW_REG_GDMA2_MAC_ADRH);
119 mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
120 (hwaddr[4] << 8) | hwaddr[5],
121 GSW_REG_GDMA2_MAC_ADRL);
123 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
126 static struct mtk_soc_data mt7621_data = {
127 .hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
128 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
129 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
131 .dma_type = MTK_PDMA,
132 .dma_ring_size = 256,
140 .reset_fe = mt7621_mtk_reset,
141 .set_mac = mt7621_set_mac,
142 .fwd_config = mt7621_fwd_config,
143 .switch_init = mtk_gsw_init,
144 .reg_table = mt7621_reg_table,
145 .pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS,
146 .rx_int = RT5350_RX_DONE_INT,
147 .tx_int = RT5350_TX_DONE_INT,
148 .status_int = MT7621_MTK_GDM1_AF | MT7621_MTK_GDM2_AF,
149 .checksum_bit = MT7621_L4_VALID,
150 .has_carrier = mt7620_has_carrier,
151 .mdio_read = mt7620_mdio_read,
152 .mdio_write = mt7620_mdio_write,
153 .mdio_adjust_link = mt7620_mdio_link_adjust,
156 const struct of_device_id of_mtk_match[] = {
157 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
161 MODULE_DEVICE_TABLE(of, of_mtk_match);