1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #ifndef _RALINK_GSW_MT7620_H__
16 #define _RALINK_GSW_MT7620_H__
18 #define GSW_REG_PHY_TIMEOUT (5 * HZ)
20 #define MT7620_GSW_REG_PIAC 0x0004
22 #define GSW_NUM_VLANS 16
23 #define GSW_NUM_VIDS 4096
24 #define GSW_NUM_PORTS 7
27 #define GSW_MDIO_ACCESS BIT(31)
28 #define GSW_MDIO_READ BIT(19)
29 #define GSW_MDIO_WRITE BIT(18)
30 #define GSW_MDIO_START BIT(16)
31 #define GSW_MDIO_ADDR_SHIFT 20
32 #define GSW_MDIO_REG_SHIFT 25
34 #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
35 #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
36 #define GSW_REG_SMACCR0 0x3fE4
37 #define GSW_REG_SMACCR1 0x3fE8
38 #define GSW_REG_CKGCR 0x3ff0
40 #define GSW_REG_IMR 0x7008
41 #define GSW_REG_ISR 0x700c
42 #define GSW_REG_GPC1 0x7014
44 #define SYSC_REG_CHIP_REV_ID 0x0c
45 #define SYSC_REG_CFG 0x10
46 #define SYSC_REG_CFG1 0x14
47 #define RST_CTRL_MCM BIT(2)
48 #define SYSC_PAD_RGMII2_MDIO 0x58
49 #define SYSC_GPIO_MODE 0x60
51 #define PORT_IRQ_ST_CHG 0x7f
53 #define MT7621_ESW_PHY_POLLING 0x0000
54 #define MT7620_ESW_PHY_POLLING 0x7000
56 #define PMCR_IPG BIT(18)
57 #define PMCR_MAC_MODE BIT(16)
58 #define PMCR_FORCE BIT(15)
59 #define PMCR_TX_EN BIT(14)
60 #define PMCR_RX_EN BIT(13)
61 #define PMCR_BACKOFF BIT(9)
62 #define PMCR_BACKPRES BIT(8)
63 #define PMCR_RX_FC BIT(5)
64 #define PMCR_TX_FC BIT(4)
65 #define PMCR_SPEED(_x) (_x << 2)
66 #define PMCR_DUPLEX BIT(1)
67 #define PMCR_LINK BIT(0)
69 #define PHY_AN_EN BIT(31)
70 #define PHY_PRE_EN BIT(30)
71 #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
73 /* ethernet subsystem config register */
74 #define ETHSYS_SYSCFG0 0x14
75 /* ethernet subsystem clock register */
76 #define ETHSYS_CLKCFG0 0x2c
77 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
79 /* p5 RGMII wrapper TX clock control register */
80 #define MT7530_P5RGMIITXCR 0x7b04
81 /* p5 RGMII wrapper RX clock control register */
82 #define MT7530_P5RGMIIRXCR 0x7b00
83 /* TRGMII TDX ODT registers */
84 #define MT7530_TRGMII_TD0_ODT 0x7a54
85 #define MT7530_TRGMII_TD1_ODT 0x7a5c
86 #define MT7530_TRGMII_TD2_ODT 0x7a64
87 #define MT7530_TRGMII_TD3_ODT 0x7a6c
88 #define MT7530_TRGMII_TD4_ODT 0x7a74
89 #define MT7530_TRGMII_TD5_ODT 0x7a7c
90 /* TRGMII TCK ctrl register */
91 #define MT7530_TRGMII_TCK_CTRL 0x7a78
92 /* TRGMII Tx ctrl register */
93 #define MT7530_TRGMII_TXCTRL 0x7a40
94 /* port 6 extended control register */
95 #define MT7530_P6ECR 0x7830
96 /* IO driver control register */
97 #define MT7530_IO_DRV_CR 0x7810
98 /* top signal control register */
99 #define MT7530_TOP_SIG_CTRL 0x7808
100 /* modified hwtrap register */
101 #define MT7530_MHWTRAP 0x7804
102 /* hwtrap status register */
103 #define MT7530_HWTRAP 0x7800
104 /* status interrupt register */
105 #define MT7530_SYS_INT_STS 0x700c
106 /* system nterrupt register */
107 #define MT7530_SYS_INT_EN 0x7008
108 /* system control register */
109 #define MT7530_SYS_CTRL 0x7000
110 /* port MAC status register */
111 #define MT7530_PMSR_P(x) (0x3008 + (x * 0x100))
112 /* port MAC control register */
113 #define MT7530_PMCR_P(x) (0x3000 + (x * 0x100))
115 #define MT7621_XTAL_SHIFT 6
116 #define MT7621_XTAL_MASK 0x7
117 #define MT7621_XTAL_25 6
118 #define MT7621_XTAL_40 3
119 #define MT7621_MDIO_DRV_MASK (3 << 4)
120 #define MT7621_GE1_MODE_MASK (3 << 12)
122 #define TRGMII_TXCTRL_TXC_INV BIT(30)
123 #define P6ECR_INTF_MODE_RGMII BIT(1)
124 #define P5RGMIIRXCR_C_ALIGN BIT(8)
125 #define P5RGMIIRXCR_DELAY_2 BIT(1)
126 #define P5RGMIITXCR_DELAY_2 (BIT(8) | BIT(2))
128 /* TOP_SIG_CTRL bits */
129 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
132 #define MHWTRAP_MANUAL BIT(16)
133 #define MHWTRAP_P5_MAC_SEL BIT(13)
134 #define MHWTRAP_P6_DIS BIT(8)
135 #define MHWTRAP_P5_RGMII_MODE BIT(7)
136 #define MHWTRAP_P5_DIS BIT(6)
137 #define MHWTRAP_PHY_ACCESS BIT(5)
140 #define HWTRAP_XTAL_SHIFT 9
141 #define HWTRAP_XTAL_MASK 0x3
144 #define SYS_CTRL_SW_RST BIT(1)
145 #define SYS_CTRL_REG_RST BIT(0)
148 #define PMCR_IFG_XMIT_96 BIT(18)
149 #define PMCR_MAC_MODE BIT(16)
150 #define PMCR_FORCE_MODE BIT(15)
151 #define PMCR_TX_EN BIT(14)
152 #define PMCR_RX_EN BIT(13)
153 #define PMCR_BACK_PRES_EN BIT(9)
154 #define PMCR_BACKOFF_EN BIT(8)
155 #define PMCR_TX_FC_EN BIT(5)
156 #define PMCR_RX_FC_EN BIT(4)
157 #define PMCR_FORCE_SPEED_1000 BIT(3)
158 #define PMCR_FORCE_FDX BIT(1)
159 #define PMCR_FORCE_LNK BIT(0)
160 #define PMCR_FIXED_LINK (PMCR_IFG_XMIT_96 | PMCR_MAC_MODE | \
161 PMCR_FORCE_MODE | PMCR_TX_EN | PMCR_RX_EN | \
162 PMCR_BACK_PRES_EN | PMCR_BACKOFF_EN | \
163 PMCR_FORCE_SPEED_1000 | PMCR_FORCE_FDX | \
166 #define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
167 PMCR_TX_FC_EN | PMCR_RX_FC_EN)
169 /* TRGMII control registers */
170 #define GSW_INTF_MODE 0x390
171 #define GSW_TRGMII_TD0_ODT 0x354
172 #define GSW_TRGMII_TD1_ODT 0x35c
173 #define GSW_TRGMII_TD2_ODT 0x364
174 #define GSW_TRGMII_TD3_ODT 0x36c
175 #define GSW_TRGMII_TXCTL_ODT 0x374
176 #define GSW_TRGMII_TCK_ODT 0x37c
177 #define GSW_TRGMII_RCK_CTRL 0x300
179 #define INTF_MODE_TRGMII BIT(1)
180 #define TRGMII_RCK_CTRL_RX_RST BIT(31)
182 /* Mac control registers */
183 #define MTK_MAC_P2_MCR 0x200
184 #define MTK_MAC_P1_MCR 0x100
186 #define MAC_MCR_MAX_RX_2K BIT(29)
187 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
188 #define MAC_MCR_FORCE_MODE BIT(15)
189 #define MAC_MCR_TX_EN BIT(14)
190 #define MAC_MCR_RX_EN BIT(13)
191 #define MAC_MCR_BACKOFF_EN BIT(9)
192 #define MAC_MCR_BACKPR_EN BIT(8)
193 #define MAC_MCR_FORCE_RX_FC BIT(5)
194 #define MAC_MCR_FORCE_TX_FC BIT(4)
195 #define MAC_MCR_SPEED_1000 BIT(3)
196 #define MAC_MCR_FORCE_DPX BIT(1)
197 #define MAC_MCR_FORCE_LINK BIT(0)
198 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_2K | MAC_MCR_IPG_CFG | \
199 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
200 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
201 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
202 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
203 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
204 #define MAC_MCR_FIXED_LINK_FC (MAC_MCR_MAX_RX_2K | MAC_MCR_IPG_CFG | \
207 /* possible XTAL speed */
208 #define MT7623_XTAL_40 0
209 #define MT7623_XTAL_20 1
210 #define MT7623_XTAL_25 3
212 /* GPIO port control registers */
213 #define GPIO_OD33_CTRL8 0x4c0
214 #define GPIO_BIAS_CTRL 0xed0
215 #define GPIO_DRV_SEL10 0xf00
217 /* on MT7620 the functio of port 4 can be software configured */
223 /* struct mt7620_gsw - the structure that holds the SoC specific data
224 * @dev: The Device struct
225 * @base: The base address
226 * @piac_offset: The PIAC base may change depending on SoC
227 * @irq: The IRQ we are using
228 * @port4: The port4 mode on MT7620
229 * @autopoll: Is MDIO autopolling enabled
230 * @ethsys: The ethsys register map
231 * @pctl: The pin control register map
232 * @clk_gsw: The switch clock
233 * @clk_gp1: The gmac1 clock
234 * @clk_gp2: The gmac2 clock
235 * @clk_trgpll: The trgmii pll clock
243 unsigned long int autopoll;
245 struct regmap *ethsys;
251 struct clk *clk_trgpll;
254 /* switch register I/O wrappers */
255 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned int reg);
256 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned int reg);
258 /* the callback used by the driver core to bringup the switch */
259 int mtk_gsw_init(struct mtk_eth *eth);
261 /* MDIO access wrappers */
262 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
263 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
264 void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port);
265 int mt7620_has_carrier(struct mtk_eth *eth);
266 void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
267 int speed, int duplex);
268 void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
269 u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
270 void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg);
272 u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
273 u32 phy_register, u32 write_data);
274 u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
275 void mt7620_handle_carrier(struct mtk_eth *eth);