drivers/staging/mt7621-dma/hsdma-mt7621.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
   4  *  MTK HSDMA support
   5  */
   6
   7 #include <linux/dmaengine.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/err.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/irq.h>
  17 #include <linux/of_dma.h>
  18 #include <linux/reset.h>
  19 #include <linux/of_device.h>
  20
  21 #include "virt-dma.h"
  22
  23 #define HSDMA_BASE_OFFSET               0x800
  24
  25 #define HSDMA_REG_TX_BASE               0x00
  26 #define HSDMA_REG_TX_CNT                0x04
  27 #define HSDMA_REG_TX_CTX                0x08
  28 #define HSDMA_REG_TX_DTX                0x0c
  29 #define HSDMA_REG_RX_BASE               0x100
  30 #define HSDMA_REG_RX_CNT                0x104
  31 #define HSDMA_REG_RX_CRX                0x108
  32 #define HSDMA_REG_RX_DRX                0x10c
  33 #define HSDMA_REG_INFO                  0x200
  34 #define HSDMA_REG_GLO_CFG               0x204
  35 #define HSDMA_REG_RST_CFG               0x208
  36 #define HSDMA_REG_DELAY_INT             0x20c
  37 #define HSDMA_REG_FREEQ_THRES           0x210
  38 #define HSDMA_REG_INT_STATUS            0x220
  39 #define HSDMA_REG_INT_MASK              0x228
  40 #define HSDMA_REG_SCH_Q01               0x280
  41 #define HSDMA_REG_SCH_Q23               0x284
  42
  43 #define HSDMA_DESCS_MAX                 0xfff
  44 #define HSDMA_DESCS_NUM                 8
  45 #define HSDMA_DESCS_MASK                (HSDMA_DESCS_NUM - 1)
  46 #define HSDMA_NEXT_DESC(x)              (((x) + 1) & HSDMA_DESCS_MASK)
  47
  48 /* HSDMA_REG_INFO */
  49 #define HSDMA_INFO_INDEX_MASK           0xf
  50 #define HSDMA_INFO_INDEX_SHIFT          24
  51 #define HSDMA_INFO_BASE_MASK            0xff
  52 #define HSDMA_INFO_BASE_SHIFT           16
  53 #define HSDMA_INFO_RX_MASK              0xff
  54 #define HSDMA_INFO_RX_SHIFT             8
  55 #define HSDMA_INFO_TX_MASK              0xff
  56 #define HSDMA_INFO_TX_SHIFT             0
  57
  58 /* HSDMA_REG_GLO_CFG */
  59 #define HSDMA_GLO_TX_2B_OFFSET          BIT(31)
  60 #define HSDMA_GLO_CLK_GATE              BIT(30)
  61 #define HSDMA_GLO_BYTE_SWAP             BIT(29)
  62 #define HSDMA_GLO_MULTI_DMA             BIT(10)
  63 #define HSDMA_GLO_TWO_BUF               BIT(9)
  64 #define HSDMA_GLO_32B_DESC              BIT(8)
  65 #define HSDMA_GLO_BIG_ENDIAN            BIT(7)
  66 #define HSDMA_GLO_TX_DONE               BIT(6)
  67 #define HSDMA_GLO_BT_MASK               0x3
  68 #define HSDMA_GLO_BT_SHIFT              4
  69 #define HSDMA_GLO_RX_BUSY               BIT(3)
  70 #define HSDMA_GLO_RX_DMA                BIT(2)
  71 #define HSDMA_GLO_TX_BUSY               BIT(1)
  72 #define HSDMA_GLO_TX_DMA                BIT(0)
  73
  74 #define HSDMA_BT_SIZE_16BYTES           (0 << HSDMA_GLO_BT_SHIFT)
  75 #define HSDMA_BT_SIZE_32BYTES           (1 << HSDMA_GLO_BT_SHIFT)
  76 #define HSDMA_BT_SIZE_64BYTES           (2 << HSDMA_GLO_BT_SHIFT)
  77 #define HSDMA_BT_SIZE_128BYTES          (3 << HSDMA_GLO_BT_SHIFT)
  78
  79 #define HSDMA_GLO_DEFAULT               (HSDMA_GLO_MULTI_DMA | \
  80                 HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
  81
  82 /* HSDMA_REG_RST_CFG */
  83 #define HSDMA_RST_RX_SHIFT              16
  84 #define HSDMA_RST_TX_SHIFT              0
  85
  86 /* HSDMA_REG_DELAY_INT */
  87 #define HSDMA_DELAY_INT_EN              BIT(15)
  88 #define HSDMA_DELAY_PEND_OFFSET         8
  89 #define HSDMA_DELAY_TIME_OFFSET         0
  90 #define HSDMA_DELAY_TX_OFFSET           16
  91 #define HSDMA_DELAY_RX_OFFSET           0
  92
  93 #define HSDMA_DELAY_INIT(x)             (HSDMA_DELAY_INT_EN | \
  94                 ((x) << HSDMA_DELAY_PEND_OFFSET))
  95 #define HSDMA_DELAY(x)                  ((HSDMA_DELAY_INIT(x) << \
  96                 HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
  97
  98 /* HSDMA_REG_INT_STATUS */
  99 #define HSDMA_INT_DELAY_RX_COH          BIT(31)
 100 #define HSDMA_INT_DELAY_RX_INT          BIT(30)
 101 #define HSDMA_INT_DELAY_TX_COH          BIT(29)
 102 #define HSDMA_INT_DELAY_TX_INT          BIT(28)
 103 #define HSDMA_INT_RX_MASK               0x3
 104 #define HSDMA_INT_RX_SHIFT              16
 105 #define HSDMA_INT_RX_Q0                 BIT(16)
 106 #define HSDMA_INT_TX_MASK               0xf
 107 #define HSDMA_INT_TX_SHIFT              0
 108 #define HSDMA_INT_TX_Q0                 BIT(0)
 109
 110 /* tx/rx dma desc flags */
 111 #define HSDMA_PLEN_MASK                 0x3fff
 112 #define HSDMA_DESC_DONE                 BIT(31)
 113 #define HSDMA_DESC_LS0                  BIT(30)
 114 #define HSDMA_DESC_PLEN0(_x)            (((_x) & HSDMA_PLEN_MASK) << 16)
 115 #define HSDMA_DESC_TAG                  BIT(15)
 116 #define HSDMA_DESC_LS1                  BIT(14)
 117 #define HSDMA_DESC_PLEN1(_x)            ((_x) & HSDMA_PLEN_MASK)
 118
 119 /* align 4 bytes */
 120 #define HSDMA_ALIGN_SIZE                3
 121 /* align size 128bytes */
 122 #define HSDMA_MAX_PLEN                  0x3f80
 123
 124 struct hsdma_desc {
 125         u32 addr0;
 126         u32 flags;
 127         u32 addr1;
 128         u32 unused;
 129 };
 130
 131 struct mtk_hsdma_sg {
 132         dma_addr_t src_addr;
 133         dma_addr_t dst_addr;
 134         u32 len;
 135 };
 136
 137 struct mtk_hsdma_desc {
 138         struct virt_dma_desc vdesc;
 139         unsigned int num_sgs;
 140         struct mtk_hsdma_sg sg[1];
 141 };
 142
 143 struct mtk_hsdma_chan {
 144         struct virt_dma_chan vchan;
 145         unsigned int id;
 146         dma_addr_t desc_addr;
 147         int tx_idx;
 148         int rx_idx;
 149         struct hsdma_desc *tx_ring;
 150         struct hsdma_desc *rx_ring;
 151         struct mtk_hsdma_desc *desc;
 152         unsigned int next_sg;
 153 };
 154
 155 struct mtk_hsdam_engine {
 156         struct dma_device ddev;
 157         struct device_dma_parameters dma_parms;
 158         void __iomem *base;
 159         struct tasklet_struct task;
 160         volatile unsigned long chan_issued;
 161
 162         struct mtk_hsdma_chan chan[1];
 163 };
 164
 165 static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(
 166                 struct mtk_hsdma_chan *chan)
 167 {
 168         return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
 169                         ddev);
 170 }
 171
 172 static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
 173 {
 174         return container_of(c, struct mtk_hsdma_chan, vchan.chan);
 175 }
 176
 177 static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(
 178                 struct virt_dma_desc *vdesc)
 179 {
 180         return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
 181 }
 182
 183 static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
 184 {
 185         return readl(hsdma->base + reg);
 186 }
 187
 188 static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
 189                                    unsigned int reg, u32 val)
 190 {
 191         writel(val, hsdma->base + reg);
 192 }
 193
 194 static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
 195                                  struct mtk_hsdma_chan *chan)
 196 {
 197         chan->tx_idx = 0;
 198         chan->rx_idx = HSDMA_DESCS_NUM - 1;
 199
 200         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
 201         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
 202
 203         mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
 204                         0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
 205         mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
 206                         0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
 207 }
 208
 209 static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
 210 {
 211         dev_dbg(hsdma->ddev.dev, "tbase %08x, tcnt %08x, "
 212                         "tctx %08x, tdtx: %08x, rbase %08x, "
 213                         "rcnt %08x, rctx %08x, rdtx %08x\n",
 214                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
 215                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
 216                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
 217                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
 218                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
 219                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
 220                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
 221                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
 222
 223         dev_dbg(hsdma->ddev.dev, "info %08x, glo %08x, delay %08x, intr_stat %08x, intr_mask %08x\n",
 224                         mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
 225                         mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
 226                         mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
 227                         mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
 228                         mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
 229 }
 230
 231 static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
 232                             struct mtk_hsdma_chan *chan)
 233 {
 234         struct hsdma_desc *tx_desc;
 235         struct hsdma_desc *rx_desc;
 236         int i;
 237
 238         dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
 239                 chan->tx_idx, chan->rx_idx);
 240
 241         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 242                 tx_desc = &chan->tx_ring[i];
 243                 rx_desc = &chan->rx_ring[i];
 244
 245                 dev_dbg(hsdma->ddev.dev, "%d tx addr0: %08x, flags %08x, "
 246                                 "tx addr1: %08x, rx addr0 %08x, flags %08x\n",
 247                                 i, tx_desc->addr0, tx_desc->flags,
 248                                 tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
 249         }
 250 }
 251
 252 static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
 253                             struct mtk_hsdma_chan *chan)
 254 {
 255         int i;
 256
 257         /* disable dma */
 258         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
 259
 260         /* disable intr */
 261         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
 262
 263         /* init desc value */
 264         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 265                 chan->tx_ring[i].addr0 = 0;
 266                 chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
 267         }
 268         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 269                 chan->rx_ring[i].addr0 = 0;
 270                 chan->rx_ring[i].flags = 0;
 271         }
 272
 273         /* reset */
 274         mtk_hsdma_reset_chan(hsdma, chan);
 275
 276         /* enable intr */
 277         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
 278
 279         /* enable dma */
 280         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
 281 }
 282
 283 static int mtk_hsdma_terminate_all(struct dma_chan *c)
 284 {
 285         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 286         struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
 287         unsigned long timeout;
 288         LIST_HEAD(head);
 289
 290         spin_lock_bh(&chan->vchan.lock);
 291         chan->desc = NULL;
 292         clear_bit(chan->id, &hsdma->chan_issued);
 293         vchan_get_all_descriptors(&chan->vchan, &head);
 294         spin_unlock_bh(&chan->vchan.lock);
 295
 296         vchan_dma_desc_free_list(&chan->vchan, &head);
 297
 298         /* wait dma transfer complete */
 299         timeout = jiffies + msecs_to_jiffies(2000);
 300         while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
 301                         (HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
 302                 if (time_after_eq(jiffies, timeout)) {
 303                         hsdma_dump_desc(hsdma, chan);
 304                         mtk_hsdma_reset(hsdma, chan);
 305                         dev_err(hsdma->ddev.dev, "timeout, reset it\n");
 306                         break;
 307                 }
 308                 cpu_relax();
 309         }
 310
 311         return 0;
 312 }
 313
 314 static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
 315                                     struct mtk_hsdma_chan *chan)
 316 {
 317         dma_addr_t src, dst;
 318         size_t len, tlen;
 319         struct hsdma_desc *tx_desc, *rx_desc;
 320         struct mtk_hsdma_sg *sg;
 321         unsigned int i;
 322         int rx_idx;
 323
 324         sg = &chan->desc->sg[0];
 325         len = sg->len;
 326         chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
 327
 328         /* tx desc */
 329         src = sg->src_addr;
 330         for (i = 0; i < chan->desc->num_sgs; i++) {
 331                 tx_desc = &chan->tx_ring[chan->tx_idx];
 332
 333                 if (len > HSDMA_MAX_PLEN)
 334                         tlen = HSDMA_MAX_PLEN;
 335                 else
 336                         tlen = len;
 337
 338                 if (i & 0x1) {
 339                         tx_desc->addr1 = src;
 340                         tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
 341                 } else {
 342                         tx_desc->addr0 = src;
 343                         tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
 344
 345                         /* update index */
 346                         chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
 347                 }
 348
 349                 src += tlen;
 350                 len -= tlen;
 351         }
 352         if (i & 0x1)
 353                 tx_desc->flags |= HSDMA_DESC_LS0;
 354         else
 355                 tx_desc->flags |= HSDMA_DESC_LS1;
 356
 357         /* rx desc */
 358         rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
 359         len = sg->len;
 360         dst = sg->dst_addr;
 361         for (i = 0; i < chan->desc->num_sgs; i++) {
 362                 rx_desc = &chan->rx_ring[rx_idx];
 363                 if (len > HSDMA_MAX_PLEN)
 364                         tlen = HSDMA_MAX_PLEN;
 365                 else
 366                         tlen = len;
 367
 368                 rx_desc->addr0 = dst;
 369                 rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
 370
 371                 dst += tlen;
 372                 len -= tlen;
 373
 374                 /* update index */
 375                 rx_idx = HSDMA_NEXT_DESC(rx_idx);
 376         }
 377
 378         /* make sure desc and index all up to date */
 379         wmb();
 380         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
 381
 382         return 0;
 383 }
 384
 385 static int gdma_next_desc(struct mtk_hsdma_chan *chan)
 386 {
 387         struct virt_dma_desc *vdesc;
 388
 389         vdesc = vchan_next_desc(&chan->vchan);
 390         if (!vdesc) {
 391                 chan->desc = NULL;
 392                 return 0;
 393         }
 394         chan->desc = to_mtk_hsdma_desc(vdesc);
 395         chan->next_sg = 0;
 396
 397         return 1;
 398 }
 399
 400 static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
 401                                 struct mtk_hsdma_chan *chan)
 402 {
 403         struct mtk_hsdma_desc *desc;
 404         int chan_issued;
 405
 406         chan_issued = 0;
 407         spin_lock_bh(&chan->vchan.lock);
 408         desc = chan->desc;
 409         if (likely(desc)) {
 410                 if (chan->next_sg == desc->num_sgs) {
 411                         list_del(&desc->vdesc.node);
 412                         vchan_cookie_complete(&desc->vdesc);
 413                         chan_issued = gdma_next_desc(chan);
 414                 }
 415         } else {
 416                 dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
 417         }
 418
 419         if (chan_issued)
 420                 set_bit(chan->id, &hsdma->chan_issued);
 421         spin_unlock_bh(&chan->vchan.lock);
 422 }
 423
 424 static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
 425 {
 426         struct mtk_hsdam_engine *hsdma = devid;
 427         u32 status;
 428
 429         status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
 430         if (unlikely(!status))
 431                 return IRQ_NONE;
 432
 433         if (likely(status & HSDMA_INT_RX_Q0))
 434                 tasklet_schedule(&hsdma->task);
 435         else
 436                 dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n", status);
 437         /* clean intr bits */
 438         mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
 439
 440         return IRQ_HANDLED;
 441 }
 442
 443 static void mtk_hsdma_issue_pending(struct dma_chan *c)
 444 {
 445         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 446         struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
 447
 448         spin_lock_bh(&chan->vchan.lock);
 449         if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
 450                 if (gdma_next_desc(chan)) {
 451                         set_bit(chan->id, &hsdma->chan_issued);
 452                         tasklet_schedule(&hsdma->task);
 453                 } else {
 454                         dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
 455                 }
 456         }
 457         spin_unlock_bh(&chan->vchan.lock);
 458 }
 459
 460 static struct dma_async_tx_descriptor *mtk_hsdma_prep_dma_memcpy(
 461                 struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
 462                 size_t len, unsigned long flags)
 463 {
 464         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 465         struct mtk_hsdma_desc *desc;
 466
 467         if (len <= 0)
 468                 return NULL;
 469
 470         desc = kzalloc(sizeof(*desc), GFP_ATOMIC);
 471         if (!desc) {
 472                 dev_err(c->device->dev, "alloc memcpy decs error\n");
 473                 return NULL;
 474         }
 475
 476         desc->sg[0].src_addr = src;
 477         desc->sg[0].dst_addr = dest;
 478         desc->sg[0].len = len;
 479
 480         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 481 }
 482
 483 static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
 484                                            dma_cookie_t cookie,
 485                                            struct dma_tx_state *state)
 486 {
 487         return dma_cookie_status(c, cookie, state);
 488 }
 489
 490 static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
 491 {
 492         vchan_free_chan_resources(to_virt_chan(c));
 493 }
 494
 495 static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
 496 {
 497         kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
 498 }
 499
 500 static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
 501 {
 502         struct mtk_hsdma_chan *chan;
 503
 504         if (test_and_clear_bit(0, &hsdma->chan_issued)) {
 505                 chan = &hsdma->chan[0];
 506                 if (chan->desc)
 507                         mtk_hsdma_start_transfer(hsdma, chan);
 508                 else
 509                         dev_dbg(hsdma->ddev.dev, "chan 0 no desc to issue\n");
 510         }
 511 }
 512
 513 static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
 514 {
 515         struct mtk_hsdma_chan *chan;
 516         int next_idx, drx_idx, cnt;
 517
 518         chan = &hsdma->chan[0];
 519         next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
 520         drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
 521
 522         cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
 523         if (!cnt)
 524                 return;
 525
 526         chan->next_sg += cnt;
 527         chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
 528
 529         /* update rx crx */
 530         wmb();
 531         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
 532
 533         mtk_hsdma_chan_done(hsdma, chan);
 534 }
 535
 536 static void mtk_hsdma_tasklet(struct tasklet_struct *t)
 537 {
 538         struct mtk_hsdam_engine *hsdma = from_tasklet(hsdma, t, task);
 539
 540         mtk_hsdma_rx(hsdma);
 541         mtk_hsdma_tx(hsdma);
 542 }
 543
 544 static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
 545                                 struct mtk_hsdma_chan *chan)
 546 {
 547         int i;
 548
 549         chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
 550                                            2 * HSDMA_DESCS_NUM *
 551                                            sizeof(*chan->tx_ring),
 552                         &chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
 553         if (!chan->tx_ring)
 554                 goto no_mem;
 555
 556         chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
 557
 558         /* init tx ring value */
 559         for (i = 0; i < HSDMA_DESCS_NUM; i++)
 560                 chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
 561
 562         return 0;
 563 no_mem:
 564         return -ENOMEM;
 565 }
 566
 567 static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
 568                                 struct mtk_hsdma_chan *chan)
 569 {
 570         if (chan->tx_ring) {
 571                 dma_free_coherent(hsdma->ddev.dev,
 572                                   2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
 573                                   chan->tx_ring, chan->desc_addr);
 574                 chan->tx_ring = NULL;
 575                 chan->rx_ring = NULL;
 576         }
 577 }
 578
 579 static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
 580 {
 581         struct mtk_hsdma_chan *chan;
 582         int ret;
 583         u32 reg;
 584
 585         /* init desc */
 586         chan = &hsdma->chan[0];
 587         ret = mtk_hsdam_alloc_desc(hsdma, chan);
 588         if (ret)
 589                 return ret;
 590
 591         /* tx */
 592         mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
 593         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
 594         /* rx */
 595         mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
 596                         (sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
 597         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
 598         /* reset */
 599         mtk_hsdma_reset_chan(hsdma, chan);
 600
 601         /* enable rx intr */
 602         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
 603
 604         /* enable dma */
 605         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
 606
 607         /* hardware info */
 608         reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
 609         dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
 610                  (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
 611                  (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
 612
 613         hsdma_dump_reg(hsdma);
 614
 615         return ret;
 616 }
 617
 618 static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
 619 {
 620         struct mtk_hsdma_chan *chan;
 621
 622         /* disable dma */
 623         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
 624
 625         /* disable intr */
 626         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
 627
 628         /* free desc */
 629         chan = &hsdma->chan[0];
 630         mtk_hsdam_free_desc(hsdma, chan);
 631
 632         /* tx */
 633         mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
 634         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
 635         /* rx */
 636         mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
 637         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
 638         /* reset */
 639         mtk_hsdma_reset_chan(hsdma, chan);
 640 }
 641
 642 static const struct of_device_id mtk_hsdma_of_match[] = {
 643         { .compatible = "mediatek,mt7621-hsdma" },
 644         { },
 645 };
 646
 647 static int mtk_hsdma_probe(struct platform_device *pdev)
 648 {
 649         const struct of_device_id *match;
 650         struct mtk_hsdma_chan *chan;
 651         struct mtk_hsdam_engine *hsdma;
 652         struct dma_device *dd;
 653         int ret;
 654         int irq;
 655         void __iomem *base;
 656
 657         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 658         if (ret)
 659                 return ret;
 660
 661         match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
 662         if (!match)
 663                 return -EINVAL;
 664
 665         hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
 666         if (!hsdma)
 667                 return -EINVAL;
 668
 669         base = devm_platform_ioremap_resource(pdev, 0);
 670         if (IS_ERR(base))
 671                 return PTR_ERR(base);
 672         hsdma->base = base + HSDMA_BASE_OFFSET;
 673         tasklet_setup(&hsdma->task, mtk_hsdma_tasklet);
 674
 675         irq = platform_get_irq(pdev, 0);
 676         if (irq < 0)
 677                 return -EINVAL;
 678         ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
 679                                0, dev_name(&pdev->dev), hsdma);
 680         if (ret) {
 681                 dev_err(&pdev->dev, "failed to request irq\n");
 682                 return ret;
 683         }
 684
 685         device_reset(&pdev->dev);
 686
 687         dd = &hsdma->ddev;
 688         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 689         dd->copy_align = HSDMA_ALIGN_SIZE;
 690         dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
 691         dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
 692         dd->device_terminate_all = mtk_hsdma_terminate_all;
 693         dd->device_tx_status = mtk_hsdma_tx_status;
 694         dd->device_issue_pending = mtk_hsdma_issue_pending;
 695         dd->dev = &pdev->dev;
 696         dd->dev->dma_parms = &hsdma->dma_parms;
 697         dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
 698         INIT_LIST_HEAD(&dd->channels);
 699
 700         chan = &hsdma->chan[0];
 701         chan->id = 0;
 702         chan->vchan.desc_free = mtk_hsdma_desc_free;
 703         vchan_init(&chan->vchan, dd);
 704
 705         /* init hardware */
 706         ret = mtk_hsdma_init(hsdma);
 707         if (ret) {
 708                 dev_err(&pdev->dev, "failed to alloc ring descs\n");
 709                 return ret;
 710         }
 711
 712         ret = dma_async_device_register(dd);
 713         if (ret) {
 714                 dev_err(&pdev->dev, "failed to register dma device\n");
 715                 goto err_uninit_hsdma;
 716         }
 717
 718         ret = of_dma_controller_register(pdev->dev.of_node,
 719                                          of_dma_xlate_by_chan_id, hsdma);
 720         if (ret) {
 721                 dev_err(&pdev->dev, "failed to register of dma controller\n");
 722                 goto err_unregister;
 723         }
 724
 725         platform_set_drvdata(pdev, hsdma);
 726
 727         return 0;
 728
 729 err_unregister:
 730         dma_async_device_unregister(dd);
 731 err_uninit_hsdma:
 732         mtk_hsdma_uninit(hsdma);
 733         return ret;
 734 }
 735
 736 static int mtk_hsdma_remove(struct platform_device *pdev)
 737 {
 738         struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
 739
 740         mtk_hsdma_uninit(hsdma);
 741
 742         of_dma_controller_free(pdev->dev.of_node);
 743         dma_async_device_unregister(&hsdma->ddev);
 744
 745         return 0;
 746 }
 747
 748 static struct platform_driver mtk_hsdma_driver = {
 749         .probe = mtk_hsdma_probe,
 750         .remove = mtk_hsdma_remove,
 751         .driver = {
 752                 .name = KBUILD_MODNAME,
 753                 .of_match_table = mtk_hsdma_of_match,
 754         },
 755 };
 756 module_platform_driver(mtk_hsdma_driver);
 757
 758 MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
 759 MODULE_DESCRIPTION("MTK HSDMA driver");
 760 MODULE_LICENSE("GPL v2");