drivers/staging/mt29f_spinand/mt29f_spinand.c

   1 /*
   2  * Copyright (c) 2003-2013 Broadcom Corporation
   3  *
   4  * Copyright (c) 2009-2010 Micron Technology, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/rawnand.h>
  22 #include <linux/spi/spi.h>
  23
  24 #include "mt29f_spinand.h"
  25
  26 #define BUFSIZE (10 * 64 * 2048)
  27 #define CACHE_BUF 2112
  28 /*
  29  * OOB area specification layout:  Total 32 available free bytes.
  30  */
  31
  32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
  33 {
  34         struct nand_chip *chip = mtd_to_nand(mtd);
  35         struct spinand_info *info = nand_get_controller_data(chip);
  36         struct spinand_state *state = info->priv;
  37
  38         return state;
  39 }
  40
  41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
  42 static int enable_hw_ecc;
  43 static int enable_read_hw_ecc;
  44
  45 static int spinand_ooblayout_64_ecc(struct mtd_info *mtd, int section,
  46                                     struct mtd_oob_region *oobregion)
  47 {
  48         if (section > 3)
  49                 return -ERANGE;
  50
  51         oobregion->offset = (section * 16) + 1;
  52         oobregion->length = 6;
  53
  54         return 0;
  55 }
  56
  57 static int spinand_ooblayout_64_free(struct mtd_info *mtd, int section,
  58                                      struct mtd_oob_region *oobregion)
  59 {
  60         if (section > 3)
  61                 return -ERANGE;
  62
  63         oobregion->offset = (section * 16) + 8;
  64         oobregion->length = 8;
  65
  66         return 0;
  67 }
  68
  69 static const struct mtd_ooblayout_ops spinand_oob_64_ops = {
  70         .ecc = spinand_ooblayout_64_ecc,
  71         .free = spinand_ooblayout_64_free,
  72 };
  73 #endif
  74
  75 /**
  76  * spinand_cmd - process a command to send to the SPI Nand
  77  * Description:
  78  *    Set up the command buffer to send to the SPI controller.
  79  *    The command buffer has to initialized to 0.
  80  */
  81
  82 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
  83 {
  84         struct spi_message message;
  85         struct spi_transfer x[4];
  86         u8 dummy = 0xff;
  87
  88         spi_message_init(&message);
  89         memset(x, 0, sizeof(x));
  90
  91         x[0].len = 1;
  92         x[0].tx_buf = &cmd->cmd;
  93         spi_message_add_tail(&x[0], &message);
  94
  95         if (cmd->n_addr) {
  96                 x[1].len = cmd->n_addr;
  97                 x[1].tx_buf = cmd->addr;
  98                 spi_message_add_tail(&x[1], &message);
  99         }
 100
 101         if (cmd->n_dummy) {
 102                 x[2].len = cmd->n_dummy;
 103                 x[2].tx_buf = &dummy;
 104                 spi_message_add_tail(&x[2], &message);
 105         }
 106
 107         if (cmd->n_tx) {
 108                 x[3].len = cmd->n_tx;
 109                 x[3].tx_buf = cmd->tx_buf;
 110                 spi_message_add_tail(&x[3], &message);
 111         }
 112
 113         if (cmd->n_rx) {
 114                 x[3].len = cmd->n_rx;
 115                 x[3].rx_buf = cmd->rx_buf;
 116                 spi_message_add_tail(&x[3], &message);
 117         }
 118
 119         return spi_sync(spi, &message);
 120 }
 121
 122 /**
 123  * spinand_read_id - Read SPI Nand ID
 124  * Description:
 125  *    read two ID bytes from the SPI Nand device
 126  */
 127 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
 128 {
 129         int retval;
 130         u8 nand_id[3];
 131         struct spinand_cmd cmd = {0};
 132
 133         cmd.cmd = CMD_READ_ID;
 134         cmd.n_rx = 3;
 135         cmd.rx_buf = &nand_id[0];
 136
 137         retval = spinand_cmd(spi_nand, &cmd);
 138         if (retval < 0) {
 139                 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
 140                 return retval;
 141         }
 142         id[0] = nand_id[1];
 143         id[1] = nand_id[2];
 144         return retval;
 145 }
 146
 147 /**
 148  * spinand_read_status - send command 0xf to the SPI Nand status register
 149  * Description:
 150  *    After read, write, or erase, the Nand device is expected to set the
 151  *    busy status.
 152  *    This function is to allow reading the status of the command: read,
 153  *    write, and erase.
 154  *    Once the status turns to be ready, the other status bits also are
 155  *    valid status bits.
 156  */
 157 static int spinand_read_status(struct spi_device *spi_nand, u8 *status)
 158 {
 159         struct spinand_cmd cmd = {0};
 160         int ret;
 161
 162         cmd.cmd = CMD_READ_REG;
 163         cmd.n_addr = 1;
 164         cmd.addr[0] = REG_STATUS;
 165         cmd.n_rx = 1;
 166         cmd.rx_buf = status;
 167
 168         ret = spinand_cmd(spi_nand, &cmd);
 169         if (ret < 0)
 170                 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
 171
 172         return ret;
 173 }
 174
 175 #define MAX_WAIT_JIFFIES  (40 * HZ)
 176 static int wait_till_ready(struct spi_device *spi_nand)
 177 {
 178         unsigned long deadline;
 179         int retval;
 180         u8 stat = 0;
 181
 182         deadline = jiffies + MAX_WAIT_JIFFIES;
 183         do {
 184                 retval = spinand_read_status(spi_nand, &stat);
 185                 if (retval < 0)
 186                         return -1;
 187                 if (!(stat & 0x1))
 188                         break;
 189
 190                 cond_resched();
 191         } while (!time_after_eq(jiffies, deadline));
 192
 193         if ((stat & 0x1) == 0)
 194                 return 0;
 195
 196         return -1;
 197 }
 198
 199 /**
 200  * spinand_get_otp - send command 0xf to read the SPI Nand OTP register
 201  * Description:
 202  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
 203  *   Enable chip internal ECC, set the bit to 1
 204  *   Disable chip internal ECC, clear the bit to 0
 205  */
 206 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
 207 {
 208         struct spinand_cmd cmd = {0};
 209         int retval;
 210
 211         cmd.cmd = CMD_READ_REG;
 212         cmd.n_addr = 1;
 213         cmd.addr[0] = REG_OTP;
 214         cmd.n_rx = 1;
 215         cmd.rx_buf = otp;
 216
 217         retval = spinand_cmd(spi_nand, &cmd);
 218         if (retval < 0)
 219                 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
 220         return retval;
 221 }
 222
 223 /**
 224  * spinand_set_otp - send command 0x1f to write the SPI Nand OTP register
 225  * Description:
 226  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
 227  *   Enable chip internal ECC, set the bit to 1
 228  *   Disable chip internal ECC, clear the bit to 0
 229  */
 230 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
 231 {
 232         int retval;
 233         struct spinand_cmd cmd = {0};
 234
 235         cmd.cmd = CMD_WRITE_REG;
 236         cmd.n_addr = 1;
 237         cmd.addr[0] = REG_OTP;
 238         cmd.n_tx = 1;
 239         cmd.tx_buf = otp;
 240
 241         retval = spinand_cmd(spi_nand, &cmd);
 242         if (retval < 0)
 243                 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
 244
 245         return retval;
 246 }
 247
 248 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 249 /**
 250  * spinand_enable_ecc - send command 0x1f to write the SPI Nand OTP register
 251  * Description:
 252  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
 253  *   Enable chip internal ECC, set the bit to 1
 254  *   Disable chip internal ECC, clear the bit to 0
 255  */
 256 static int spinand_enable_ecc(struct spi_device *spi_nand)
 257 {
 258         int retval;
 259         u8 otp = 0;
 260
 261         retval = spinand_get_otp(spi_nand, &otp);
 262         if (retval < 0)
 263                 return retval;
 264
 265         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
 266                 return 0;
 267         otp |= OTP_ECC_MASK;
 268         retval = spinand_set_otp(spi_nand, &otp);
 269         if (retval < 0)
 270                 return retval;
 271         return spinand_get_otp(spi_nand, &otp);
 272 }
 273 #endif
 274
 275 static int spinand_disable_ecc(struct spi_device *spi_nand)
 276 {
 277         int retval;
 278         u8 otp = 0;
 279
 280         retval = spinand_get_otp(spi_nand, &otp);
 281         if (retval < 0)
 282                 return retval;
 283
 284         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
 285                 otp &= ~OTP_ECC_MASK;
 286                 retval = spinand_set_otp(spi_nand, &otp);
 287                 if (retval < 0)
 288                         return retval;
 289                 return spinand_get_otp(spi_nand, &otp);
 290         }
 291         return 0;
 292 }
 293
 294 /**
 295  * spinand_write_enable - send command 0x06 to enable write or erase the
 296  * Nand cells
 297  * Description:
 298  *   Before write and erase the Nand cells, the write enable has to be set.
 299  *   After the write or erase, the write enable bit is automatically
 300  *   cleared (status register bit 2)
 301  *   Set the bit 2 of the status register has the same effect
 302  */
 303 static int spinand_write_enable(struct spi_device *spi_nand)
 304 {
 305         struct spinand_cmd cmd = {0};
 306
 307         cmd.cmd = CMD_WR_ENABLE;
 308         return spinand_cmd(spi_nand, &cmd);
 309 }
 310
 311 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
 312 {
 313         struct spinand_cmd cmd = {0};
 314         u16 row;
 315
 316         row = page_id;
 317         cmd.cmd = CMD_READ;
 318         cmd.n_addr = 3;
 319         cmd.addr[0] = (u8)((row & 0xff0000) >> 16);
 320         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
 321         cmd.addr[2] = (u8)(row & 0x00ff);
 322
 323         return spinand_cmd(spi_nand, &cmd);
 324 }
 325
 326 /**
 327  * spinand_read_from_cache - send command 0x03 to read out the data from the
 328  * cache register (2112 bytes max)
 329  * Description:
 330  *   The read can specify 1 to 2112 bytes of data read at the corresponding
 331  *   locations.
 332  *   No tRd delay.
 333  */
 334 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
 335                                    u16 byte_id, u16 len, u8 *rbuf)
 336 {
 337         struct spinand_cmd cmd = {0};
 338         u16 column;
 339
 340         column = byte_id;
 341         cmd.cmd = CMD_READ_RDM;
 342         cmd.n_addr = 3;
 343         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
 344         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
 345         cmd.addr[1] = (u8)(column & 0x00ff);
 346         cmd.addr[2] = (u8)(0xff);
 347         cmd.n_dummy = 0;
 348         cmd.n_rx = len;
 349         cmd.rx_buf = rbuf;
 350
 351         return spinand_cmd(spi_nand, &cmd);
 352 }
 353
 354 /**
 355  * spinand_read_page - read a page
 356  * @page_id: the physical page number
 357  * @offset:  the location from 0 to 2111
 358  * @len:     number of bytes to read
 359  * @rbuf:    read buffer to hold @len bytes
 360  *
 361  * Description:
 362  *   The read includes two commands to the Nand - 0x13 and 0x03 commands
 363  *   Poll to read status to wait for tRD time.
 364  */
 365 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
 366                              u16 offset, u16 len, u8 *rbuf)
 367 {
 368         int ret;
 369         u8 status = 0;
 370
 371 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 372         if (enable_read_hw_ecc) {
 373                 if (spinand_enable_ecc(spi_nand) < 0)
 374                         dev_err(&spi_nand->dev, "enable HW ECC failed!");
 375         }
 376 #endif
 377         ret = spinand_read_page_to_cache(spi_nand, page_id);
 378         if (ret < 0)
 379                 return ret;
 380
 381         if (wait_till_ready(spi_nand))
 382                 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
 383
 384         while (1) {
 385                 ret = spinand_read_status(spi_nand, &status);
 386                 if (ret < 0) {
 387                         dev_err(&spi_nand->dev,
 388                                 "err %d read status register\n", ret);
 389                         return ret;
 390                 }
 391
 392                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 393                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
 394                                 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
 395                                         page_id);
 396                                 return 0;
 397                         }
 398                         break;
 399                 }
 400         }
 401
 402         ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
 403         if (ret < 0) {
 404                 dev_err(&spi_nand->dev, "read from cache failed!!\n");
 405                 return ret;
 406         }
 407
 408 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 409         if (enable_read_hw_ecc) {
 410                 ret = spinand_disable_ecc(spi_nand);
 411                 if (ret < 0) {
 412                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
 413                         return ret;
 414                 }
 415                 enable_read_hw_ecc = 0;
 416         }
 417 #endif
 418         return ret;
 419 }
 420
 421 /**
 422  * spinand_program_data_to_cache - write a page to cache
 423  * @byte_id: the location to write to the cache
 424  * @len:     number of bytes to write
 425  * @wbuf:    write buffer holding @len bytes
 426  *
 427  * Description:
 428  *   The write command used here is 0x84--indicating that the cache is
 429  *   not cleared first.
 430  *   Since it is writing the data to cache, there is no tPROG time.
 431  */
 432 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
 433                                          u16 page_id, u16 byte_id,
 434                                          u16 len, u8 *wbuf)
 435 {
 436         struct spinand_cmd cmd = {0};
 437         u16 column;
 438
 439         column = byte_id;
 440         cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
 441         cmd.n_addr = 2;
 442         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
 443         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
 444         cmd.addr[1] = (u8)(column & 0x00ff);
 445         cmd.n_tx = len;
 446         cmd.tx_buf = wbuf;
 447
 448         return spinand_cmd(spi_nand, &cmd);
 449 }
 450
 451 /**
 452  * spinand_program_execute - write a page from cache to the Nand array
 453  * @page_id: the physical page location to write the page.
 454  *
 455  * Description:
 456  *   The write command used here is 0x10--indicating the cache is writing to
 457  *   the Nand array.
 458  *   Need to wait for tPROG time to finish the transaction.
 459  */
 460 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
 461 {
 462         struct spinand_cmd cmd = {0};
 463         u16 row;
 464
 465         row = page_id;
 466         cmd.cmd = CMD_PROG_PAGE_EXC;
 467         cmd.n_addr = 3;
 468         cmd.addr[0] = (u8)((row & 0xff0000) >> 16);
 469         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
 470         cmd.addr[2] = (u8)(row & 0x00ff);
 471
 472         return spinand_cmd(spi_nand, &cmd);
 473 }
 474
 475 /**
 476  * spinand_program_page - write a page
 477  * @page_id: the physical page location to write the page.
 478  * @offset:  the location from the cache starting from 0 to 2111
 479  * @len:     the number of bytes to write
 480  * @buf:     the buffer holding @len bytes
 481  *
 482  * Description:
 483  *   The commands used here are 0x06, 0x84, and 0x10--indicating that
 484  *   the write enable is first sent, the write cache command, and the
 485  *   write execute command.
 486  *   Poll to wait for the tPROG time to finish the transaction.
 487  */
 488 static int spinand_program_page(struct spi_device *spi_nand,
 489                                 u16 page_id, u16 offset, u16 len, u8 *buf)
 490 {
 491         int retval;
 492         u8 status = 0;
 493         u8 *wbuf;
 494 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 495         unsigned int i, j;
 496
 497         wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
 498         if (!wbuf)
 499                 return -ENOMEM;
 500
 501         enable_read_hw_ecc = 1;
 502         retval = spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
 503         if (retval < 0) {
 504                 dev_err(&spi_nand->dev, "ecc error on read page!!!\n");
 505                 return retval;
 506         }
 507
 508         for (i = offset, j = 0; i < len; i++, j++)
 509                 wbuf[i] &= buf[j];
 510
 511         if (enable_hw_ecc) {
 512                 retval = spinand_enable_ecc(spi_nand);
 513                 if (retval < 0) {
 514                         dev_err(&spi_nand->dev, "enable ecc failed!!\n");
 515                         return retval;
 516                 }
 517         }
 518 #else
 519         wbuf = buf;
 520 #endif
 521         retval = spinand_write_enable(spi_nand);
 522         if (retval < 0) {
 523                 dev_err(&spi_nand->dev, "write enable failed!!\n");
 524                 return retval;
 525         }
 526         if (wait_till_ready(spi_nand))
 527                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
 528
 529         retval = spinand_program_data_to_cache(spi_nand, page_id,
 530                                                offset, len, wbuf);
 531         if (retval < 0)
 532                 return retval;
 533         retval = spinand_program_execute(spi_nand, page_id);
 534         if (retval < 0)
 535                 return retval;
 536         while (1) {
 537                 retval = spinand_read_status(spi_nand, &status);
 538                 if (retval < 0) {
 539                         dev_err(&spi_nand->dev,
 540                                 "error %d reading status register\n", retval);
 541                         return retval;
 542                 }
 543
 544                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 545                         if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
 546                                 dev_err(&spi_nand->dev,
 547                                         "program error, page %d\n", page_id);
 548                                 return -1;
 549                         }
 550                         break;
 551                 }
 552         }
 553 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 554         if (enable_hw_ecc) {
 555                 retval = spinand_disable_ecc(spi_nand);
 556                 if (retval < 0) {
 557                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
 558                         return retval;
 559                 }
 560                 enable_hw_ecc = 0;
 561         }
 562 #endif
 563
 564         return 0;
 565 }
 566
 567 /**
 568  * spinand_erase_block_erase - erase a page
 569  * @block_id: the physical block location to erase.
 570  *
 571  * Description:
 572  *   The command used here is 0xd8--indicating an erase command to erase
 573  *   one block--64 pages
 574  *   Need to wait for tERS.
 575  */
 576 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
 577 {
 578         struct spinand_cmd cmd = {0};
 579         u16 row;
 580
 581         row = block_id;
 582         cmd.cmd = CMD_ERASE_BLK;
 583         cmd.n_addr = 3;
 584         cmd.addr[0] = (u8)((row & 0xff0000) >> 16);
 585         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
 586         cmd.addr[2] = (u8)(row & 0x00ff);
 587
 588         return spinand_cmd(spi_nand, &cmd);
 589 }
 590
 591 /**
 592  * spinand_erase_block - erase a page
 593  * @block_id: the physical block location to erase.
 594  *
 595  * Description:
 596  *   The commands used here are 0x06 and 0xd8--indicating an erase
 597  *   command to erase one block--64 pages
 598  *   It will first to enable the write enable bit (0x06 command),
 599  *   and then send the 0xd8 erase command
 600  *   Poll to wait for the tERS time to complete the tranaction.
 601  */
 602 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
 603 {
 604         int retval;
 605         u8 status = 0;
 606
 607         retval = spinand_write_enable(spi_nand);
 608         if (wait_till_ready(spi_nand))
 609                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
 610
 611         retval = spinand_erase_block_erase(spi_nand, block_id);
 612         while (1) {
 613                 retval = spinand_read_status(spi_nand, &status);
 614                 if (retval < 0) {
 615                         dev_err(&spi_nand->dev,
 616                                 "error %d reading status register\n", retval);
 617                         return retval;
 618                 }
 619
 620                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 621                         if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
 622                                 dev_err(&spi_nand->dev,
 623                                         "erase error, block %d\n", block_id);
 624                                 return -1;
 625                         }
 626                         break;
 627                 }
 628         }
 629         return 0;
 630 }
 631
 632 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 633 static int spinand_write_page_hwecc(struct mtd_info *mtd,
 634                                     struct nand_chip *chip,
 635                                     const u8 *buf, int oob_required,
 636                                     int page)
 637 {
 638         const u8 *p = buf;
 639         int eccsize = chip->ecc.size;
 640         int eccsteps = chip->ecc.steps;
 641
 642         enable_hw_ecc = 1;
 643         return nand_prog_page_op(chip, page, 0, p, eccsize * eccsteps);
 644 }
 645
 646 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 647                                    u8 *buf, int oob_required, int page)
 648 {
 649         int retval;
 650         u8 status;
 651         u8 *p = buf;
 652         int eccsize = chip->ecc.size;
 653         int eccsteps = chip->ecc.steps;
 654         struct spinand_info *info = nand_get_controller_data(chip);
 655
 656         enable_read_hw_ecc = 1;
 657
 658         nand_read_page_op(chip, page, 0, p, eccsize * eccsteps);
 659         if (oob_required)
 660                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 661
 662         while (1) {
 663                 retval = spinand_read_status(info->spi, &status);
 664                 if (retval < 0) {
 665                         dev_err(&mtd->dev,
 666                                 "error %d reading status register\n", retval);
 667                         return retval;
 668                 }
 669
 670                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 671                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
 672                                 pr_info("spinand: ECC error\n");
 673                                 mtd->ecc_stats.failed++;
 674                         } else if ((status & STATUS_ECC_MASK) ==
 675                                         STATUS_ECC_1BIT_CORRECTED)
 676                                 mtd->ecc_stats.corrected++;
 677                         break;
 678                 }
 679         }
 680         return 0;
 681 }
 682 #endif
 683
 684 static void spinand_select_chip(struct mtd_info *mtd, int dev)
 685 {
 686 }
 687
 688 static u8 spinand_read_byte(struct mtd_info *mtd)
 689 {
 690         struct spinand_state *state = mtd_to_state(mtd);
 691         u8 data;
 692
 693         data = state->buf[state->buf_ptr];
 694         state->buf_ptr++;
 695         return data;
 696 }
 697
 698 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 699 {
 700         struct spinand_info *info = nand_get_controller_data(chip);
 701
 702         unsigned long timeo = jiffies;
 703         int retval, state = chip->state;
 704         u8 status;
 705
 706         if (state == FL_ERASING)
 707                 timeo += (HZ * 400) / 1000;
 708         else
 709                 timeo += (HZ * 20) / 1000;
 710
 711         while (time_before(jiffies, timeo)) {
 712                 retval = spinand_read_status(info->spi, &status);
 713                 if (retval < 0) {
 714                         dev_err(&mtd->dev,
 715                                 "error %d reading status register\n", retval);
 716                         return retval;
 717                 }
 718
 719                 if ((status & STATUS_OIP_MASK) == STATUS_READY)
 720                         return 0;
 721
 722                 cond_resched();
 723         }
 724         return 0;
 725 }
 726
 727 static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 728 {
 729         struct spinand_state *state = mtd_to_state(mtd);
 730
 731         memcpy(state->buf + state->buf_ptr, buf, len);
 732         state->buf_ptr += len;
 733 }
 734
 735 static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 736 {
 737         struct spinand_state *state = mtd_to_state(mtd);
 738
 739         memcpy(buf, state->buf + state->buf_ptr, len);
 740         state->buf_ptr += len;
 741 }
 742
 743 /*
 744  * spinand_reset- send RESET command "0xff" to the Nand device.
 745  */
 746 static void spinand_reset(struct spi_device *spi_nand)
 747 {
 748         struct spinand_cmd cmd = {0};
 749
 750         cmd.cmd = CMD_RESET;
 751
 752         if (spinand_cmd(spi_nand, &cmd) < 0)
 753                 pr_info("spinand reset failed!\n");
 754
 755         /* elapse 1ms before issuing any other command */
 756         usleep_range(1000, 2000);
 757
 758         if (wait_till_ready(spi_nand))
 759                 dev_err(&spi_nand->dev, "wait timedout!\n");
 760 }
 761
 762 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
 763                             int column, int page)
 764 {
 765         struct nand_chip *chip = mtd_to_nand(mtd);
 766         struct spinand_info *info = nand_get_controller_data(chip);
 767         struct spinand_state *state = info->priv;
 768
 769         switch (command) {
 770         /*
 771          * READ0 - read in first  0x800 bytes
 772          */
 773         case NAND_CMD_READ1:
 774         case NAND_CMD_READ0:
 775                 state->buf_ptr = 0;
 776                 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
 777                 break;
 778         /* READOOB reads only the OOB because no ECC is performed. */
 779         case NAND_CMD_READOOB:
 780                 state->buf_ptr = 0;
 781                 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
 782                 break;
 783         case NAND_CMD_RNDOUT:
 784                 state->buf_ptr = column;
 785                 break;
 786         case NAND_CMD_READID:
 787                 state->buf_ptr = 0;
 788                 spinand_read_id(info->spi, state->buf);
 789                 break;
 790         case NAND_CMD_PARAM:
 791                 state->buf_ptr = 0;
 792                 break;
 793         /* ERASE1 stores the block and page address */
 794         case NAND_CMD_ERASE1:
 795                 spinand_erase_block(info->spi, page);
 796                 break;
 797         /* ERASE2 uses the block and page address from ERASE1 */
 798         case NAND_CMD_ERASE2:
 799                 break;
 800         /* SEQIN sets up the addr buffer and all registers except the length */
 801         case NAND_CMD_SEQIN:
 802                 state->col = column;
 803                 state->row = page;
 804                 state->buf_ptr = 0;
 805                 break;
 806         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 807         case NAND_CMD_PAGEPROG:
 808                 spinand_program_page(info->spi, state->row, state->col,
 809                                      state->buf_ptr, state->buf);
 810                 break;
 811         case NAND_CMD_STATUS:
 812                 spinand_get_otp(info->spi, state->buf);
 813                 if (!(state->buf[0] & 0x80))
 814                         state->buf[0] = 0x80;
 815                 state->buf_ptr = 0;
 816                 break;
 817         /* RESET command */
 818         case NAND_CMD_RESET:
 819                 if (wait_till_ready(info->spi))
 820                         dev_err(&info->spi->dev, "WAIT timedout!!!\n");
 821                 /* a minimum of 250us must elapse before issuing RESET cmd*/
 822                 usleep_range(250, 1000);
 823                 spinand_reset(info->spi);
 824                 break;
 825         default:
 826                 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
 827         }
 828 }
 829
 830 /**
 831  * spinand_lock_block - send write register 0x1f command to the Nand device
 832  *
 833  * Description:
 834  *    After power up, all the Nand blocks are locked.  This function allows
 835  *    one to unlock the blocks, and so it can be written or erased.
 836  */
 837 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
 838 {
 839         struct spinand_cmd cmd = {0};
 840         int ret;
 841         u8 otp = 0;
 842
 843         ret = spinand_get_otp(spi_nand, &otp);
 844
 845         cmd.cmd = CMD_WRITE_REG;
 846         cmd.n_addr = 1;
 847         cmd.addr[0] = REG_BLOCK_LOCK;
 848         cmd.n_tx = 1;
 849         cmd.tx_buf = &lock;
 850
 851         ret = spinand_cmd(spi_nand, &cmd);
 852         if (ret < 0)
 853                 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
 854
 855         return ret;
 856 }
 857
 858 /**
 859  * spinand_probe - [spinand Interface]
 860  * @spi_nand: registered device driver.
 861  *
 862  * Description:
 863  *   Set up the device driver parameters to make the device available.
 864  */
 865 static int spinand_probe(struct spi_device *spi_nand)
 866 {
 867         struct mtd_info *mtd;
 868         struct nand_chip *chip;
 869         struct spinand_info *info;
 870         struct spinand_state *state;
 871
 872         info  = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
 873                              GFP_KERNEL);
 874         if (!info)
 875                 return -ENOMEM;
 876
 877         info->spi = spi_nand;
 878
 879         spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
 880
 881         state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
 882                              GFP_KERNEL);
 883         if (!state)
 884                 return -ENOMEM;
 885
 886         info->priv      = state;
 887         state->buf_ptr  = 0;
 888         state->buf      = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
 889         if (!state->buf)
 890                 return -ENOMEM;
 891
 892         chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
 893                             GFP_KERNEL);
 894         if (!chip)
 895                 return -ENOMEM;
 896
 897 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 898         chip->ecc.mode  = NAND_ECC_HW;
 899         chip->ecc.size  = 0x200;
 900         chip->ecc.bytes = 0x6;
 901         chip->ecc.steps = 0x4;
 902
 903         chip->ecc.strength = 1;
 904         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
 905         chip->ecc.read_page = spinand_read_page_hwecc;
 906         chip->ecc.write_page = spinand_write_page_hwecc;
 907 #else
 908         chip->ecc.mode  = NAND_ECC_SOFT;
 909         chip->ecc.algo  = NAND_ECC_HAMMING;
 910         if (spinand_disable_ecc(spi_nand) < 0)
 911                 dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
 912                          __func__);
 913 #endif
 914
 915         nand_set_flash_node(chip, spi_nand->dev.of_node);
 916         nand_set_controller_data(chip, info);
 917         chip->read_buf  = spinand_read_buf;
 918         chip->write_buf = spinand_write_buf;
 919         chip->read_byte = spinand_read_byte;
 920         chip->cmdfunc   = spinand_cmdfunc;
 921         chip->waitfunc  = spinand_wait;
 922         chip->options   |= NAND_CACHEPRG;
 923         chip->select_chip = spinand_select_chip;
 924         chip->set_features = nand_get_set_features_notsupp;
 925         chip->get_features = nand_get_set_features_notsupp;
 926
 927         mtd = nand_to_mtd(chip);
 928
 929         dev_set_drvdata(&spi_nand->dev, mtd);
 930
 931         mtd->dev.parent = &spi_nand->dev;
 932         mtd->oobsize = 64;
 933 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 934         mtd_set_ooblayout(mtd, &spinand_oob_64_ops);
 935 #endif
 936
 937         if (nand_scan(chip, 1))
 938                 return -ENXIO;
 939
 940         return mtd_device_register(mtd, NULL, 0);
 941 }
 942
 943 /**
 944  * spinand_remove - remove the device driver
 945  * @spi: the spi device.
 946  *
 947  * Description:
 948  *   Remove the device driver parameters and free up allocated memories.
 949  */
 950 static int spinand_remove(struct spi_device *spi)
 951 {
 952         mtd_device_unregister(dev_get_drvdata(&spi->dev));
 953
 954         return 0;
 955 }
 956
 957 static const struct of_device_id spinand_dt[] = {
 958         { .compatible = "spinand,mt29f", },
 959         {}
 960 };
 961 MODULE_DEVICE_TABLE(of, spinand_dt);
 962
 963 /*
 964  * Device name structure description
 965  */
 966 static struct spi_driver spinand_driver = {
 967         .driver = {
 968                 .name           = "mt29f",
 969                 .of_match_table = spinand_dt,
 970         },
 971         .probe          = spinand_probe,
 972         .remove         = spinand_remove,
 973 };
 974
 975 module_spi_driver(spinand_driver);
 976
 977 MODULE_DESCRIPTION("SPI NAND driver for Micron");
 978 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
 979 MODULE_LICENSE("GPL v2");