1 // SPDX-License-Identifier: GPL-2.0
3 * reg.h - Definitions for registers of DIM2
4 * (MediaLB, Device Interface Macro IP, OS62420)
6 * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
10 #define DIM2_OS62420_H
12 #include <linux/types.h>
16 u32 rsvd0[1]; /* 0x01 */
17 u32 MLBPC0; /* 0x02 */
19 u32 rsvd1[1]; /* 0x04 */
21 u32 rsvd2[2]; /* 0x06 */
24 u32 rsvd3[1]; /* 0x0A */
26 u32 rsvd4[1]; /* 0x0C */
27 u32 MLBPC2; /* 0x0D */
28 u32 MLBPC1; /* 0x0E */
30 u32 rsvd5[0x10]; /* 0x10 */
32 u32 rsvd6[1]; /* 0x21 */
39 u32 rsvd7[8]; /* 0x28 */
50 u32 rsvd8[0xb6]; /* 0x3A */
52 u32 rsvd9[3]; /* 0xF1 */
59 #define DIM2_MASK(n) (~((~(u32)0) << (n)))
66 MLBC0_MLBCLK_SHIFT = 2,
67 MLBC0_MLBCLK_VAL_256FS = 0,
68 MLBC0_MLBCLK_VAL_512FS = 1,
69 MLBC0_MLBCLK_VAL_1024FS = 2,
70 MLBC0_MLBCLK_VAL_2048FS = 3,
72 MLBC0_FCNT_SHIFT = 15,
74 MLBC0_FCNT_MAX_VAL = 6,
78 MIEN_CTX_BREAK_BIT = 29,
80 MIEN_CTX_DONE_BIT = 27,
82 MIEN_CRX_BREAK_BIT = 26,
84 MIEN_CRX_DONE_BIT = 24,
86 MIEN_ATX_BREAK_BIT = 22,
88 MIEN_ATX_DONE_BIT = 20,
90 MIEN_ARX_BREAK_BIT = 19,
92 MIEN_ARX_DONE_BIT = 17,
94 MIEN_SYNC_PE_BIT = 16,
96 MIEN_ISOC_BUFO_BIT = 1,
100 MLBC1_NDA_MASK = 0xFF,
102 MLBC1_CLKMERR_BIT = 7,
103 MLBC1_LOCKERR_BIT = 6,
105 ACTL_DMA_MODE_BIT = 2,
106 ACTL_DMA_MODE_VAL_DMA_MODE_0 = 0,
107 ACTL_DMA_MODE_VAL_DMA_MODE_1 = 1,
114 CDT0_RPC_SHIFT = 16 + 11,
115 CDT0_RPC_MASK = DIM2_MASK(5),
117 CDT1_BS_ISOC_SHIFT = 0,
118 CDT1_BS_ISOC_MASK = DIM2_MASK(9),
121 CDT3_BD_MASK = DIM2_MASK(12),
122 CDT3_BD_ISOC_MASK = DIM2_MASK(13),
135 ADT1_CTRL_ASYNC_BD_MASK = DIM2_MASK(11),
136 ADT1_ISOC_SYNC_BD_MASK = DIM2_MASK(13),
149 CAT_CT_VAL_CONTROL = 1,
150 CAT_CT_VAL_ASYNC = 2,
154 CAT_CL_MASK = DIM2_MASK(6)
157 #endif /* DIM2_OS62420_H */