1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
6 #ifndef __TEGRA_CSI_H__
7 #define __TEGRA_CSI_H__
9 #include <media/media-entity.h>
10 #include <media/v4l2-async.h>
11 #include <media/v4l2-subdev.h>
14 * Each CSI brick supports max of 4 lanes that can be used as either
15 * one x4 port using both CILA and CILB partitions of a CSI brick or can
16 * be used as two x2 ports with one x2 from CILA and the other x2 from
19 #define CSI_PORTS_PER_BRICK 2
21 /* each CSI channel can have one sink and one source pads */
22 #define TEGRA_CSI_PADS_NUM 2
24 enum tegra_csi_cil_port {
29 enum tegra_csi_block {
38 * struct tegra_csi_channel - Tegra CSI channel
40 * @list: list head for this entry
41 * @subdev: V4L2 subdevice associated with this channel
42 * @pads: media pads for the subdevice entity
43 * @numpads: number of pads.
44 * @csi: Tegra CSI device structure
45 * @of_node: csi device tree node
46 * @numlanes: number of lanes used per port/channel
47 * @csi_port_num: CSI channel port number
48 * @pg_mode: test pattern generator mode for channel
49 * @format: active format of the channel
50 * @framerate: active framerate for TPG
51 * @h_blank: horizontal blanking for TPG active format
52 * @v_blank: vertical blanking for TPG active format
53 * @mipi: mipi device for corresponding csi channel pads
54 * @pixel_rate: active pixel rate from the sensor on this channel
56 struct tegra_csi_channel {
57 struct list_head list;
58 struct v4l2_subdev subdev;
59 struct media_pad pads[TEGRA_CSI_PADS_NUM];
61 struct tegra_csi *csi;
62 struct device_node *of_node;
63 unsigned int numlanes;
66 struct v4l2_mbus_framefmt format;
67 unsigned int framerate;
70 struct tegra_mipi_device *mipi;
71 unsigned int pixel_rate;
75 * struct tpg_framerate - Tegra CSI TPG framerate configuration
77 * @frmsize: frame resolution
78 * @code: media bus format code
79 * @h_blank: horizontal blanking used for TPG
80 * @v_blank: vertical blanking interval used for TPG
81 * @framerate: framerate achieved with the corresponding blanking intervals,
82 * format and resolution.
84 struct tpg_framerate {
85 struct v4l2_frmsize_discrete frmsize;
89 unsigned int framerate;
93 * struct tegra_csi_ops - Tegra CSI operations
95 * @csi_start_streaming: programs csi hardware to enable streaming.
96 * @csi_stop_streaming: programs csi hardware to disable streaming.
97 * @csi_err_recover: csi hardware block recovery in case of any capture errors
98 * due to missing source stream or due to improper csi input from
99 * the external source.
101 struct tegra_csi_ops {
102 int (*csi_start_streaming)(struct tegra_csi_channel *csi_chan);
103 void (*csi_stop_streaming)(struct tegra_csi_channel *csi_chan);
104 void (*csi_err_recover)(struct tegra_csi_channel *csi_chan);
108 * struct tegra_csi_soc - NVIDIA Tegra CSI SoC structure
110 * @ops: csi hardware operations
111 * @csi_max_channels: supported max streaming channels
112 * @clk_names: csi and cil clock names
113 * @num_clks: total clocks count
114 * @tpg_frmrate_table: csi tpg frame rate table with blanking intervals
115 * @tpg_frmrate_table_size: size of frame rate table
117 struct tegra_csi_soc {
118 const struct tegra_csi_ops *ops;
119 unsigned int csi_max_channels;
120 const char * const *clk_names;
121 unsigned int num_clks;
122 const struct tpg_framerate *tpg_frmrate_table;
123 unsigned int tpg_frmrate_table_size;
127 * struct tegra_csi - NVIDIA Tegra CSI device structure
129 * @dev: device struct
130 * @client: host1x_client struct
131 * @iomem: register base
132 * @clks: clock for CSI and CIL
133 * @soc: pointer to SoC data structure
134 * @ops: csi operations
135 * @channels: list head for CSI channels
139 struct host1x_client client;
141 struct clk_bulk_data *clks;
142 const struct tegra_csi_soc *soc;
143 const struct tegra_csi_ops *ops;
144 struct list_head csi_chans;
147 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
148 extern const struct tegra_csi_soc tegra210_csi_soc;
151 void tegra_csi_error_recover(struct v4l2_subdev *subdev);
152 void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan,
154 u8 *ths_settle_time);