2 * drivers/staging/media/st-cec/stih-cec.c
5 * Copyright (C) STMicroelectronic SA 2016
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/version.h>
21 #include <media/cec.h>
23 #define CEC_NAME "stih-cec"
26 #define CEC_CLK_DIV 0x0
28 #define CEC_IRQ_CTRL 0x8
29 #define CEC_STATUS 0xC
30 #define CEC_EXT_STATUS 0x10
31 #define CEC_TX_CTRL 0x14
32 #define CEC_FREE_TIME_THRESH 0x18
33 #define CEC_BIT_TOUT_THRESH 0x1C
34 #define CEC_BIT_PULSE_THRESH 0x20
36 #define CEC_TX_ARRAY_CTRL 0x28
37 #define CEC_CTRL2 0x2C
38 #define CEC_TX_ERROR_STS 0x30
39 #define CEC_ADDR_TABLE 0x34
40 #define CEC_DATA_ARRAY_CTRL 0x38
41 #define CEC_DATA_ARRAY_STATUS 0x3C
42 #define CEC_TX_DATA_BASE 0x40
43 #define CEC_TX_DATA_TOP 0x50
44 #define CEC_TX_DATA_SIZE 0x1
45 #define CEC_RX_DATA_BASE 0x54
46 #define CEC_RX_DATA_TOP 0x64
47 #define CEC_RX_DATA_SIZE 0x1
50 #define CEC_LINE_INACTIVE_EN BIT(0)
51 #define CEC_AUTO_BUS_ERR_EN BIT(1)
52 #define CEC_STOP_ON_ARB_ERR_EN BIT(2)
53 #define CEC_TX_REQ_WAIT_EN BIT(3)
55 /* CEC_DATA_ARRAY_CTRL */
56 #define CEC_TX_ARRAY_EN BIT(0)
57 #define CEC_RX_ARRAY_EN BIT(1)
58 #define CEC_TX_ARRAY_RESET BIT(2)
59 #define CEC_RX_ARRAY_RESET BIT(3)
60 #define CEC_TX_N_OF_BYTES_IRQ_EN BIT(4)
61 #define CEC_TX_STOP_ON_NACK BIT(7)
63 /* CEC_TX_ARRAY_CTRL */
64 #define CEC_TX_N_OF_BYTES 0x1F
65 #define CEC_TX_START BIT(5)
66 #define CEC_TX_AUTO_SOM_EN BIT(6)
67 #define CEC_TX_AUTO_EOM_EN BIT(7)
70 #define CEC_TX_DONE_IRQ_EN BIT(0)
71 #define CEC_ERROR_IRQ_EN BIT(2)
72 #define CEC_RX_DONE_IRQ_EN BIT(3)
73 #define CEC_RX_SOM_IRQ_EN BIT(4)
74 #define CEC_RX_EOM_IRQ_EN BIT(5)
75 #define CEC_FREE_TIME_IRQ_EN BIT(6)
76 #define CEC_PIN_STS_IRQ_EN BIT(7)
79 #define CEC_IN_FILTER_EN BIT(0)
80 #define CEC_PWR_SAVE_EN BIT(1)
82 #define CEC_ACK_CTRL BIT(5)
83 #define CEC_RX_RESET_EN BIT(6)
84 #define CEC_IGNORE_RX_ERROR BIT(7)
87 #define CEC_TX_DONE_STS BIT(0)
88 #define CEC_TX_ACK_GET_STS BIT(1)
89 #define CEC_ERROR_STS BIT(2)
90 #define CEC_RX_DONE_STS BIT(3)
91 #define CEC_RX_SOM_STS BIT(4)
92 #define CEC_RX_EOM_STS BIT(5)
93 #define CEC_FREE_TIME_IRQ_STS BIT(6)
94 #define CEC_PIN_STS BIT(7)
95 #define CEC_SBIT_TOUT_STS BIT(8)
96 #define CEC_DBIT_TOUT_STS BIT(9)
97 #define CEC_LPULSE_ERROR_STS BIT(10)
98 #define CEC_HPULSE_ERROR_STS BIT(11)
99 #define CEC_TX_ERROR BIT(12)
100 #define CEC_TX_ARB_ERROR BIT(13)
101 #define CEC_RX_ERROR_MIN BIT(14)
102 #define CEC_RX_ERROR_MAX BIT(15)
104 /* Signal free time in bit periods (2.4ms) */
105 #define CEC_PRESENT_INIT_SFT 7
106 #define CEC_NEW_INIT_SFT 5
107 #define CEC_RETRANSMIT_SFT 3
109 /* Constants for CEC_BIT_TOUT_THRESH register */
110 #define CEC_SBIT_TOUT_47MS BIT(1)
111 #define CEC_SBIT_TOUT_48MS BIT(0) | BIT(1)
112 #define CEC_SBIT_TOUT_50MS BIT(2)
113 #define CEC_DBIT_TOUT_27MS BIT(0)
114 #define CEC_DBIT_TOUT_28MS BIT(1)
115 #define CEC_DBIT_TOUT_29MS BIT(0) | BIT(1)
117 /* Constants for CEC_BIT_PULSE_THRESH register */
118 #define CEC_BIT_LPULSE_03MS BIT(1)
119 #define CEC_BIT_HPULSE_03MS BIT(3)
121 /* Constants for CEC_DATA_ARRAY_STATUS register */
122 #define CEC_RX_N_OF_BYTES 0x1F
123 #define CEC_TX_N_OF_BYTES_SENT BIT(5)
124 #define CEC_RX_OVERRUN BIT(6)
127 struct cec_adapter *adap;
135 static int stih_cec_adap_enable(struct cec_adapter *adap, bool enable)
137 struct stih_cec *cec = adap->priv;
140 /* The doc says (input TCLK_PERIOD * CEC_CLK_DIV) = 0.1ms */
141 unsigned long clk_freq = clk_get_rate(cec->clk);
142 u32 cec_clk_div = clk_freq / 10000;
144 writel(cec_clk_div, cec->regs + CEC_CLK_DIV);
146 /* Configuration of the durations activating a timeout */
147 writel(CEC_SBIT_TOUT_47MS | (CEC_DBIT_TOUT_28MS << 4),
148 cec->regs + CEC_BIT_TOUT_THRESH);
150 /* Configuration of the smallest allowed duration for pulses */
151 writel(CEC_BIT_LPULSE_03MS | CEC_BIT_HPULSE_03MS,
152 cec->regs + CEC_BIT_PULSE_THRESH);
154 /* Minimum received bit period threshold */
155 writel(BIT(5) | BIT(7), cec->regs + CEC_TX_CTRL);
157 /* Configuration of transceiver data arrays */
158 writel(CEC_TX_ARRAY_EN | CEC_RX_ARRAY_EN | CEC_TX_STOP_ON_NACK,
159 cec->regs + CEC_DATA_ARRAY_CTRL);
161 /* Configuration of the control bits for CEC Transceiver */
162 writel(CEC_IN_FILTER_EN | CEC_EN | CEC_RX_RESET_EN,
163 cec->regs + CEC_CTRL);
165 /* Clear logical addresses */
166 writel(0, cec->regs + CEC_ADDR_TABLE);
168 /* Clear the status register */
169 writel(0x0, cec->regs + CEC_STATUS);
171 /* Enable the interrupts */
172 writel(CEC_TX_DONE_IRQ_EN | CEC_RX_DONE_IRQ_EN |
173 CEC_RX_SOM_IRQ_EN | CEC_RX_EOM_IRQ_EN |
175 cec->regs + CEC_IRQ_CTRL);
178 /* Clear logical addresses */
179 writel(0, cec->regs + CEC_ADDR_TABLE);
181 /* Clear the status register */
182 writel(0x0, cec->regs + CEC_STATUS);
184 /* Disable the interrupts */
185 writel(0, cec->regs + CEC_IRQ_CTRL);
191 static int stih_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
193 struct stih_cec *cec = adap->priv;
194 u32 reg = readl(cec->regs + CEC_ADDR_TABLE);
196 reg |= 1 << logical_addr;
198 if (logical_addr == CEC_LOG_ADDR_INVALID)
201 writel(reg, cec->regs + CEC_ADDR_TABLE);
206 static int stih_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
207 u32 signal_free_time, struct cec_msg *msg)
209 struct stih_cec *cec = adap->priv;
212 /* Copy message into registers */
213 for (i = 0; i < msg->len; i++)
214 writeb(msg->msg[i], cec->regs + CEC_TX_DATA_BASE + i);
216 /* Start transmission, configure hardware to add start and stop bits
217 * Signal free time is handled by the hardware
219 writel(CEC_TX_AUTO_SOM_EN | CEC_TX_AUTO_EOM_EN | CEC_TX_START |
220 msg->len, cec->regs + CEC_TX_ARRAY_CTRL);
225 static void stih_tx_done(struct stih_cec *cec, u32 status)
227 if (status & CEC_TX_ERROR) {
228 cec_transmit_done(cec->adap, CEC_TX_STATUS_ERROR, 0, 0, 0, 1);
232 if (status & CEC_TX_ARB_ERROR) {
233 cec_transmit_done(cec->adap,
234 CEC_TX_STATUS_ARB_LOST, 1, 0, 0, 0);
238 if (!(status & CEC_TX_ACK_GET_STS)) {
239 cec_transmit_done(cec->adap, CEC_TX_STATUS_NACK, 0, 1, 0, 0);
243 cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
246 static void stih_rx_done(struct stih_cec *cec, u32 status)
248 struct cec_msg msg = {};
251 if (status & CEC_RX_ERROR_MIN)
254 if (status & CEC_RX_ERROR_MAX)
257 msg.len = readl(cec->regs + CEC_DATA_ARRAY_STATUS) & 0x1f;
265 for (i = 0; i < msg.len; i++)
266 msg.msg[i] = readl(cec->regs + CEC_RX_DATA_BASE + i);
268 cec_received_msg(cec->adap, &msg);
271 static irqreturn_t stih_cec_irq_handler_thread(int irq, void *priv)
273 struct stih_cec *cec = priv;
275 if (cec->irq_status & CEC_TX_DONE_STS)
276 stih_tx_done(cec, cec->irq_status);
278 if (cec->irq_status & CEC_RX_DONE_STS)
279 stih_rx_done(cec, cec->irq_status);
286 static irqreturn_t stih_cec_irq_handler(int irq, void *priv)
288 struct stih_cec *cec = priv;
290 cec->irq_status = readl(cec->regs + CEC_STATUS);
291 writel(cec->irq_status, cec->regs + CEC_STATUS);
293 return IRQ_WAKE_THREAD;
296 static const struct cec_adap_ops sti_cec_adap_ops = {
297 .adap_enable = stih_cec_adap_enable,
298 .adap_log_addr = stih_cec_adap_log_addr,
299 .adap_transmit = stih_cec_adap_transmit,
302 static int stih_cec_probe(struct platform_device *pdev)
304 struct device *dev = &pdev->dev;
305 struct resource *res;
306 struct stih_cec *cec;
309 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
315 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
316 cec->regs = devm_ioremap_resource(dev, res);
317 if (IS_ERR(cec->regs))
318 return PTR_ERR(cec->regs);
320 cec->irq = platform_get_irq(pdev, 0);
324 ret = devm_request_threaded_irq(dev, cec->irq, stih_cec_irq_handler,
325 stih_cec_irq_handler_thread, 0,
330 cec->clk = devm_clk_get(dev, "cec-clk");
331 if (IS_ERR(cec->clk)) {
332 dev_err(dev, "Cannot get cec clock\n");
333 return PTR_ERR(cec->clk);
336 cec->adap = cec_allocate_adapter(&sti_cec_adap_ops, cec,
338 CEC_CAP_LOG_ADDRS | CEC_CAP_PASSTHROUGH |
339 CEC_CAP_PHYS_ADDR | CEC_CAP_TRANSMIT,
341 ret = PTR_ERR_OR_ZERO(cec->adap);
345 ret = cec_register_adapter(cec->adap);
347 cec_delete_adapter(cec->adap);
351 platform_set_drvdata(pdev, cec);
355 static int stih_cec_remove(struct platform_device *pdev)
360 static const struct of_device_id stih_cec_match[] = {
362 .compatible = "st,stih-cec",
367 static struct platform_driver stih_cec_pdrv = {
368 .probe = stih_cec_probe,
369 .remove = stih_cec_remove,
372 .of_match_table = stih_cec_match,
376 module_platform_driver(stih_cec_pdrv);
378 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@linaro.org>");
379 MODULE_LICENSE("GPL");
380 MODULE_DESCRIPTION("STIH4xx CEC driver");