drivers/staging/media/omap4iss/iss_csi2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI OMAP4 ISS V4L2 Driver - CSI PHY module
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <media/v4l2-common.h>
  12 #include <linux/v4l2-mediabus.h>
  13 #include <linux/mm.h>
  14
  15 #include "iss.h"
  16 #include "iss_regs.h"
  17 #include "iss_csi2.h"
  18
  19 /*
  20  * csi2_if_enable - Enable CSI2 Receiver interface.
  21  * @enable: enable flag
  22  *
  23  */
  24 static void csi2_if_enable(struct iss_csi2_device *csi2, u8 enable)
  25 {
  26         struct iss_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
  27
  28         iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTRL, CSI2_CTRL_IF_EN,
  29                        enable ? CSI2_CTRL_IF_EN : 0);
  30
  31         currctrl->if_enable = enable;
  32 }
  33
  34 /*
  35  * csi2_recv_config - CSI2 receiver module configuration.
  36  * @currctrl: iss_csi2_ctrl_cfg structure
  37  *
  38  */
  39 static void csi2_recv_config(struct iss_csi2_device *csi2,
  40                              struct iss_csi2_ctrl_cfg *currctrl)
  41 {
  42         u32 reg = 0;
  43
  44         if (currctrl->frame_mode)
  45                 reg |= CSI2_CTRL_FRAME;
  46         else
  47                 reg &= ~CSI2_CTRL_FRAME;
  48
  49         if (currctrl->vp_clk_enable)
  50                 reg |= CSI2_CTRL_VP_CLK_EN;
  51         else
  52                 reg &= ~CSI2_CTRL_VP_CLK_EN;
  53
  54         if (currctrl->vp_only_enable)
  55                 reg |= CSI2_CTRL_VP_ONLY_EN;
  56         else
  57                 reg &= ~CSI2_CTRL_VP_ONLY_EN;
  58
  59         reg &= ~CSI2_CTRL_VP_OUT_CTRL_MASK;
  60         reg |= currctrl->vp_out_ctrl << CSI2_CTRL_VP_OUT_CTRL_SHIFT;
  61
  62         if (currctrl->ecc_enable)
  63                 reg |= CSI2_CTRL_ECC_EN;
  64         else
  65                 reg &= ~CSI2_CTRL_ECC_EN;
  66
  67         /*
  68          * Set MFlag assertion boundaries to:
  69          * Low: 4/8 of FIFO size
  70          * High: 6/8 of FIFO size
  71          */
  72         reg &= ~(CSI2_CTRL_MFLAG_LEVH_MASK | CSI2_CTRL_MFLAG_LEVL_MASK);
  73         reg |= (2 << CSI2_CTRL_MFLAG_LEVH_SHIFT) |
  74                (4 << CSI2_CTRL_MFLAG_LEVL_SHIFT);
  75
  76         /* Generation of 16x64-bit bursts (Recommended) */
  77         reg |= CSI2_CTRL_BURST_SIZE_EXPAND;
  78
  79         /* Do Non-Posted writes (Recommended) */
  80         reg |= CSI2_CTRL_NON_POSTED_WRITE;
  81
  82         /*
  83          * Enforce Little endian for all formats, including:
  84          * YUV4:2:2 8-bit and YUV4:2:0 Legacy
  85          */
  86         reg |= CSI2_CTRL_ENDIANNESS;
  87
  88         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTRL, reg);
  89 }
  90
  91 static const unsigned int csi2_input_fmts[] = {
  92         MEDIA_BUS_FMT_SGRBG10_1X10,
  93         MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  94         MEDIA_BUS_FMT_SRGGB10_1X10,
  95         MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
  96         MEDIA_BUS_FMT_SBGGR10_1X10,
  97         MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
  98         MEDIA_BUS_FMT_SGBRG10_1X10,
  99         MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
 100         MEDIA_BUS_FMT_SBGGR8_1X8,
 101         MEDIA_BUS_FMT_SGBRG8_1X8,
 102         MEDIA_BUS_FMT_SGRBG8_1X8,
 103         MEDIA_BUS_FMT_SRGGB8_1X8,
 104         MEDIA_BUS_FMT_UYVY8_1X16,
 105         MEDIA_BUS_FMT_YUYV8_1X16,
 106 };
 107
 108 /* To set the format on the CSI2 requires a mapping function that takes
 109  * the following inputs:
 110  * - 3 different formats (at this time)
 111  * - 2 destinations (mem, vp+mem) (vp only handled separately)
 112  * - 2 decompression options (on, off)
 113  * Output should be CSI2 frame format code
 114  * Array indices as follows: [format][dest][decompr]
 115  * Not all combinations are valid. 0 means invalid.
 116  */
 117 static const u16 __csi2_fmt_map[][2][2] = {
 118         /* RAW10 formats */
 119         {
 120                 /* Output to memory */
 121                 {
 122                         /* No DPCM decompression */
 123                         CSI2_PIX_FMT_RAW10_EXP16,
 124                         /* DPCM decompression */
 125                         0,
 126                 },
 127                 /* Output to both */
 128                 {
 129                         /* No DPCM decompression */
 130                         CSI2_PIX_FMT_RAW10_EXP16_VP,
 131                         /* DPCM decompression */
 132                         0,
 133                 },
 134         },
 135         /* RAW10 DPCM8 formats */
 136         {
 137                 /* Output to memory */
 138                 {
 139                         /* No DPCM decompression */
 140                         CSI2_USERDEF_8BIT_DATA1,
 141                         /* DPCM decompression */
 142                         CSI2_USERDEF_8BIT_DATA1_DPCM10,
 143                 },
 144                 /* Output to both */
 145                 {
 146                         /* No DPCM decompression */
 147                         CSI2_PIX_FMT_RAW8_VP,
 148                         /* DPCM decompression */
 149                         CSI2_USERDEF_8BIT_DATA1_DPCM10_VP,
 150                 },
 151         },
 152         /* RAW8 formats */
 153         {
 154                 /* Output to memory */
 155                 {
 156                         /* No DPCM decompression */
 157                         CSI2_PIX_FMT_RAW8,
 158                         /* DPCM decompression */
 159                         0,
 160                 },
 161                 /* Output to both */
 162                 {
 163                         /* No DPCM decompression */
 164                         CSI2_PIX_FMT_RAW8_VP,
 165                         /* DPCM decompression */
 166                         0,
 167                 },
 168         },
 169         /* YUV422 formats */
 170         {
 171                 /* Output to memory */
 172                 {
 173                         /* No DPCM decompression */
 174                         CSI2_PIX_FMT_YUV422_8BIT,
 175                         /* DPCM decompression */
 176                         0,
 177                 },
 178                 /* Output to both */
 179                 {
 180                         /* No DPCM decompression */
 181                         CSI2_PIX_FMT_YUV422_8BIT_VP16,
 182                         /* DPCM decompression */
 183                         0,
 184                 },
 185         },
 186 };
 187
 188 /*
 189  * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
 190  * @csi2: ISS CSI2 device
 191  *
 192  * Returns CSI2 physical format id
 193  */
 194 static u16 csi2_ctx_map_format(struct iss_csi2_device *csi2)
 195 {
 196         const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
 197         int fmtidx, destidx;
 198
 199         switch (fmt->code) {
 200         case MEDIA_BUS_FMT_SGRBG10_1X10:
 201         case MEDIA_BUS_FMT_SRGGB10_1X10:
 202         case MEDIA_BUS_FMT_SBGGR10_1X10:
 203         case MEDIA_BUS_FMT_SGBRG10_1X10:
 204                 fmtidx = 0;
 205                 break;
 206         case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
 207         case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
 208         case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
 209         case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
 210                 fmtidx = 1;
 211                 break;
 212         case MEDIA_BUS_FMT_SBGGR8_1X8:
 213         case MEDIA_BUS_FMT_SGBRG8_1X8:
 214         case MEDIA_BUS_FMT_SGRBG8_1X8:
 215         case MEDIA_BUS_FMT_SRGGB8_1X8:
 216                 fmtidx = 2;
 217                 break;
 218         case MEDIA_BUS_FMT_UYVY8_1X16:
 219         case MEDIA_BUS_FMT_YUYV8_1X16:
 220                 fmtidx = 3;
 221                 break;
 222         default:
 223                 WARN(1, "CSI2: pixel format %08x unsupported!\n",
 224                      fmt->code);
 225                 return 0;
 226         }
 227
 228         if (!(csi2->output & CSI2_OUTPUT_IPIPEIF) &&
 229             !(csi2->output & CSI2_OUTPUT_MEMORY)) {
 230                 /* Neither output enabled is a valid combination */
 231                 return CSI2_PIX_FMT_OTHERS;
 232         }
 233
 234         /* If we need to skip frames at the beginning of the stream disable the
 235          * video port to avoid sending the skipped frames to the IPIPEIF.
 236          */
 237         destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
 238
 239         return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress];
 240 }
 241
 242 /*
 243  * csi2_set_outaddr - Set memory address to save output image
 244  * @csi2: Pointer to ISS CSI2a device.
 245  * @addr: 32-bit memory address aligned on 32 byte boundary.
 246  *
 247  * Sets the memory address where the output will be saved.
 248  *
 249  * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
 250  * boundary.
 251  */
 252 static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr)
 253 {
 254         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[0];
 255
 256         ctx->ping_addr = addr;
 257         ctx->pong_addr = addr;
 258         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
 259                       ctx->ping_addr);
 260         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
 261                       ctx->pong_addr);
 262 }
 263
 264 /*
 265  * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
 266  *                      be enabled by CSI2.
 267  * @format_id: mapped format id
 268  *
 269  */
 270 static inline int is_usr_def_mapping(u32 format_id)
 271 {
 272         return (format_id & 0xf0) == 0x40 ? 1 : 0;
 273 }
 274
 275 /*
 276  * csi2_ctx_enable - Enable specified CSI2 context
 277  * @ctxnum: Context number, valid between 0 and 7 values.
 278  * @enable: enable
 279  *
 280  */
 281 static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable)
 282 {
 283         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
 284         u32 reg;
 285
 286         reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum));
 287
 288         if (enable) {
 289                 unsigned int skip = 0;
 290
 291                 if (csi2->frame_skip)
 292                         skip = csi2->frame_skip;
 293                 else if (csi2->output & CSI2_OUTPUT_MEMORY)
 294                         skip = 1;
 295
 296                 reg &= ~CSI2_CTX_CTRL1_COUNT_MASK;
 297                 reg |= CSI2_CTX_CTRL1_COUNT_UNLOCK
 298                     |  (skip << CSI2_CTX_CTRL1_COUNT_SHIFT)
 299                     |  CSI2_CTX_CTRL1_CTX_EN;
 300         } else {
 301                 reg &= ~CSI2_CTX_CTRL1_CTX_EN;
 302         }
 303
 304         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum), reg);
 305         ctx->enabled = enable;
 306 }
 307
 308 /*
 309  * csi2_ctx_config - CSI2 context configuration.
 310  * @ctx: context configuration
 311  *
 312  */
 313 static void csi2_ctx_config(struct iss_csi2_device *csi2,
 314                             struct iss_csi2_ctx_cfg *ctx)
 315 {
 316         u32 reg = 0;
 317
 318         ctx->frame = 0;
 319
 320         /* Set up CSI2_CTx_CTRL1 */
 321         if (ctx->eof_enabled)
 322                 reg = CSI2_CTX_CTRL1_EOF_EN;
 323
 324         if (ctx->eol_enabled)
 325                 reg |= CSI2_CTX_CTRL1_EOL_EN;
 326
 327         if (ctx->checksum_enabled)
 328                 reg |= CSI2_CTX_CTRL1_CS_EN;
 329
 330         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg);
 331
 332         /* Set up CSI2_CTx_CTRL2 */
 333         reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
 334         reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT;
 335
 336         if (ctx->dpcm_decompress && ctx->dpcm_predictor)
 337                 reg |= CSI2_CTX_CTRL2_DPCM_PRED;
 338
 339         if (is_usr_def_mapping(ctx->format_id))
 340                 reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
 341
 342         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg);
 343
 344         /* Set up CSI2_CTx_CTRL3 */
 345         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL3(ctx->ctxnum),
 346                       ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT);
 347
 348         /* Set up CSI2_CTx_DAT_OFST */
 349         iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTX_DAT_OFST(ctx->ctxnum),
 350                        CSI2_CTX_DAT_OFST_MASK, ctx->data_offset);
 351
 352         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
 353                       ctx->ping_addr);
 354         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
 355                       ctx->pong_addr);
 356 }
 357
 358 /*
 359  * csi2_timing_config - CSI2 timing configuration.
 360  * @timing: csi2_timing_cfg structure
 361  */
 362 static void csi2_timing_config(struct iss_csi2_device *csi2,
 363                                struct iss_csi2_timing_cfg *timing)
 364 {
 365         u32 reg;
 366
 367         reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_TIMING);
 368
 369         if (timing->force_rx_mode)
 370                 reg |= CSI2_TIMING_FORCE_RX_MODE_IO1;
 371         else
 372                 reg &= ~CSI2_TIMING_FORCE_RX_MODE_IO1;
 373
 374         if (timing->stop_state_16x)
 375                 reg |= CSI2_TIMING_STOP_STATE_X16_IO1;
 376         else
 377                 reg &= ~CSI2_TIMING_STOP_STATE_X16_IO1;
 378
 379         if (timing->stop_state_4x)
 380                 reg |= CSI2_TIMING_STOP_STATE_X4_IO1;
 381         else
 382                 reg &= ~CSI2_TIMING_STOP_STATE_X4_IO1;
 383
 384         reg &= ~CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK;
 385         reg |= timing->stop_state_counter <<
 386                CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT;
 387
 388         iss_reg_write(csi2->iss, csi2->regs1, CSI2_TIMING, reg);
 389 }
 390
 391 /*
 392  * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
 393  * @enable: Enable/disable CSI2 Context interrupts
 394  */
 395 static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable)
 396 {
 397         const u32 mask = CSI2_CTX_IRQ_FE | CSI2_CTX_IRQ_FS;
 398         int i;
 399
 400         for (i = 0; i < 8; i++) {
 401                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(i),
 402                               mask);
 403                 if (enable)
 404                         iss_reg_set(csi2->iss, csi2->regs1,
 405                                     CSI2_CTX_IRQENABLE(i), mask);
 406                 else
 407                         iss_reg_clr(csi2->iss, csi2->regs1,
 408                                     CSI2_CTX_IRQENABLE(i), mask);
 409         }
 410 }
 411
 412 /*
 413  * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
 414  * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
 415  */
 416 static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable)
 417 {
 418         u32 reg;
 419
 420         reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT |
 421                 CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER |
 422                 CSI2_COMPLEXIO_IRQ_STATEULPM5 |
 423                 CSI2_COMPLEXIO_IRQ_ERRCONTROL5 |
 424                 CSI2_COMPLEXIO_IRQ_ERRESC5 |
 425                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 |
 426                 CSI2_COMPLEXIO_IRQ_ERRSOTHS5 |
 427                 CSI2_COMPLEXIO_IRQ_STATEULPM4 |
 428                 CSI2_COMPLEXIO_IRQ_ERRCONTROL4 |
 429                 CSI2_COMPLEXIO_IRQ_ERRESC4 |
 430                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 |
 431                 CSI2_COMPLEXIO_IRQ_ERRSOTHS4 |
 432                 CSI2_COMPLEXIO_IRQ_STATEULPM3 |
 433                 CSI2_COMPLEXIO_IRQ_ERRCONTROL3 |
 434                 CSI2_COMPLEXIO_IRQ_ERRESC3 |
 435                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 |
 436                 CSI2_COMPLEXIO_IRQ_ERRSOTHS3 |
 437                 CSI2_COMPLEXIO_IRQ_STATEULPM2 |
 438                 CSI2_COMPLEXIO_IRQ_ERRCONTROL2 |
 439                 CSI2_COMPLEXIO_IRQ_ERRESC2 |
 440                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 |
 441                 CSI2_COMPLEXIO_IRQ_ERRSOTHS2 |
 442                 CSI2_COMPLEXIO_IRQ_STATEULPM1 |
 443                 CSI2_COMPLEXIO_IRQ_ERRCONTROL1 |
 444                 CSI2_COMPLEXIO_IRQ_ERRESC1 |
 445                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 |
 446                 CSI2_COMPLEXIO_IRQ_ERRSOTHS1;
 447         iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg);
 448         if (enable)
 449                 iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
 450                             reg);
 451         else
 452                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
 453                               0);
 454 }
 455
 456 /*
 457  * csi2_irq_status_set - Enables CSI2 Status IRQs.
 458  * @enable: Enable/disable CSI2 Status interrupts
 459  */
 460 static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable)
 461 {
 462         u32 reg;
 463
 464         reg = CSI2_IRQ_OCP_ERR |
 465                 CSI2_IRQ_SHORT_PACKET |
 466                 CSI2_IRQ_ECC_CORRECTION |
 467                 CSI2_IRQ_ECC_NO_CORRECTION |
 468                 CSI2_IRQ_COMPLEXIO_ERR |
 469                 CSI2_IRQ_FIFO_OVF |
 470                 CSI2_IRQ_CONTEXT0;
 471         iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg);
 472         if (enable)
 473                 iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg);
 474         else
 475                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQENABLE, 0);
 476 }
 477
 478 /*
 479  * omap4iss_csi2_reset - Resets the CSI2 module.
 480  *
 481  * Must be called with the phy lock held.
 482  *
 483  * Returns 0 if successful, or -EBUSY if power command didn't respond.
 484  */
 485 int omap4iss_csi2_reset(struct iss_csi2_device *csi2)
 486 {
 487         unsigned int timeout;
 488
 489         if (!csi2->available)
 490                 return -ENODEV;
 491
 492         if (csi2->phy->phy_in_use)
 493                 return -EBUSY;
 494
 495         iss_reg_set(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
 496                     CSI2_SYSCONFIG_SOFT_RESET);
 497
 498         timeout = iss_poll_condition_timeout(
 499                 iss_reg_read(csi2->iss, csi2->regs1, CSI2_SYSSTATUS) &
 500                 CSI2_SYSSTATUS_RESET_DONE, 500, 100, 200);
 501         if (timeout) {
 502                 dev_err(csi2->iss->dev, "CSI2: Soft reset timeout!\n");
 503                 return -EBUSY;
 504         }
 505
 506         iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_CFG,
 507                     CSI2_COMPLEXIO_CFG_RESET_CTRL);
 508
 509         timeout = iss_poll_condition_timeout(
 510                 iss_reg_read(csi2->iss, csi2->phy->phy_regs, REGISTER1) &
 511                 REGISTER1_RESET_DONE_CTRLCLK, 10000, 100, 500);
 512         if (timeout) {
 513                 dev_err(csi2->iss->dev, "CSI2: CSI2_96M_FCLK reset timeout!\n");
 514                 return -EBUSY;
 515         }
 516
 517         iss_reg_update(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
 518                        CSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 519                        CSI2_SYSCONFIG_AUTO_IDLE,
 520                        CSI2_SYSCONFIG_MSTANDBY_MODE_NO);
 521
 522         return 0;
 523 }
 524
 525 static int csi2_configure(struct iss_csi2_device *csi2)
 526 {
 527         const struct iss_v4l2_subdevs_group *pdata;
 528         struct iss_csi2_timing_cfg *timing = &csi2->timing[0];
 529         struct v4l2_subdev *sensor;
 530         struct media_pad *pad;
 531
 532         /*
 533          * CSI2 fields that can be updated while the context has
 534          * been enabled or the interface has been enabled are not
 535          * updated dynamically currently. So we do not allow to
 536          * reconfigure if either has been enabled
 537          */
 538         if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
 539                 return -EBUSY;
 540
 541         pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
 542         sensor = media_entity_to_v4l2_subdev(pad->entity);
 543         pdata = sensor->host_priv;
 544
 545         csi2->frame_skip = 0;
 546         v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
 547
 548         csi2->ctrl.vp_out_ctrl = pdata->bus.csi2.vpclk_div;
 549         csi2->ctrl.frame_mode = ISS_CSI2_FRAME_IMMEDIATE;
 550         csi2->ctrl.ecc_enable = pdata->bus.csi2.crc;
 551
 552         timing->force_rx_mode = 1;
 553         timing->stop_state_16x = 1;
 554         timing->stop_state_4x = 1;
 555         timing->stop_state_counter = 0x1ff;
 556
 557         /*
 558          * The CSI2 receiver can't do any format conversion except DPCM
 559          * decompression, so every set_format call configures both pads
 560          * and enables DPCM decompression as a special case:
 561          */
 562         if (csi2->formats[CSI2_PAD_SINK].code !=
 563             csi2->formats[CSI2_PAD_SOURCE].code)
 564                 csi2->dpcm_decompress = true;
 565         else
 566                 csi2->dpcm_decompress = false;
 567
 568         csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
 569
 570         if (csi2->video_out.bpl_padding == 0)
 571                 csi2->contexts[0].data_offset = 0;
 572         else
 573                 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
 574
 575         /*
 576          * Enable end of frame and end of line signals generation for
 577          * context 0. These signals are generated from CSI2 receiver to
 578          * qualify the last pixel of a frame and the last pixel of a line.
 579          * Without enabling the signals CSI2 receiver writes data to memory
 580          * beyond buffer size and/or data line offset is not handled correctly.
 581          */
 582         csi2->contexts[0].eof_enabled = 1;
 583         csi2->contexts[0].eol_enabled = 1;
 584
 585         csi2_irq_complexio1_set(csi2, 1);
 586         csi2_irq_ctx_set(csi2, 1);
 587         csi2_irq_status_set(csi2, 1);
 588
 589         /* Set configuration (timings, format and links) */
 590         csi2_timing_config(csi2, timing);
 591         csi2_recv_config(csi2, &csi2->ctrl);
 592         csi2_ctx_config(csi2, &csi2->contexts[0]);
 593
 594         return 0;
 595 }
 596
 597 /*
 598  * csi2_print_status - Prints CSI2 debug information.
 599  */
 600 #define CSI2_PRINT_REGISTER(iss, regs, name)\
 601         dev_dbg(iss->dev, "###CSI2 " #name "=0x%08x\n", \
 602                 iss_reg_read(iss, regs, CSI2_##name))
 603
 604 static void csi2_print_status(struct iss_csi2_device *csi2)
 605 {
 606         struct iss_device *iss = csi2->iss;
 607
 608         if (!csi2->available)
 609                 return;
 610
 611         dev_dbg(iss->dev, "-------------CSI2 Register dump-------------\n");
 612
 613         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSCONFIG);
 614         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSSTATUS);
 615         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQENABLE);
 616         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQSTATUS);
 617         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTRL);
 618         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_H);
 619         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_CFG);
 620         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQSTATUS);
 621         CSI2_PRINT_REGISTER(iss, csi2->regs1, SHORT_PACKET);
 622         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQENABLE);
 623         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_P);
 624         CSI2_PRINT_REGISTER(iss, csi2->regs1, TIMING);
 625         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL1(0));
 626         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL2(0));
 627         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_DAT_OFST(0));
 628         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PING_ADDR(0));
 629         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PONG_ADDR(0));
 630         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQENABLE(0));
 631         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQSTATUS(0));
 632         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL3(0));
 633
 634         dev_dbg(iss->dev, "--------------------------------------------\n");
 635 }
 636
 637 /* -----------------------------------------------------------------------------
 638  * Interrupt handling
 639  */
 640
 641 /*
 642  * csi2_isr_buffer - Does buffer handling at end-of-frame
 643  * when writing to memory.
 644  */
 645 static void csi2_isr_buffer(struct iss_csi2_device *csi2)
 646 {
 647         struct iss_buffer *buffer;
 648
 649         csi2_ctx_enable(csi2, 0, 0);
 650
 651         buffer = omap4iss_video_buffer_next(&csi2->video_out);
 652
 653         /*
 654          * Let video queue operation restart engine if there is an underrun
 655          * condition.
 656          */
 657         if (!buffer)
 658                 return;
 659
 660         csi2_set_outaddr(csi2, buffer->iss_addr);
 661         csi2_ctx_enable(csi2, 0, 1);
 662 }
 663
 664 static void csi2_isr_ctx(struct iss_csi2_device *csi2,
 665                          struct iss_csi2_ctx_cfg *ctx)
 666 {
 667         unsigned int n = ctx->ctxnum;
 668         u32 status;
 669
 670         status = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n));
 671         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n), status);
 672
 673         if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
 674                 return;
 675
 676         /* Propagate frame number */
 677         if (status & CSI2_CTX_IRQ_FS) {
 678                 struct iss_pipeline *pipe =
 679                                      to_iss_pipeline(&csi2->subdev.entity);
 680                 u16 frame;
 681                 u16 delta;
 682
 683                 frame = iss_reg_read(csi2->iss, csi2->regs1,
 684                                      CSI2_CTX_CTRL2(ctx->ctxnum))
 685                       >> CSI2_CTX_CTRL2_FRAME_SHIFT;
 686
 687                 if (frame == 0) {
 688                         /* A zero value means that the counter isn't implemented
 689                          * by the source. Increment the frame number in software
 690                          * in that case.
 691                          */
 692                         atomic_inc(&pipe->frame_number);
 693                 } else {
 694                         /* Extend the 16 bit frame number to 32 bits by
 695                          * computing the delta between two consecutive CSI2
 696                          * frame numbers and adding it to the software frame
 697                          * number. The hardware counter starts at 1 and wraps
 698                          * from 0xffff to 1 without going through 0, so subtract
 699                          * 1 when the counter wraps.
 700                          */
 701                         delta = frame - ctx->frame;
 702                         if (frame < ctx->frame)
 703                                 delta--;
 704                         ctx->frame = frame;
 705
 706                         atomic_add(delta, &pipe->frame_number);
 707                 }
 708         }
 709
 710         if (!(status & CSI2_CTX_IRQ_FE))
 711                 return;
 712
 713         /* Skip interrupts until we reach the frame skip count. The CSI2 will be
 714          * automatically disabled, as the frame skip count has been programmed
 715          * in the CSI2_CTx_CTRL1::COUNT field, so re-enable it.
 716          *
 717          * It would have been nice to rely on the FRAME_NUMBER interrupt instead
 718          * but it turned out that the interrupt is only generated when the CSI2
 719          * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
 720          * correctly and reaches 0 when data is forwarded to the video port only
 721          * but no interrupt arrives). Maybe a CSI2 hardware bug.
 722          */
 723         if (csi2->frame_skip) {
 724                 csi2->frame_skip--;
 725                 if (csi2->frame_skip == 0) {
 726                         ctx->format_id = csi2_ctx_map_format(csi2);
 727                         csi2_ctx_config(csi2, ctx);
 728                         csi2_ctx_enable(csi2, n, 1);
 729                 }
 730                 return;
 731         }
 732
 733         if (csi2->output & CSI2_OUTPUT_MEMORY)
 734                 csi2_isr_buffer(csi2);
 735 }
 736
 737 /*
 738  * omap4iss_csi2_isr - CSI2 interrupt handling.
 739  */
 740 void omap4iss_csi2_isr(struct iss_csi2_device *csi2)
 741 {
 742         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
 743         u32 csi2_irqstatus, cpxio1_irqstatus;
 744         struct iss_device *iss = csi2->iss;
 745
 746         if (!csi2->available)
 747                 return;
 748
 749         csi2_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_IRQSTATUS);
 750         iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, csi2_irqstatus);
 751
 752         /* Failure Cases */
 753         if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) {
 754                 cpxio1_irqstatus = iss_reg_read(csi2->iss, csi2->regs1,
 755                                                 CSI2_COMPLEXIO_IRQSTATUS);
 756                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS,
 757                               cpxio1_irqstatus);
 758                 dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ %x\n",
 759                         cpxio1_irqstatus);
 760                 pipe->error = true;
 761         }
 762
 763         if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR |
 764                               CSI2_IRQ_SHORT_PACKET |
 765                               CSI2_IRQ_ECC_NO_CORRECTION |
 766                               CSI2_IRQ_COMPLEXIO_ERR |
 767                               CSI2_IRQ_FIFO_OVF)) {
 768                 dev_dbg(iss->dev,
 769                         "CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n",
 770                         csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0,
 771                         csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0,
 772                         csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0,
 773                         csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0,
 774                         csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0);
 775                 pipe->error = true;
 776         }
 777
 778         /* Successful cases */
 779         if (csi2_irqstatus & CSI2_IRQ_CONTEXT0)
 780                 csi2_isr_ctx(csi2, &csi2->contexts[0]);
 781
 782         if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION)
 783                 dev_dbg(iss->dev, "CSI2: ECC correction done\n");
 784 }
 785
 786 /* -----------------------------------------------------------------------------
 787  * ISS video operations
 788  */
 789
 790 /*
 791  * csi2_queue - Queues the first buffer when using memory output
 792  * @video: The video node
 793  * @buffer: buffer to queue
 794  */
 795 static int csi2_queue(struct iss_video *video, struct iss_buffer *buffer)
 796 {
 797         struct iss_csi2_device *csi2 = container_of(video,
 798                                 struct iss_csi2_device, video_out);
 799
 800         csi2_set_outaddr(csi2, buffer->iss_addr);
 801
 802         /*
 803          * If streaming was enabled before there was a buffer queued
 804          * or underrun happened in the ISR, the hardware was not enabled
 805          * and DMA queue flag ISS_VIDEO_DMAQUEUE_UNDERRUN is still set.
 806          * Enable it now.
 807          */
 808         if (csi2->video_out.dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) {
 809                 /* Enable / disable context 0 and IRQs */
 810                 csi2_if_enable(csi2, 1);
 811                 csi2_ctx_enable(csi2, 0, 1);
 812                 iss_video_dmaqueue_flags_clr(&csi2->video_out);
 813         }
 814
 815         return 0;
 816 }
 817
 818 static const struct iss_video_operations csi2_issvideo_ops = {
 819         .queue = csi2_queue,
 820 };
 821
 822 /* -----------------------------------------------------------------------------
 823  * V4L2 subdev operations
 824  */
 825
 826 static struct v4l2_mbus_framefmt *
 827 __csi2_get_format(struct iss_csi2_device *csi2,
 828                   struct v4l2_subdev_pad_config *cfg,
 829                   unsigned int pad,
 830                   enum v4l2_subdev_format_whence which)
 831 {
 832         if (which == V4L2_SUBDEV_FORMAT_TRY)
 833                 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
 834
 835         return &csi2->formats[pad];
 836 }
 837
 838 static void
 839 csi2_try_format(struct iss_csi2_device *csi2,
 840                 struct v4l2_subdev_pad_config *cfg,
 841                 unsigned int pad,
 842                 struct v4l2_mbus_framefmt *fmt,
 843                 enum v4l2_subdev_format_whence which)
 844 {
 845         u32 pixelcode;
 846         struct v4l2_mbus_framefmt *format;
 847         const struct iss_format_info *info;
 848         unsigned int i;
 849
 850         switch (pad) {
 851         case CSI2_PAD_SINK:
 852                 /* Clamp the width and height to valid range (1-8191). */
 853                 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
 854                         if (fmt->code == csi2_input_fmts[i])
 855                                 break;
 856                 }
 857
 858                 /* If not found, use SGRBG10 as default */
 859                 if (i >= ARRAY_SIZE(csi2_input_fmts))
 860                         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 861
 862                 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
 863                 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
 864                 break;
 865
 866         case CSI2_PAD_SOURCE:
 867                 /* Source format same as sink format, except for DPCM
 868                  * compression.
 869                  */
 870                 pixelcode = fmt->code;
 871                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
 872                 memcpy(fmt, format, sizeof(*fmt));
 873
 874                 /*
 875                  * Only Allow DPCM decompression, and check that the
 876                  * pattern is preserved
 877                  */
 878                 info = omap4iss_video_format_info(fmt->code);
 879                 if (info->uncompressed == pixelcode)
 880                         fmt->code = pixelcode;
 881                 break;
 882         }
 883
 884         /* RGB, non-interlaced */
 885         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 886         fmt->field = V4L2_FIELD_NONE;
 887 }
 888
 889 /*
 890  * csi2_enum_mbus_code - Handle pixel format enumeration
 891  * @sd     : pointer to v4l2 subdev structure
 892  * @cfg    : V4L2 subdev pad config
 893  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 894  * return -EINVAL or zero on success
 895  */
 896 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
 897                                struct v4l2_subdev_pad_config *cfg,
 898                                struct v4l2_subdev_mbus_code_enum *code)
 899 {
 900         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 901         struct v4l2_mbus_framefmt *format;
 902         const struct iss_format_info *info;
 903
 904         if (code->pad == CSI2_PAD_SINK) {
 905                 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
 906                         return -EINVAL;
 907
 908                 code->code = csi2_input_fmts[code->index];
 909         } else {
 910                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
 911                                            code->which);
 912                 switch (code->index) {
 913                 case 0:
 914                         /* Passthrough sink pad code */
 915                         code->code = format->code;
 916                         break;
 917                 case 1:
 918                         /* Uncompressed code */
 919                         info = omap4iss_video_format_info(format->code);
 920                         if (info->uncompressed == format->code)
 921                                 return -EINVAL;
 922
 923                         code->code = info->uncompressed;
 924                         break;
 925                 default:
 926                         return -EINVAL;
 927                 }
 928         }
 929
 930         return 0;
 931 }
 932
 933 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
 934                                 struct v4l2_subdev_pad_config *cfg,
 935                                 struct v4l2_subdev_frame_size_enum *fse)
 936 {
 937         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 938         struct v4l2_mbus_framefmt format;
 939
 940         if (fse->index != 0)
 941                 return -EINVAL;
 942
 943         format.code = fse->code;
 944         format.width = 1;
 945         format.height = 1;
 946         csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
 947         fse->min_width = format.width;
 948         fse->min_height = format.height;
 949
 950         if (format.code != fse->code)
 951                 return -EINVAL;
 952
 953         format.code = fse->code;
 954         format.width = -1;
 955         format.height = -1;
 956         csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
 957         fse->max_width = format.width;
 958         fse->max_height = format.height;
 959
 960         return 0;
 961 }
 962
 963 /*
 964  * csi2_get_format - Handle get format by pads subdev method
 965  * @sd : pointer to v4l2 subdev structure
 966  * @cfg: V4L2 subdev pad config
 967  * @fmt: pointer to v4l2 subdev format structure
 968  * return -EINVAL or zero on success
 969  */
 970 static int csi2_get_format(struct v4l2_subdev *sd,
 971                            struct v4l2_subdev_pad_config *cfg,
 972                            struct v4l2_subdev_format *fmt)
 973 {
 974         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 975         struct v4l2_mbus_framefmt *format;
 976
 977         format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
 978         if (!format)
 979                 return -EINVAL;
 980
 981         fmt->format = *format;
 982         return 0;
 983 }
 984
 985 /*
 986  * csi2_set_format - Handle set format by pads subdev method
 987  * @sd : pointer to v4l2 subdev structure
 988  * @cfg: V4L2 subdev pad config
 989  * @fmt: pointer to v4l2 subdev format structure
 990  * return -EINVAL or zero on success
 991  */
 992 static int csi2_set_format(struct v4l2_subdev *sd,
 993                            struct v4l2_subdev_pad_config *cfg,
 994                            struct v4l2_subdev_format *fmt)
 995 {
 996         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 997         struct v4l2_mbus_framefmt *format;
 998
 999         format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
1000         if (!format)
1001                 return -EINVAL;
1002
1003         csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
1004         *format = fmt->format;
1005
1006         /* Propagate the format from sink to source */
1007         if (fmt->pad == CSI2_PAD_SINK) {
1008                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
1009                                            fmt->which);
1010                 *format = fmt->format;
1011                 csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
1012         }
1013
1014         return 0;
1015 }
1016
1017 static int csi2_link_validate(struct v4l2_subdev *sd, struct media_link *link,
1018                               struct v4l2_subdev_format *source_fmt,
1019                               struct v4l2_subdev_format *sink_fmt)
1020 {
1021         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1022         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1023         int rval;
1024
1025         pipe->external = media_entity_to_v4l2_subdev(link->source->entity);
1026         rval = omap4iss_get_external_info(pipe, link);
1027         if (rval < 0)
1028                 return rval;
1029
1030         return v4l2_subdev_link_validate_default(sd, link, source_fmt,
1031                                                  sink_fmt);
1032 }
1033
1034 /*
1035  * csi2_init_formats - Initialize formats on all pads
1036  * @sd: ISS CSI2 V4L2 subdevice
1037  * @fh: V4L2 subdev file handle
1038  *
1039  * Initialize all pad formats with default values. If fh is not NULL, try
1040  * formats are initialized on the file handle. Otherwise active formats are
1041  * initialized on the device.
1042  */
1043 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1044 {
1045         struct v4l2_subdev_format format;
1046
1047         memset(&format, 0, sizeof(format));
1048         format.pad = CSI2_PAD_SINK;
1049         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1050         format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1051         format.format.width = 4096;
1052         format.format.height = 4096;
1053         csi2_set_format(sd, fh ? fh->pad : NULL, &format);
1054
1055         return 0;
1056 }
1057
1058 /*
1059  * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1060  * @sd: ISS CSI2 V4L2 subdevice
1061  * @enable: ISS pipeline stream state
1062  *
1063  * Return 0 on success or a negative error code otherwise.
1064  */
1065 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1066 {
1067         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1068         struct iss_device *iss = csi2->iss;
1069         struct iss_video *video_out = &csi2->video_out;
1070         int ret = 0;
1071
1072         if (csi2->state == ISS_PIPELINE_STREAM_STOPPED) {
1073                 if (enable == ISS_PIPELINE_STREAM_STOPPED)
1074                         return 0;
1075
1076                 omap4iss_subclk_enable(iss, csi2->subclk);
1077         }
1078
1079         switch (enable) {
1080         case ISS_PIPELINE_STREAM_CONTINUOUS: {
1081                 ret = omap4iss_csiphy_config(iss, sd);
1082                 if (ret < 0)
1083                         return ret;
1084
1085                 if (omap4iss_csiphy_acquire(csi2->phy) < 0)
1086                         return -ENODEV;
1087                 csi2_configure(csi2);
1088                 csi2_print_status(csi2);
1089
1090                 /*
1091                  * When outputting to memory with no buffer available, let the
1092                  * buffer queue handler start the hardware. A DMA queue flag
1093                  * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1094                  * a buffer available.
1095                  */
1096                 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1097                     !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED))
1098                         break;
1099                 /* Enable context 0 and IRQs */
1100                 atomic_set(&csi2->stopping, 0);
1101                 csi2_ctx_enable(csi2, 0, 1);
1102                 csi2_if_enable(csi2, 1);
1103                 iss_video_dmaqueue_flags_clr(video_out);
1104                 break;
1105         }
1106         case ISS_PIPELINE_STREAM_STOPPED:
1107                 if (csi2->state == ISS_PIPELINE_STREAM_STOPPED)
1108                         return 0;
1109                 if (omap4iss_module_sync_idle(&sd->entity, &csi2->wait,
1110                                               &csi2->stopping))
1111                         ret = -ETIMEDOUT;
1112                 csi2_ctx_enable(csi2, 0, 0);
1113                 csi2_if_enable(csi2, 0);
1114                 csi2_irq_ctx_set(csi2, 0);
1115                 omap4iss_csiphy_release(csi2->phy);
1116                 omap4iss_subclk_disable(iss, csi2->subclk);
1117                 iss_video_dmaqueue_flags_clr(video_out);
1118                 break;
1119         }
1120
1121         csi2->state = enable;
1122         return ret;
1123 }
1124
1125 /* subdev video operations */
1126 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1127         .s_stream = csi2_set_stream,
1128 };
1129
1130 /* subdev pad operations */
1131 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1132         .enum_mbus_code = csi2_enum_mbus_code,
1133         .enum_frame_size = csi2_enum_frame_size,
1134         .get_fmt = csi2_get_format,
1135         .set_fmt = csi2_set_format,
1136         .link_validate = csi2_link_validate,
1137 };
1138
1139 /* subdev operations */
1140 static const struct v4l2_subdev_ops csi2_ops = {
1141         .video = &csi2_video_ops,
1142         .pad = &csi2_pad_ops,
1143 };
1144
1145 /* subdev internal operations */
1146 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1147         .open = csi2_init_formats,
1148 };
1149
1150 /* -----------------------------------------------------------------------------
1151  * Media entity operations
1152  */
1153
1154 /*
1155  * csi2_link_setup - Setup CSI2 connections.
1156  * @entity : Pointer to media entity structure
1157  * @local  : Pointer to local pad array
1158  * @remote : Pointer to remote pad array
1159  * @flags  : Link flags
1160  * return -EINVAL or zero on success
1161  */
1162 static int csi2_link_setup(struct media_entity *entity,
1163                            const struct media_pad *local,
1164                            const struct media_pad *remote, u32 flags)
1165 {
1166         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1167         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1168         struct iss_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1169         unsigned int index = local->index;
1170
1171         /* FIXME: this is actually a hack! */
1172         if (is_media_entity_v4l2_subdev(remote->entity))
1173                 index |= 2 << 16;
1174
1175         /*
1176          * The ISS core doesn't support pipelines with multiple video outputs.
1177          * Revisit this when it will be implemented, and return -EBUSY for now.
1178          */
1179
1180         switch (index) {
1181         case CSI2_PAD_SOURCE:
1182                 if (flags & MEDIA_LNK_FL_ENABLED) {
1183                         if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1184                                 return -EBUSY;
1185                         csi2->output |= CSI2_OUTPUT_MEMORY;
1186                 } else {
1187                         csi2->output &= ~CSI2_OUTPUT_MEMORY;
1188                 }
1189                 break;
1190
1191         case CSI2_PAD_SOURCE | 2 << 16:
1192                 if (flags & MEDIA_LNK_FL_ENABLED) {
1193                         if (csi2->output & ~CSI2_OUTPUT_IPIPEIF)
1194                                 return -EBUSY;
1195                         csi2->output |= CSI2_OUTPUT_IPIPEIF;
1196                 } else {
1197                         csi2->output &= ~CSI2_OUTPUT_IPIPEIF;
1198                 }
1199                 break;
1200
1201         default:
1202                 /* Link from camera to CSI2 is fixed... */
1203                 return -EINVAL;
1204         }
1205
1206         ctrl->vp_only_enable = csi2->output & CSI2_OUTPUT_MEMORY ? false : true;
1207         ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
1208
1209         return 0;
1210 }
1211
1212 /* media operations */
1213 static const struct media_entity_operations csi2_media_ops = {
1214         .link_setup = csi2_link_setup,
1215         .link_validate = v4l2_subdev_link_validate,
1216 };
1217
1218 void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2)
1219 {
1220         v4l2_device_unregister_subdev(&csi2->subdev);
1221         omap4iss_video_unregister(&csi2->video_out);
1222 }
1223
1224 int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,
1225                                     struct v4l2_device *vdev)
1226 {
1227         int ret;
1228
1229         /* Register the subdev and video nodes. */
1230         ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1231         if (ret < 0)
1232                 goto error;
1233
1234         ret = omap4iss_video_register(&csi2->video_out, vdev);
1235         if (ret < 0)
1236                 goto error;
1237
1238         return 0;
1239
1240 error:
1241         omap4iss_csi2_unregister_entities(csi2);
1242         return ret;
1243 }
1244
1245 /* -----------------------------------------------------------------------------
1246  * ISS CSI2 initialisation and cleanup
1247  */
1248
1249 /*
1250  * csi2_init_entities - Initialize subdev and media entity.
1251  * @csi2: Pointer to csi2 structure.
1252  * return -ENOMEM or zero on success
1253  */
1254 static int csi2_init_entities(struct iss_csi2_device *csi2, const char *subname)
1255 {
1256         struct v4l2_subdev *sd = &csi2->subdev;
1257         struct media_pad *pads = csi2->pads;
1258         struct media_entity *me = &sd->entity;
1259         int ret;
1260         char name[V4L2_SUBDEV_NAME_SIZE];
1261
1262         v4l2_subdev_init(sd, &csi2_ops);
1263         sd->internal_ops = &csi2_internal_ops;
1264         snprintf(name, sizeof(name), "CSI2%s", subname);
1265         snprintf(sd->name, sizeof(sd->name), "OMAP4 ISS %s", name);
1266
1267         sd->grp_id = BIT(16);   /* group ID for iss subdevs */
1268         v4l2_set_subdevdata(sd, csi2);
1269         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1270
1271         pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1272         pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1273
1274         me->ops = &csi2_media_ops;
1275         ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
1276         if (ret < 0)
1277                 return ret;
1278
1279         csi2_init_formats(sd, NULL);
1280
1281         /* Video device node */
1282         csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1283         csi2->video_out.ops = &csi2_issvideo_ops;
1284         csi2->video_out.bpl_alignment = 32;
1285         csi2->video_out.bpl_zero_padding = 1;
1286         csi2->video_out.bpl_max = 0x1ffe0;
1287         csi2->video_out.iss = csi2->iss;
1288         csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1289
1290         ret = omap4iss_video_init(&csi2->video_out, name);
1291         if (ret < 0)
1292                 goto error_video;
1293
1294         return 0;
1295
1296 error_video:
1297         media_entity_cleanup(&csi2->subdev.entity);
1298         return ret;
1299 }
1300
1301 /*
1302  * omap4iss_csi2_init - Routine for module driver init
1303  */
1304 int omap4iss_csi2_init(struct iss_device *iss)
1305 {
1306         struct iss_csi2_device *csi2a = &iss->csi2a;
1307         struct iss_csi2_device *csi2b = &iss->csi2b;
1308         int ret;
1309
1310         csi2a->iss = iss;
1311         csi2a->available = 1;
1312         csi2a->regs1 = OMAP4_ISS_MEM_CSI2_A_REGS1;
1313         csi2a->phy = &iss->csiphy1;
1314         csi2a->subclk = OMAP4_ISS_SUBCLK_CSI2_A;
1315         csi2a->state = ISS_PIPELINE_STREAM_STOPPED;
1316         init_waitqueue_head(&csi2a->wait);
1317
1318         ret = csi2_init_entities(csi2a, "a");
1319         if (ret < 0)
1320                 return ret;
1321
1322         csi2b->iss = iss;
1323         csi2b->available = 1;
1324         csi2b->regs1 = OMAP4_ISS_MEM_CSI2_B_REGS1;
1325         csi2b->phy = &iss->csiphy2;
1326         csi2b->subclk = OMAP4_ISS_SUBCLK_CSI2_B;
1327         csi2b->state = ISS_PIPELINE_STREAM_STOPPED;
1328         init_waitqueue_head(&csi2b->wait);
1329
1330         ret = csi2_init_entities(csi2b, "b");
1331         if (ret < 0)
1332                 return ret;
1333
1334         return 0;
1335 }
1336
1337 /*
1338  * omap4iss_csi2_create_links() - CSI2 pads links creation
1339  * @iss: Pointer to ISS device
1340  *
1341  * return negative error code or zero on success
1342  */
1343 int omap4iss_csi2_create_links(struct iss_device *iss)
1344 {
1345         struct iss_csi2_device *csi2a = &iss->csi2a;
1346         struct iss_csi2_device *csi2b = &iss->csi2b;
1347         int ret;
1348
1349         /* Connect the CSI2a subdev to the video node. */
1350         ret = media_create_pad_link(&csi2a->subdev.entity, CSI2_PAD_SOURCE,
1351                                     &csi2a->video_out.video.entity, 0, 0);
1352         if (ret < 0)
1353                 return ret;
1354
1355         /* Connect the CSI2b subdev to the video node. */
1356         ret = media_create_pad_link(&csi2b->subdev.entity, CSI2_PAD_SOURCE,
1357                                     &csi2b->video_out.video.entity, 0, 0);
1358         if (ret < 0)
1359                 return ret;
1360
1361         return 0;
1362 }
1363
1364 /*
1365  * omap4iss_csi2_cleanup - Routine for module driver cleanup
1366  */
1367 void omap4iss_csi2_cleanup(struct iss_device *iss)
1368 {
1369         struct iss_csi2_device *csi2a = &iss->csi2a;
1370         struct iss_csi2_device *csi2b = &iss->csi2b;
1371
1372         omap4iss_video_cleanup(&csi2a->video_out);
1373         media_entity_cleanup(&csi2a->subdev.entity);
1374
1375         omap4iss_video_cleanup(&csi2b->video_out);
1376         media_entity_cleanup(&csi2b->subdev.entity);
1377 }