1 // SPDX-License-Identifier: GPL-2.0
3 * V4L2 Capture CSI Subdev for Freescale i.MX6UL/L / i.MX7 SOC
5 * Copyright (c) 2019 Linaro Ltd
10 #include <linux/delay.h>
11 #include <linux/gcd.h>
12 #include <linux/interrupt.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_graph.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/types.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-event.h>
24 #include <media/v4l2-fwnode.h>
25 #include <media/v4l2-mc.h>
26 #include <media/v4l2-subdev.h>
27 #include <media/videobuf2-dma-contig.h>
29 #include <media/imx.h>
30 #include "imx-media.h"
32 #define IMX7_CSI_PAD_SINK 0
33 #define IMX7_CSI_PAD_SRC 1
34 #define IMX7_CSI_PADS_NUM 2
37 #define CSICR1_RESET_VAL 0x40000800
38 #define CSICR2_RESET_VAL 0x0
39 #define CSICR3_RESET_VAL 0x0
41 /* csi control reg 1 */
42 #define BIT_SWAP16_EN BIT(31)
43 #define BIT_EXT_VSYNC BIT(30)
44 #define BIT_EOF_INT_EN BIT(29)
45 #define BIT_PRP_IF_EN BIT(28)
46 #define BIT_CCIR_MODE BIT(27)
47 #define BIT_COF_INT_EN BIT(26)
48 #define BIT_SF_OR_INTEN BIT(25)
49 #define BIT_RF_OR_INTEN BIT(24)
50 #define BIT_SFF_DMA_DONE_INTEN BIT(22)
51 #define BIT_STATFF_INTEN BIT(21)
52 #define BIT_FB2_DMA_DONE_INTEN BIT(20)
53 #define BIT_FB1_DMA_DONE_INTEN BIT(19)
54 #define BIT_RXFF_INTEN BIT(18)
55 #define BIT_SOF_POL BIT(17)
56 #define BIT_SOF_INTEN BIT(16)
57 #define BIT_MCLKDIV (0xF << 12)
58 #define BIT_HSYNC_POL BIT(11)
59 #define BIT_CCIR_EN BIT(10)
60 #define BIT_MCLKEN BIT(9)
61 #define BIT_FCC BIT(8)
62 #define BIT_PACK_DIR BIT(7)
63 #define BIT_CLR_STATFIFO BIT(6)
64 #define BIT_CLR_RXFIFO BIT(5)
65 #define BIT_GCLK_MODE BIT(4)
66 #define BIT_INV_DATA BIT(3)
67 #define BIT_INV_PCLK BIT(2)
68 #define BIT_REDGE BIT(1)
69 #define BIT_PIXEL_BIT BIT(0)
71 #define SHIFT_MCLKDIV 12
74 #define BIT_FRMCNT (0xFFFF << 16)
75 #define BIT_FRMCNT_RST BIT(15)
76 #define BIT_DMA_REFLASH_RFF BIT(14)
77 #define BIT_DMA_REFLASH_SFF BIT(13)
78 #define BIT_DMA_REQ_EN_RFF BIT(12)
79 #define BIT_DMA_REQ_EN_SFF BIT(11)
80 #define BIT_STATFF_LEVEL (0x7 << 8)
81 #define BIT_HRESP_ERR_EN BIT(7)
82 #define BIT_RXFF_LEVEL (0x7 << 4)
83 #define BIT_TWO_8BIT_SENSOR BIT(3)
84 #define BIT_ZERO_PACK_EN BIT(2)
85 #define BIT_ECC_INT_EN BIT(1)
86 #define BIT_ECC_AUTO_EN BIT(0)
88 #define SHIFT_FRMCNT 16
89 #define SHIFT_RXFIFO_LEVEL 4
92 #define BIT_ADDR_CH_ERR_INT BIT(28)
93 #define BIT_FIELD0_INT BIT(27)
94 #define BIT_FIELD1_INT BIT(26)
95 #define BIT_SFF_OR_INT BIT(25)
96 #define BIT_RFF_OR_INT BIT(24)
97 #define BIT_DMA_TSF_DONE_SFF BIT(22)
98 #define BIT_STATFF_INT BIT(21)
99 #define BIT_DMA_TSF_DONE_FB2 BIT(20)
100 #define BIT_DMA_TSF_DONE_FB1 BIT(19)
101 #define BIT_RXFF_INT BIT(18)
102 #define BIT_EOF_INT BIT(17)
103 #define BIT_SOF_INT BIT(16)
104 #define BIT_F2_INT BIT(15)
105 #define BIT_F1_INT BIT(14)
106 #define BIT_COF_INT BIT(13)
107 #define BIT_HRESP_ERR_INT BIT(7)
108 #define BIT_ECC_INT BIT(1)
109 #define BIT_DRDY BIT(0)
111 /* csi control reg 18 */
112 #define BIT_CSI_HW_ENABLE BIT(31)
113 #define BIT_MIPI_DATA_FORMAT_RAW8 (0x2a << 25)
114 #define BIT_MIPI_DATA_FORMAT_RAW10 (0x2b << 25)
115 #define BIT_MIPI_DATA_FORMAT_RAW12 (0x2c << 25)
116 #define BIT_MIPI_DATA_FORMAT_RAW14 (0x2d << 25)
117 #define BIT_MIPI_DATA_FORMAT_YUV422_8B (0x1e << 25)
118 #define BIT_MIPI_DATA_FORMAT_MASK (0x3F << 25)
119 #define BIT_MIPI_DATA_FORMAT_OFFSET 25
120 #define BIT_DATA_FROM_MIPI BIT(22)
121 #define BIT_MIPI_YU_SWAP BIT(21)
122 #define BIT_MIPI_DOUBLE_CMPNT BIT(20)
123 #define BIT_BASEADDR_CHG_ERR_EN BIT(9)
124 #define BIT_BASEADDR_SWITCH_SEL BIT(5)
125 #define BIT_BASEADDR_SWITCH_EN BIT(4)
126 #define BIT_PARALLEL24_EN BIT(3)
127 #define BIT_DEINTERLACE_EN BIT(2)
128 #define BIT_TVDECODER_IN_EN BIT(1)
129 #define BIT_NTSC_EN BIT(0)
131 #define CSI_MCLK_VF 1
132 #define CSI_MCLK_ENC 2
133 #define CSI_MCLK_RAW 4
134 #define CSI_MCLK_I2C 8
136 #define CSI_CSICR1 0x0
137 #define CSI_CSICR2 0x4
138 #define CSI_CSICR3 0x8
139 #define CSI_STATFIFO 0xC
140 #define CSI_CSIRXFIFO 0x10
141 #define CSI_CSIRXCNT 0x14
142 #define CSI_CSISR 0x18
144 #define CSI_CSIDBG 0x1C
145 #define CSI_CSIDMASA_STATFIFO 0x20
146 #define CSI_CSIDMATS_STATFIFO 0x24
147 #define CSI_CSIDMASA_FB1 0x28
148 #define CSI_CSIDMASA_FB2 0x2C
149 #define CSI_CSIFBUF_PARA 0x30
150 #define CSI_CSIIMAG_PARA 0x34
152 #define CSI_CSICR18 0x48
153 #define CSI_CSICR19 0x4c
157 struct v4l2_subdev sd;
158 struct v4l2_async_notifier notifier;
159 struct imx_media_video_dev *vdev;
160 struct imx_media_dev *imxmd;
161 struct media_pad pad[IMX7_CSI_PADS_NUM];
163 /* lock to protect members below */
165 /* lock to protect irq handler when stop streaming */
168 struct v4l2_subdev *src_sd;
170 struct media_entity *sink;
172 struct v4l2_mbus_framefmt format_mbus[IMX7_CSI_PADS_NUM];
173 const struct imx_media_pixfmt *cc[IMX7_CSI_PADS_NUM];
174 struct v4l2_fract frame_interval[IMX7_CSI_PADS_NUM];
176 struct v4l2_ctrl_handler ctrl_hdlr;
178 void __iomem *regbase;
182 /* active vb2 buffers to send to video dev sink */
183 struct imx_media_buffer *active_vb2_buf[2];
184 struct imx_media_dma_buf underrun_buf;
194 struct completion last_eof_completion;
197 static struct imx7_csi *
198 imx7_csi_notifier_to_dev(struct v4l2_async_notifier *n)
200 return container_of(n, struct imx7_csi, notifier);
203 static u32 imx7_csi_reg_read(struct imx7_csi *csi, unsigned int offset)
205 return readl(csi->regbase + offset);
208 static void imx7_csi_reg_write(struct imx7_csi *csi, unsigned int value,
211 writel(value, csi->regbase + offset);
214 static void imx7_csi_hw_reset(struct imx7_csi *csi)
216 imx7_csi_reg_write(csi,
217 imx7_csi_reg_read(csi, CSI_CSICR3) | BIT_FRMCNT_RST,
220 imx7_csi_reg_write(csi, CSICR1_RESET_VAL, CSI_CSICR1);
221 imx7_csi_reg_write(csi, CSICR2_RESET_VAL, CSI_CSICR2);
222 imx7_csi_reg_write(csi, CSICR3_RESET_VAL, CSI_CSICR3);
225 static u32 imx7_csi_irq_clear(struct imx7_csi *csi)
229 isr = imx7_csi_reg_read(csi, CSI_CSISR);
230 imx7_csi_reg_write(csi, isr, CSI_CSISR);
235 static void imx7_csi_init_interface(struct imx7_csi *csi)
237 unsigned int val = 0;
238 unsigned int imag_para;
240 val = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL |
241 BIT_FCC | 1 << SHIFT_MCLKDIV | BIT_MCLKEN;
242 imx7_csi_reg_write(csi, val, CSI_CSICR1);
244 imag_para = (800 << 16) | 600;
245 imx7_csi_reg_write(csi, imag_para, CSI_CSIIMAG_PARA);
247 val = BIT_DMA_REFLASH_RFF;
248 imx7_csi_reg_write(csi, val, CSI_CSICR3);
251 static void imx7_csi_hw_enable_irq(struct imx7_csi *csi)
253 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
255 cr1 |= BIT_SOF_INTEN;
256 cr1 |= BIT_RFF_OR_INT;
258 /* still capture needs DMA interrupt */
259 cr1 |= BIT_FB1_DMA_DONE_INTEN;
260 cr1 |= BIT_FB2_DMA_DONE_INTEN;
262 cr1 |= BIT_EOF_INT_EN;
264 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
267 static void imx7_csi_hw_disable_irq(struct imx7_csi *csi)
269 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
271 cr1 &= ~BIT_SOF_INTEN;
272 cr1 &= ~BIT_RFF_OR_INT;
273 cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
274 cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
275 cr1 &= ~BIT_EOF_INT_EN;
277 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
280 static void imx7_csi_hw_enable(struct imx7_csi *csi)
282 u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
284 cr |= BIT_CSI_HW_ENABLE;
286 imx7_csi_reg_write(csi, cr, CSI_CSICR18);
289 static void imx7_csi_hw_disable(struct imx7_csi *csi)
291 u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
293 cr &= ~BIT_CSI_HW_ENABLE;
295 imx7_csi_reg_write(csi, cr, CSI_CSICR18);
298 static void imx7_csi_dma_reflash(struct imx7_csi *csi)
302 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
303 cr3 |= BIT_DMA_REFLASH_RFF;
304 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
307 static void imx7_csi_rx_fifo_clear(struct imx7_csi *csi)
311 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
312 imx7_csi_reg_write(csi, cr1 & ~BIT_FCC, CSI_CSICR1);
313 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
314 imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
316 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
317 imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1);
320 static void imx7_csi_buf_stride_set(struct imx7_csi *csi, u32 stride)
322 imx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA);
325 static void imx7_csi_deinterlace_enable(struct imx7_csi *csi, bool enable)
327 u32 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
330 cr18 |= BIT_DEINTERLACE_EN;
332 cr18 &= ~BIT_DEINTERLACE_EN;
334 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
337 static void imx7_csi_dmareq_rff_enable(struct imx7_csi *csi)
339 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
340 u32 cr2 = imx7_csi_reg_read(csi, CSI_CSICR2);
342 /* Burst Type of DMA Transfer from RxFIFO. INCR16 */
345 cr3 |= BIT_DMA_REQ_EN_RFF;
346 cr3 |= BIT_HRESP_ERR_EN;
347 cr3 &= ~BIT_RXFF_LEVEL;
350 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
351 imx7_csi_reg_write(csi, cr2, CSI_CSICR2);
354 static void imx7_csi_dmareq_rff_disable(struct imx7_csi *csi)
356 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
358 cr3 &= ~BIT_DMA_REQ_EN_RFF;
359 cr3 &= ~BIT_HRESP_ERR_EN;
360 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
363 static void imx7_csi_set_imagpara(struct imx7_csi *csi, int width, int height)
368 rx_count = (width * height) >> 2;
369 imx7_csi_reg_write(csi, rx_count, CSI_CSIRXCNT);
371 imag_para = (width << 16) | height;
372 imx7_csi_reg_write(csi, imag_para, CSI_CSIIMAG_PARA);
374 /* reflash the embedded DMA controller */
375 imx7_csi_dma_reflash(csi);
378 static void imx7_csi_sw_reset(struct imx7_csi *csi)
380 imx7_csi_hw_disable(csi);
382 imx7_csi_rx_fifo_clear(csi);
384 imx7_csi_dma_reflash(csi);
386 usleep_range(2000, 3000);
388 imx7_csi_irq_clear(csi);
390 imx7_csi_hw_enable(csi);
393 static void imx7_csi_error_recovery(struct imx7_csi *csi)
395 imx7_csi_hw_disable(csi);
397 imx7_csi_rx_fifo_clear(csi);
399 imx7_csi_dma_reflash(csi);
401 imx7_csi_hw_enable(csi);
404 static int imx7_csi_init(struct imx7_csi *csi)
411 ret = clk_prepare_enable(csi->mclk);
414 imx7_csi_hw_reset(csi);
415 imx7_csi_init_interface(csi);
416 imx7_csi_dmareq_rff_enable(csi);
423 static void imx7_csi_deinit(struct imx7_csi *csi)
428 imx7_csi_hw_reset(csi);
429 imx7_csi_init_interface(csi);
430 imx7_csi_dmareq_rff_disable(csi);
431 clk_disable_unprepare(csi->mclk);
433 csi->is_init = false;
436 static int imx7_csi_link_setup(struct media_entity *entity,
437 const struct media_pad *local,
438 const struct media_pad *remote, u32 flags)
440 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
441 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
442 struct v4l2_subdev *remote_sd;
445 dev_dbg(csi->dev, "link setup %s -> %s\n", remote->entity->name,
446 local->entity->name);
448 mutex_lock(&csi->lock);
450 if (local->flags & MEDIA_PAD_FL_SINK) {
451 if (!is_media_entity_v4l2_subdev(remote->entity)) {
456 remote_sd = media_entity_to_v4l2_subdev(remote->entity);
458 if (flags & MEDIA_LNK_FL_ENABLED) {
463 csi->src_sd = remote_sd;
472 if (flags & MEDIA_LNK_FL_ENABLED) {
477 csi->sink = remote->entity;
479 v4l2_ctrl_handler_free(&csi->ctrl_hdlr);
480 v4l2_ctrl_handler_init(&csi->ctrl_hdlr, 0);
485 if (csi->sink || csi->src_sd)
486 ret = imx7_csi_init(csi);
488 imx7_csi_deinit(csi);
491 mutex_unlock(&csi->lock);
496 static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd,
497 struct media_link *link,
498 struct v4l2_subdev_format *source_fmt,
499 struct v4l2_subdev_format *sink_fmt)
501 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
502 struct media_entity *src;
503 struct media_pad *pad;
506 ret = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt);
513 src = &csi->src_sd->entity;
516 * if the source is neither a CSI MUX or CSI-2 get the one directly
517 * upstream from this CSI
519 if (src->function != MEDIA_ENT_F_VID_IF_BRIDGE &&
520 src->function != MEDIA_ENT_F_VID_MUX)
521 src = &csi->sd.entity;
524 * find the entity that is selected by the source. This is needed
525 * to distinguish between a parallel or CSI-2 pipeline.
527 pad = imx_media_pipeline_pad(src, 0, 0, true);
531 mutex_lock(&csi->lock);
533 csi->is_csi2 = (pad->entity->function == MEDIA_ENT_F_VID_IF_BRIDGE);
535 mutex_unlock(&csi->lock);
540 static void imx7_csi_update_buf(struct imx7_csi *csi, dma_addr_t phys,
544 imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB2);
546 imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB1);
549 static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi)
551 struct imx_media_video_dev *vdev = csi->vdev;
552 struct imx_media_buffer *buf;
553 struct vb2_buffer *vb2_buf;
557 for (i = 0; i < 2; i++) {
558 buf = imx_media_capture_device_next_buf(vdev);
560 csi->active_vb2_buf[i] = buf;
561 vb2_buf = &buf->vbuf.vb2_buf;
562 phys[i] = vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
564 csi->active_vb2_buf[i] = NULL;
565 phys[i] = csi->underrun_buf.phys;
568 imx7_csi_update_buf(csi, phys[i], i);
572 static void imx7_csi_dma_unsetup_vb2_buf(struct imx7_csi *csi,
573 enum vb2_buffer_state return_status)
575 struct imx_media_buffer *buf;
578 /* return any remaining active frames with return_status */
579 for (i = 0; i < 2; i++) {
580 buf = csi->active_vb2_buf[i];
582 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
584 vb->timestamp = ktime_get_ns();
585 vb2_buffer_done(vb, return_status);
590 static void imx7_csi_vb2_buf_done(struct imx7_csi *csi)
592 struct imx_media_video_dev *vdev = csi->vdev;
593 struct imx_media_buffer *done, *next;
594 struct vb2_buffer *vb;
597 done = csi->active_vb2_buf[csi->buf_num];
599 done->vbuf.field = vdev->fmt.fmt.pix.field;
600 done->vbuf.sequence = csi->frame_sequence;
601 vb = &done->vbuf.vb2_buf;
602 vb->timestamp = ktime_get_ns();
603 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
605 csi->frame_sequence++;
607 /* get next queued buffer */
608 next = imx_media_capture_device_next_buf(vdev);
610 phys = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0);
611 csi->active_vb2_buf[csi->buf_num] = next;
613 phys = csi->underrun_buf.phys;
614 csi->active_vb2_buf[csi->buf_num] = NULL;
617 imx7_csi_update_buf(csi, phys, csi->buf_num);
620 static irqreturn_t imx7_csi_irq_handler(int irq, void *data)
622 struct imx7_csi *csi = data;
625 spin_lock(&csi->irqlock);
627 status = imx7_csi_irq_clear(csi);
629 if (status & BIT_RFF_OR_INT) {
630 dev_warn(csi->dev, "Rx fifo overflow\n");
631 imx7_csi_error_recovery(csi);
634 if (status & BIT_HRESP_ERR_INT) {
635 dev_warn(csi->dev, "Hresponse error detected\n");
636 imx7_csi_error_recovery(csi);
639 if (status & BIT_ADDR_CH_ERR_INT) {
640 imx7_csi_hw_disable(csi);
642 imx7_csi_dma_reflash(csi);
644 imx7_csi_hw_enable(csi);
647 if ((status & BIT_DMA_TSF_DONE_FB1) &&
648 (status & BIT_DMA_TSF_DONE_FB2)) {
650 * For both FB1 and FB2 interrupter bits set case,
651 * CSI DMA is work in one of FB1 and FB2 buffer,
652 * but software can not know the state.
653 * Skip it to avoid base address updated
654 * when csi work in field0 and field1 will write to
657 } else if (status & BIT_DMA_TSF_DONE_FB1) {
659 } else if (status & BIT_DMA_TSF_DONE_FB2) {
663 if ((status & BIT_DMA_TSF_DONE_FB1) ||
664 (status & BIT_DMA_TSF_DONE_FB2)) {
665 imx7_csi_vb2_buf_done(csi);
668 complete(&csi->last_eof_completion);
669 csi->last_eof = false;
673 spin_unlock(&csi->irqlock);
678 static int imx7_csi_dma_start(struct imx7_csi *csi)
680 struct imx_media_video_dev *vdev = csi->vdev;
681 struct v4l2_pix_format *out_pix = &vdev->fmt.fmt.pix;
684 ret = imx_media_alloc_dma_buf(csi->dev, &csi->underrun_buf,
687 v4l2_warn(&csi->sd, "consider increasing the CMA area\n");
691 csi->frame_sequence = 0;
692 csi->last_eof = false;
693 init_completion(&csi->last_eof_completion);
695 imx7_csi_setup_vb2_buf(csi);
700 static void imx7_csi_dma_stop(struct imx7_csi *csi)
702 unsigned long timeout_jiffies;
706 /* mark next EOF interrupt as the last before stream off */
707 spin_lock_irqsave(&csi->irqlock, flags);
708 csi->last_eof = true;
709 spin_unlock_irqrestore(&csi->irqlock, flags);
712 * and then wait for interrupt handler to mark completion.
714 timeout_jiffies = msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT);
715 ret = wait_for_completion_timeout(&csi->last_eof_completion,
718 v4l2_warn(&csi->sd, "wait last EOF timeout\n");
720 imx7_csi_hw_disable_irq(csi);
722 imx7_csi_dma_unsetup_vb2_buf(csi, VB2_BUF_STATE_ERROR);
724 imx_media_free_dma_buf(csi->dev, &csi->underrun_buf);
727 static int imx7_csi_configure(struct imx7_csi *csi)
729 struct imx_media_video_dev *vdev = csi->vdev;
730 struct v4l2_pix_format *out_pix = &vdev->fmt.fmt.pix;
731 __u32 in_code = csi->format_mbus[IMX7_CSI_PAD_SINK].code;
733 int width = out_pix->width;
735 if (out_pix->field == V4L2_FIELD_INTERLACED) {
736 imx7_csi_deinterlace_enable(csi, true);
737 imx7_csi_buf_stride_set(csi, out_pix->width);
739 imx7_csi_deinterlace_enable(csi, false);
740 imx7_csi_buf_stride_set(csi, 0);
743 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
746 if (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||
747 out_pix->pixelformat == V4L2_PIX_FMT_YUYV)
750 imx7_csi_set_imagpara(csi, width, out_pix->height);
752 cr18 |= (BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
753 BIT_BASEADDR_CHG_ERR_EN);
754 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
759 imx7_csi_set_imagpara(csi, width, out_pix->height);
761 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
762 cr1 &= ~BIT_GCLK_MODE;
764 cr18 &= BIT_MIPI_DATA_FORMAT_MASK;
765 cr18 |= BIT_DATA_FROM_MIPI;
767 switch (out_pix->pixelformat) {
768 case V4L2_PIX_FMT_UYVY:
769 case V4L2_PIX_FMT_YUYV:
770 cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
772 case V4L2_PIX_FMT_GREY:
773 if (in_code == MEDIA_BUS_FMT_Y8_1X8)
774 cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
775 else if (in_code == MEDIA_BUS_FMT_Y10_1X10)
776 cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
778 cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
780 case V4L2_PIX_FMT_Y10:
781 cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
782 cr1 |= BIT_PIXEL_BIT;
784 case V4L2_PIX_FMT_Y12:
785 cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
786 cr1 |= BIT_PIXEL_BIT;
788 case V4L2_PIX_FMT_SBGGR8:
789 cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
791 case V4L2_PIX_FMT_SBGGR16:
792 if (in_code == MEDIA_BUS_FMT_SBGGR10_1X10)
793 cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
794 else if (in_code == MEDIA_BUS_FMT_SBGGR12_1X12)
795 cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
796 else if (in_code == MEDIA_BUS_FMT_SBGGR14_1X14)
797 cr18 |= BIT_MIPI_DATA_FORMAT_RAW14;
798 cr1 |= BIT_PIXEL_BIT;
804 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
805 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
810 static void imx7_csi_enable(struct imx7_csi *csi)
812 imx7_csi_sw_reset(csi);
814 imx7_csi_dmareq_rff_enable(csi);
815 imx7_csi_hw_enable_irq(csi);
816 imx7_csi_hw_enable(csi);
819 static void imx7_csi_disable(struct imx7_csi *csi)
821 imx7_csi_dmareq_rff_disable(csi);
823 imx7_csi_hw_disable_irq(csi);
825 imx7_csi_buf_stride_set(csi, 0);
827 imx7_csi_hw_disable(csi);
830 static int imx7_csi_streaming_start(struct imx7_csi *csi)
834 ret = imx7_csi_dma_start(csi);
838 ret = imx7_csi_configure(csi);
842 imx7_csi_enable(csi);
847 imx7_csi_dma_stop(csi);
852 static int imx7_csi_streaming_stop(struct imx7_csi *csi)
854 imx7_csi_dma_stop(csi);
856 imx7_csi_disable(csi);
861 static int imx7_csi_s_stream(struct v4l2_subdev *sd, int enable)
863 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
866 mutex_lock(&csi->lock);
868 if (!csi->src_sd || !csi->sink) {
873 if (csi->is_streaming == !!enable)
877 ret = v4l2_subdev_call(csi->src_sd, video, s_stream, 1);
881 ret = imx7_csi_streaming_start(csi);
883 v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
887 imx7_csi_streaming_stop(csi);
889 v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
892 csi->is_streaming = !!enable;
895 mutex_unlock(&csi->lock);
900 static struct v4l2_mbus_framefmt *
901 imx7_csi_get_format(struct imx7_csi *csi,
902 struct v4l2_subdev_pad_config *cfg,
904 enum v4l2_subdev_format_whence which)
906 if (which == V4L2_SUBDEV_FORMAT_TRY)
907 return v4l2_subdev_get_try_format(&csi->sd, cfg, pad);
909 return &csi->format_mbus[pad];
912 static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd,
913 struct v4l2_subdev_pad_config *cfg,
914 struct v4l2_subdev_mbus_code_enum *code)
916 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
917 struct v4l2_mbus_framefmt *in_fmt;
920 mutex_lock(&csi->lock);
922 in_fmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SINK, code->which);
925 case IMX7_CSI_PAD_SINK:
926 ret = imx_media_enum_mbus_formats(&code->code, code->index,
929 case IMX7_CSI_PAD_SRC:
930 if (code->index != 0) {
935 code->code = in_fmt->code;
942 mutex_unlock(&csi->lock);
947 static int imx7_csi_get_fmt(struct v4l2_subdev *sd,
948 struct v4l2_subdev_pad_config *cfg,
949 struct v4l2_subdev_format *sdformat)
951 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
952 struct v4l2_mbus_framefmt *fmt;
955 mutex_lock(&csi->lock);
957 fmt = imx7_csi_get_format(csi, cfg, sdformat->pad, sdformat->which);
963 sdformat->format = *fmt;
966 mutex_unlock(&csi->lock);
971 static int imx7_csi_try_fmt(struct imx7_csi *csi,
972 struct v4l2_subdev_pad_config *cfg,
973 struct v4l2_subdev_format *sdformat,
974 const struct imx_media_pixfmt **cc)
976 const struct imx_media_pixfmt *in_cc;
977 struct v4l2_mbus_framefmt *in_fmt;
980 in_fmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SINK,
985 switch (sdformat->pad) {
986 case IMX7_CSI_PAD_SRC:
987 in_cc = imx_media_find_mbus_format(in_fmt->code,
990 sdformat->format.width = in_fmt->width;
991 sdformat->format.height = in_fmt->height;
992 sdformat->format.code = in_fmt->code;
993 sdformat->format.field = in_fmt->field;
996 sdformat->format.colorspace = in_fmt->colorspace;
997 sdformat->format.xfer_func = in_fmt->xfer_func;
998 sdformat->format.quantization = in_fmt->quantization;
999 sdformat->format.ycbcr_enc = in_fmt->ycbcr_enc;
1001 case IMX7_CSI_PAD_SINK:
1002 *cc = imx_media_find_mbus_format(sdformat->format.code,
1005 imx_media_enum_mbus_formats(&code, 0,
1006 PIXFMT_SEL_YUV_RGB);
1007 *cc = imx_media_find_mbus_format(code,
1008 PIXFMT_SEL_YUV_RGB);
1009 sdformat->format.code = (*cc)->codes[0];
1012 if (sdformat->format.field != V4L2_FIELD_INTERLACED)
1013 sdformat->format.field = V4L2_FIELD_NONE;
1019 imx_media_try_colorimetry(&sdformat->format, false);
1024 static int imx7_csi_set_fmt(struct v4l2_subdev *sd,
1025 struct v4l2_subdev_pad_config *cfg,
1026 struct v4l2_subdev_format *sdformat)
1028 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1029 const struct imx_media_pixfmt *outcc;
1030 struct v4l2_mbus_framefmt *outfmt;
1031 const struct imx_media_pixfmt *cc;
1032 struct v4l2_mbus_framefmt *fmt;
1033 struct v4l2_subdev_format format;
1036 if (sdformat->pad >= IMX7_CSI_PADS_NUM)
1039 mutex_lock(&csi->lock);
1041 if (csi->is_streaming) {
1046 ret = imx7_csi_try_fmt(csi, cfg, sdformat, &cc);
1050 fmt = imx7_csi_get_format(csi, cfg, sdformat->pad, sdformat->which);
1056 *fmt = sdformat->format;
1058 if (sdformat->pad == IMX7_CSI_PAD_SINK) {
1059 /* propagate format to source pads */
1060 format.pad = IMX7_CSI_PAD_SRC;
1061 format.which = sdformat->which;
1062 format.format = sdformat->format;
1063 if (imx7_csi_try_fmt(csi, cfg, &format, &outcc)) {
1067 outfmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SRC,
1069 *outfmt = format.format;
1071 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1072 csi->cc[IMX7_CSI_PAD_SRC] = outcc;
1075 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1076 csi->cc[sdformat->pad] = cc;
1079 mutex_unlock(&csi->lock);
1084 static int imx7_csi_registered(struct v4l2_subdev *sd)
1086 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1090 for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
1091 /* set a default mbus format */
1092 ret = imx_media_init_mbus_fmt(&csi->format_mbus[i],
1093 800, 600, 0, V4L2_FIELD_NONE,
1098 /* init default frame interval */
1099 csi->frame_interval[i].numerator = 1;
1100 csi->frame_interval[i].denominator = 30;
1103 csi->vdev = imx_media_capture_device_init(csi->sd.dev, &csi->sd,
1105 if (IS_ERR(csi->vdev))
1106 return PTR_ERR(csi->vdev);
1108 ret = imx_media_capture_device_register(csi->vdev);
1110 imx_media_capture_device_remove(csi->vdev);
1115 static void imx7_csi_unregistered(struct v4l2_subdev *sd)
1117 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1119 imx_media_capture_device_unregister(csi->vdev);
1120 imx_media_capture_device_remove(csi->vdev);
1123 static int imx7_csi_init_cfg(struct v4l2_subdev *sd,
1124 struct v4l2_subdev_pad_config *cfg)
1126 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1127 struct v4l2_mbus_framefmt *mf;
1131 for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
1132 mf = v4l2_subdev_get_try_format(sd, cfg, i);
1134 ret = imx_media_init_mbus_fmt(mf, 800, 600, 0, V4L2_FIELD_NONE,
1143 static const struct media_entity_operations imx7_csi_entity_ops = {
1144 .link_setup = imx7_csi_link_setup,
1145 .link_validate = v4l2_subdev_link_validate,
1146 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1149 static const struct v4l2_subdev_video_ops imx7_csi_video_ops = {
1150 .s_stream = imx7_csi_s_stream,
1153 static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = {
1154 .init_cfg = imx7_csi_init_cfg,
1155 .enum_mbus_code = imx7_csi_enum_mbus_code,
1156 .get_fmt = imx7_csi_get_fmt,
1157 .set_fmt = imx7_csi_set_fmt,
1158 .link_validate = imx7_csi_pad_link_validate,
1161 static const struct v4l2_subdev_ops imx7_csi_subdev_ops = {
1162 .video = &imx7_csi_video_ops,
1163 .pad = &imx7_csi_pad_ops,
1166 static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = {
1167 .registered = imx7_csi_registered,
1168 .unregistered = imx7_csi_unregistered,
1171 static int imx7_csi_notify_bound(struct v4l2_async_notifier *notifier,
1172 struct v4l2_subdev *sd,
1173 struct v4l2_async_subdev *asd)
1175 struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier);
1176 struct media_pad *sink = &csi->sd.entity.pads[IMX7_CSI_PAD_SINK];
1179 * If the subdev is a video mux, it must be one of the CSI
1180 * muxes. Mark it as such via its group id.
1182 if (sd->entity.function == MEDIA_ENT_F_VID_MUX)
1183 sd->grp_id = IMX_MEDIA_GRP_ID_CSI_MUX;
1185 return v4l2_create_fwnode_links_to_pad(sd, sink);
1188 static const struct v4l2_async_notifier_operations imx7_csi_notify_ops = {
1189 .bound = imx7_csi_notify_bound,
1192 static int imx7_csi_async_register(struct imx7_csi *csi)
1194 struct v4l2_async_subdev *asd;
1195 struct fwnode_handle *ep;
1198 v4l2_async_notifier_init(&csi->notifier);
1200 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
1201 FWNODE_GRAPH_ENDPOINT_NEXT);
1203 asd = v4l2_async_notifier_add_fwnode_remote_subdev(
1204 &csi->notifier, ep, sizeof(*asd));
1206 fwnode_handle_put(ep);
1210 /* OK if asd already exists */
1216 csi->notifier.ops = &imx7_csi_notify_ops;
1218 ret = v4l2_async_subdev_notifier_register(&csi->sd, &csi->notifier);
1222 return v4l2_async_register_subdev(&csi->sd);
1225 static int imx7_csi_probe(struct platform_device *pdev)
1227 struct device *dev = &pdev->dev;
1228 struct device_node *node = dev->of_node;
1229 struct imx_media_dev *imxmd;
1230 struct imx7_csi *csi;
1233 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
1239 csi->mclk = devm_clk_get(&pdev->dev, "mclk");
1240 if (IS_ERR(csi->mclk)) {
1241 ret = PTR_ERR(csi->mclk);
1242 dev_err(dev, "Failed to get mclk: %d", ret);
1246 csi->irq = platform_get_irq(pdev, 0);
1250 csi->regbase = devm_platform_ioremap_resource(pdev, 0);
1251 if (IS_ERR(csi->regbase))
1252 return PTR_ERR(csi->regbase);
1254 spin_lock_init(&csi->irqlock);
1255 mutex_init(&csi->lock);
1257 /* install interrupt handler */
1258 ret = devm_request_irq(dev, csi->irq, imx7_csi_irq_handler, 0, "csi",
1261 dev_err(dev, "Request CSI IRQ failed.\n");
1265 /* add media device */
1266 imxmd = imx_media_dev_init(dev, NULL);
1267 if (IS_ERR(imxmd)) {
1268 ret = PTR_ERR(imxmd);
1271 platform_set_drvdata(pdev, &csi->sd);
1273 ret = imx_media_of_add_csi(imxmd, node);
1274 if (ret < 0 && ret != -ENODEV && ret != -EEXIST)
1277 ret = imx_media_dev_notifier_register(imxmd, NULL);
1282 v4l2_subdev_init(&csi->sd, &imx7_csi_subdev_ops);
1283 v4l2_set_subdevdata(&csi->sd, csi);
1284 csi->sd.internal_ops = &imx7_csi_internal_ops;
1285 csi->sd.entity.ops = &imx7_csi_entity_ops;
1286 csi->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1287 csi->sd.dev = &pdev->dev;
1288 csi->sd.owner = THIS_MODULE;
1289 csi->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1290 csi->sd.grp_id = IMX_MEDIA_GRP_ID_CSI;
1291 snprintf(csi->sd.name, sizeof(csi->sd.name), "csi");
1293 v4l2_ctrl_handler_init(&csi->ctrl_hdlr, 0);
1294 csi->sd.ctrl_handler = &csi->ctrl_hdlr;
1296 for (i = 0; i < IMX7_CSI_PADS_NUM; i++)
1297 csi->pad[i].flags = (i == IMX7_CSI_PAD_SINK) ?
1298 MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
1300 ret = media_entity_pads_init(&csi->sd.entity, IMX7_CSI_PADS_NUM,
1305 ret = imx7_csi_async_register(csi);
1307 goto subdev_notifier_cleanup;
1311 subdev_notifier_cleanup:
1312 v4l2_async_notifier_unregister(&csi->notifier);
1313 v4l2_async_notifier_cleanup(&csi->notifier);
1316 v4l2_ctrl_handler_free(&csi->ctrl_hdlr);
1319 v4l2_async_notifier_unregister(&imxmd->notifier);
1320 v4l2_async_notifier_cleanup(&imxmd->notifier);
1321 v4l2_device_unregister(&imxmd->v4l2_dev);
1322 media_device_unregister(&imxmd->md);
1323 media_device_cleanup(&imxmd->md);
1326 mutex_destroy(&csi->lock);
1331 static int imx7_csi_remove(struct platform_device *pdev)
1333 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1334 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1335 struct imx_media_dev *imxmd = csi->imxmd;
1337 v4l2_async_notifier_unregister(&imxmd->notifier);
1338 v4l2_async_notifier_cleanup(&imxmd->notifier);
1340 media_device_unregister(&imxmd->md);
1341 v4l2_device_unregister(&imxmd->v4l2_dev);
1342 media_device_cleanup(&imxmd->md);
1344 v4l2_async_notifier_unregister(&csi->notifier);
1345 v4l2_async_notifier_cleanup(&csi->notifier);
1346 v4l2_async_unregister_subdev(sd);
1347 v4l2_ctrl_handler_free(&csi->ctrl_hdlr);
1349 mutex_destroy(&csi->lock);
1354 static const struct of_device_id imx7_csi_of_match[] = {
1355 { .compatible = "fsl,imx7-csi" },
1356 { .compatible = "fsl,imx6ul-csi" },
1359 MODULE_DEVICE_TABLE(of, imx7_csi_of_match);
1361 static struct platform_driver imx7_csi_driver = {
1362 .probe = imx7_csi_probe,
1363 .remove = imx7_csi_remove,
1365 .of_match_table = imx7_csi_of_match,
1369 module_platform_driver(imx7_csi_driver);
1371 MODULE_DESCRIPTION("i.MX7 CSI subdev driver");
1372 MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
1373 MODULE_LICENSE("GPL v2");
1374 MODULE_ALIAS("platform:imx7-csi");