1 // SPDX-License-Identifier: GPL-2.0+
3 * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
5 * Copyright (c) 2012-2017 Mentor Graphics Inc.
8 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/of_graph.h>
14 #include <linux/platform_device.h>
15 #include <media/v4l2-common.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-fwnode.h>
18 #include <media/v4l2-mc.h>
19 #include <media/v4l2-subdev.h>
20 #include "imx-media.h"
23 * there must be 5 pads: 1 input pad from sensor, and
24 * the 4 virtual channel output pads
26 #define CSI2_SINK_PAD 0
27 #define CSI2_NUM_SINK_PADS 1
28 #define CSI2_NUM_SRC_PADS 4
29 #define CSI2_NUM_PADS 5
32 * The default maximum bit-rate per lane in Mbps, if the
33 * source subdev does not provide V4L2_CID_LINK_FREQ.
35 #define CSI2_DEFAULT_MAX_MBPS 849
39 struct v4l2_subdev sd;
40 struct v4l2_async_notifier notifier;
41 struct media_pad pad[CSI2_NUM_PADS];
43 struct clk *pllref_clk;
44 struct clk *pix_clk; /* what is this? */
47 struct v4l2_subdev *remote;
48 unsigned int remote_pad;
49 unsigned short data_lanes;
51 /* lock to protect all members below */
54 struct v4l2_mbus_framefmt format_mbus;
57 struct v4l2_subdev *src_sd;
58 bool sink_linked[CSI2_NUM_SRC_PADS];
61 #define DEVICE_NAME "imx6-mipi-csi2"
63 /* Register offsets */
64 #define CSI2_VERSION 0x000
65 #define CSI2_N_LANES 0x004
66 #define CSI2_PHY_SHUTDOWNZ 0x008
67 #define CSI2_DPHY_RSTZ 0x00c
68 #define CSI2_RESETN 0x010
69 #define CSI2_PHY_STATE 0x014
70 #define PHY_STOPSTATEDATA_BIT 4
71 #define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n))
72 #define PHY_RXCLKACTIVEHS BIT(8)
73 #define PHY_RXULPSCLKNOT BIT(9)
74 #define PHY_STOPSTATECLK BIT(10)
75 #define CSI2_DATA_IDS_1 0x018
76 #define CSI2_DATA_IDS_2 0x01c
77 #define CSI2_ERR1 0x020
78 #define CSI2_ERR2 0x024
79 #define CSI2_MSK1 0x028
80 #define CSI2_MSK2 0x02c
81 #define CSI2_PHY_TST_CTRL0 0x030
82 #define PHY_TESTCLR BIT(0)
83 #define PHY_TESTCLK BIT(1)
84 #define CSI2_PHY_TST_CTRL1 0x034
85 #define PHY_TESTEN BIT(16)
87 * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is
88 * not part of the MIPI CSI-2 core, but its registers fall in the
89 * same register map range.
91 #define CSI2IPU_GASKET 0xf00
92 #define CSI2IPU_YUV422_YUYV BIT(2)
94 static inline struct csi2_dev *sd_to_dev(struct v4l2_subdev *sdev)
96 return container_of(sdev, struct csi2_dev, sd);
99 static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n)
101 return container_of(n, struct csi2_dev, notifier);
105 * The required sequence of MIPI CSI-2 startup as specified in the i.MX6
106 * reference manual is as follows:
108 * 1. Deassert presetn signal (global reset).
109 * It's not clear what this "global reset" signal is (maybe APB
110 * global reset), but in any case this step would be probably
111 * be carried out during driver load in csi2_probe().
113 * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
114 * This must be carried out by the MIPI sensor's s_power(ON) subdev
117 * 3. D-PHY initialization.
118 * 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ,
119 * deassert PHY_RSTZ, deassert CSI2_RESETN).
120 * 5. Read the PHY status register (PHY_STATE) to confirm that all data and
121 * clock lanes of the D-PHY are in LP-11 state.
122 * 6. Configure the MIPI Camera Sensor to start transmitting a clock on the
124 * 7. CSI2 Controller programming - Read the PHY status register (PHY_STATE)
125 * to confirm that the D-PHY is receiving a clock on the D-PHY clock lane.
127 * All steps 3 through 7 are carried out by csi2_s_stream(ON) here. Step
128 * 6 is accomplished by calling the source subdev's s_stream(ON) between
132 static void csi2_enable(struct csi2_dev *csi2, bool enable)
135 writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ);
136 writel(0x1, csi2->base + CSI2_DPHY_RSTZ);
137 writel(0x1, csi2->base + CSI2_RESETN);
139 writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ);
140 writel(0x0, csi2->base + CSI2_DPHY_RSTZ);
141 writel(0x0, csi2->base + CSI2_RESETN);
145 static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes)
147 writel(lanes - 1, csi2->base + CSI2_N_LANES);
150 static void dw_mipi_csi2_phy_write(struct csi2_dev *csi2,
151 u32 test_code, u32 test_data)
153 /* Clear PHY test interface */
154 writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0);
155 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1);
156 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
158 /* Raise test interface strobe signal */
159 writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
161 /* Configure address write on falling edge and lower strobe signal */
162 writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1);
163 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
165 /* Configure data write on rising edge and raise strobe signal */
166 writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1);
167 writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
169 /* Clear strobe signal */
170 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
174 * This table is based on the table documented at
175 * https://community.nxp.com/docs/DOC-94312. It assumes
176 * a 27MHz D-PHY pll reference clock.
178 static const struct {
182 { 90, 0x00}, {100, 0x20}, {110, 0x40}, {125, 0x02},
183 {140, 0x22}, {150, 0x42}, {160, 0x04}, {180, 0x24},
184 {200, 0x44}, {210, 0x06}, {240, 0x26}, {250, 0x46},
185 {270, 0x08}, {300, 0x28}, {330, 0x48}, {360, 0x2a},
186 {400, 0x4a}, {450, 0x0c}, {500, 0x2c}, {550, 0x0e},
187 {600, 0x2e}, {650, 0x10}, {700, 0x30}, {750, 0x12},
188 {800, 0x32}, {850, 0x14}, {900, 0x34}, {950, 0x54},
192 static int max_mbps_to_hsfreqrange_sel(u32 max_mbps)
196 for (i = 0; i < ARRAY_SIZE(hsfreq_map); i++)
197 if (hsfreq_map[i].max_mbps > max_mbps)
198 return hsfreq_map[i].hsfreqrange_sel;
203 static int csi2_dphy_init(struct csi2_dev *csi2)
205 struct v4l2_ctrl *ctrl;
209 ctrl = v4l2_ctrl_find(csi2->src_sd->ctrl_handler,
212 mbps_per_lane = CSI2_DEFAULT_MAX_MBPS;
214 mbps_per_lane = DIV_ROUND_UP_ULL(2 * ctrl->qmenu_int[ctrl->val],
217 sel = max_mbps_to_hsfreqrange_sel(mbps_per_lane);
221 dw_mipi_csi2_phy_write(csi2, 0x44, sel);
227 * Waits for ultra-low-power state on D-PHY clock lane. This is currently
228 * unused and may not be needed at all, but keep around just in case.
230 static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2)
235 /* wait for ULP on clock lane */
236 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
237 !(reg & PHY_RXULPSCLKNOT), 0, 500000);
239 v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg);
243 /* wait until no errors on bus */
244 ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg,
245 reg == 0x0, 0, 500000);
247 v4l2_err(&csi2->sd, "stable bus timeout, err1 = 0x%08x\n", reg);
254 /* Waits for low-power LP-11 state on data and clock lanes. */
255 static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes)
260 mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT);
262 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
263 (reg & mask) == mask, 0, 500000);
265 v4l2_warn(&csi2->sd, "LP-11 wait timeout, likely a sensor driver bug, expect capture failures.\n");
266 v4l2_warn(&csi2->sd, "phy_state = 0x%08x\n", reg);
270 /* Wait for active clock on the clock lane. */
271 static int csi2_dphy_wait_clock_lane(struct csi2_dev *csi2)
276 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
277 (reg & PHY_RXCLKACTIVEHS), 0, 500000);
279 v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n",
287 /* Setup the i.MX CSI2IPU Gasket */
288 static void csi2ipu_gasket_init(struct csi2_dev *csi2)
292 switch (csi2->format_mbus.code) {
293 case MEDIA_BUS_FMT_YUYV8_2X8:
294 case MEDIA_BUS_FMT_YUYV8_1X16:
295 reg = CSI2IPU_YUV422_YUYV;
301 writel(reg, csi2->base + CSI2IPU_GASKET);
304 static int csi2_get_active_lanes(struct csi2_dev *csi2, unsigned int *lanes)
306 struct v4l2_mbus_config mbus_config = { 0 };
309 *lanes = csi2->data_lanes;
311 ret = v4l2_subdev_call(csi2->remote, pad, get_mbus_config,
312 csi2->remote_pad, &mbus_config);
313 if (ret == -ENOIOCTLCMD) {
314 dev_dbg(csi2->dev, "No remote mbus configuration available\n");
319 dev_err(csi2->dev, "Failed to get remote mbus configuration\n");
323 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
324 dev_err(csi2->dev, "Unsupported media bus type %u\n",
329 if (mbus_config.bus.mipi_csi2.num_data_lanes > csi2->data_lanes) {
331 "Unsupported mbus config: too many data lanes %u\n",
332 mbus_config.bus.mipi_csi2.num_data_lanes);
336 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes;
341 static int csi2_start(struct csi2_dev *csi2)
346 ret = clk_prepare_enable(csi2->pix_clk);
350 /* setup the gasket */
351 csi2ipu_gasket_init(csi2);
354 ret = csi2_dphy_init(csi2);
356 goto err_disable_clk;
358 ret = csi2_get_active_lanes(csi2, &lanes);
360 goto err_disable_clk;
363 csi2_set_lanes(csi2, lanes);
364 csi2_enable(csi2, true);
367 ret = v4l2_subdev_call(csi2->src_sd, video, pre_streamon,
368 V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP);
369 if (ret && ret != -ENOIOCTLCMD)
370 goto err_assert_reset;
371 csi2_dphy_wait_stopstate(csi2, lanes);
374 ret = v4l2_subdev_call(csi2->src_sd, video, s_stream, 1);
375 ret = (ret && ret != -ENOIOCTLCMD) ? ret : 0;
380 ret = csi2_dphy_wait_clock_lane(csi2);
382 goto err_stop_upstream;
387 v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
389 v4l2_subdev_call(csi2->src_sd, video, post_streamoff);
391 csi2_enable(csi2, false);
393 clk_disable_unprepare(csi2->pix_clk);
397 static void csi2_stop(struct csi2_dev *csi2)
400 v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
401 v4l2_subdev_call(csi2->src_sd, video, post_streamoff);
403 csi2_enable(csi2, false);
404 clk_disable_unprepare(csi2->pix_clk);
408 * V4L2 subdev operations.
411 static int csi2_s_stream(struct v4l2_subdev *sd, int enable)
413 struct csi2_dev *csi2 = sd_to_dev(sd);
416 mutex_lock(&csi2->lock);
423 for (i = 0; i < CSI2_NUM_SRC_PADS; i++) {
424 if (csi2->sink_linked[i])
427 if (i >= CSI2_NUM_SRC_PADS) {
433 * enable/disable streaming only if stream_count is
434 * going from 0 to 1 / 1 to 0.
436 if (csi2->stream_count != !enable)
439 dev_dbg(csi2->dev, "stream %s\n", enable ? "ON" : "OFF");
441 ret = csi2_start(csi2);
448 csi2->stream_count += enable ? 1 : -1;
449 if (csi2->stream_count < 0)
450 csi2->stream_count = 0;
452 mutex_unlock(&csi2->lock);
456 static int csi2_link_setup(struct media_entity *entity,
457 const struct media_pad *local,
458 const struct media_pad *remote, u32 flags)
460 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
461 struct csi2_dev *csi2 = sd_to_dev(sd);
462 struct v4l2_subdev *remote_sd;
465 dev_dbg(csi2->dev, "link setup %s -> %s", remote->entity->name,
466 local->entity->name);
468 remote_sd = media_entity_to_v4l2_subdev(remote->entity);
470 mutex_lock(&csi2->lock);
472 if (local->flags & MEDIA_PAD_FL_SOURCE) {
473 if (flags & MEDIA_LNK_FL_ENABLED) {
474 if (csi2->sink_linked[local->index - 1]) {
478 csi2->sink_linked[local->index - 1] = true;
480 csi2->sink_linked[local->index - 1] = false;
483 if (flags & MEDIA_LNK_FL_ENABLED) {
488 csi2->src_sd = remote_sd;
495 mutex_unlock(&csi2->lock);
499 static struct v4l2_mbus_framefmt *
500 __csi2_get_fmt(struct csi2_dev *csi2, struct v4l2_subdev_state *sd_state,
501 unsigned int pad, enum v4l2_subdev_format_whence which)
503 if (which == V4L2_SUBDEV_FORMAT_TRY)
504 return v4l2_subdev_state_get_format(sd_state, pad);
506 return &csi2->format_mbus;
509 static int csi2_get_fmt(struct v4l2_subdev *sd,
510 struct v4l2_subdev_state *sd_state,
511 struct v4l2_subdev_format *sdformat)
513 struct csi2_dev *csi2 = sd_to_dev(sd);
514 struct v4l2_mbus_framefmt *fmt;
516 mutex_lock(&csi2->lock);
518 fmt = __csi2_get_fmt(csi2, sd_state, sdformat->pad, sdformat->which);
520 sdformat->format = *fmt;
522 mutex_unlock(&csi2->lock);
527 static int csi2_set_fmt(struct v4l2_subdev *sd,
528 struct v4l2_subdev_state *sd_state,
529 struct v4l2_subdev_format *sdformat)
531 struct csi2_dev *csi2 = sd_to_dev(sd);
532 struct v4l2_mbus_framefmt *fmt;
535 if (sdformat->pad >= CSI2_NUM_PADS)
538 mutex_lock(&csi2->lock);
540 if (csi2->stream_count > 0) {
545 /* Output pads mirror active input pad, no limits on input pads */
546 if (sdformat->pad != CSI2_SINK_PAD)
547 sdformat->format = csi2->format_mbus;
549 fmt = __csi2_get_fmt(csi2, sd_state, sdformat->pad, sdformat->which);
551 *fmt = sdformat->format;
553 mutex_unlock(&csi2->lock);
557 static int csi2_registered(struct v4l2_subdev *sd)
559 struct csi2_dev *csi2 = sd_to_dev(sd);
561 /* set a default mbus format */
562 return imx_media_init_mbus_fmt(&csi2->format_mbus,
563 IMX_MEDIA_DEF_PIX_WIDTH,
564 IMX_MEDIA_DEF_PIX_HEIGHT, 0,
565 V4L2_FIELD_NONE, NULL);
568 /* --------------- CORE OPS --------------- */
570 static int csi2_log_status(struct v4l2_subdev *sd)
572 struct csi2_dev *csi2 = sd_to_dev(sd);
574 v4l2_info(sd, "-----MIPI CSI status-----\n");
575 v4l2_info(sd, "VERSION: 0x%x\n",
576 readl(csi2->base + CSI2_VERSION));
577 v4l2_info(sd, "N_LANES: 0x%x\n",
578 readl(csi2->base + CSI2_N_LANES));
579 v4l2_info(sd, "PHY_SHUTDOWNZ: 0x%x\n",
580 readl(csi2->base + CSI2_PHY_SHUTDOWNZ));
581 v4l2_info(sd, "DPHY_RSTZ: 0x%x\n",
582 readl(csi2->base + CSI2_DPHY_RSTZ));
583 v4l2_info(sd, "RESETN: 0x%x\n",
584 readl(csi2->base + CSI2_RESETN));
585 v4l2_info(sd, "PHY_STATE: 0x%x\n",
586 readl(csi2->base + CSI2_PHY_STATE));
587 v4l2_info(sd, "DATA_IDS_1: 0x%x\n",
588 readl(csi2->base + CSI2_DATA_IDS_1));
589 v4l2_info(sd, "DATA_IDS_2: 0x%x\n",
590 readl(csi2->base + CSI2_DATA_IDS_2));
591 v4l2_info(sd, "ERR1: 0x%x\n",
592 readl(csi2->base + CSI2_ERR1));
593 v4l2_info(sd, "ERR2: 0x%x\n",
594 readl(csi2->base + CSI2_ERR2));
595 v4l2_info(sd, "MSK1: 0x%x\n",
596 readl(csi2->base + CSI2_MSK1));
597 v4l2_info(sd, "MSK2: 0x%x\n",
598 readl(csi2->base + CSI2_MSK2));
599 v4l2_info(sd, "PHY_TST_CTRL0: 0x%x\n",
600 readl(csi2->base + CSI2_PHY_TST_CTRL0));
601 v4l2_info(sd, "PHY_TST_CTRL1: 0x%x\n",
602 readl(csi2->base + CSI2_PHY_TST_CTRL1));
607 static const struct v4l2_subdev_core_ops csi2_core_ops = {
608 .log_status = csi2_log_status,
611 static const struct media_entity_operations csi2_entity_ops = {
612 .link_setup = csi2_link_setup,
613 .link_validate = v4l2_subdev_link_validate,
614 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
617 static const struct v4l2_subdev_video_ops csi2_video_ops = {
618 .s_stream = csi2_s_stream,
621 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
622 .get_fmt = csi2_get_fmt,
623 .set_fmt = csi2_set_fmt,
626 static const struct v4l2_subdev_ops csi2_subdev_ops = {
627 .core = &csi2_core_ops,
628 .video = &csi2_video_ops,
629 .pad = &csi2_pad_ops,
632 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
633 .init_state = imx_media_init_state,
634 .registered = csi2_registered,
637 static int csi2_notify_bound(struct v4l2_async_notifier *notifier,
638 struct v4l2_subdev *sd,
639 struct v4l2_async_connection *asd)
641 struct csi2_dev *csi2 = notifier_to_dev(notifier);
642 struct media_pad *sink = &csi2->sd.entity.pads[CSI2_SINK_PAD];
645 pad = media_entity_get_fwnode_pad(&sd->entity, asd->match.fwnode,
646 MEDIA_PAD_FL_SOURCE);
648 dev_err(csi2->dev, "Failed to find pad for %s\n", sd->name);
653 csi2->remote_pad = pad;
655 dev_dbg(csi2->dev, "Bound %s pad: %d\n", sd->name, pad);
657 return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
660 static void csi2_notify_unbind(struct v4l2_async_notifier *notifier,
661 struct v4l2_subdev *sd,
662 struct v4l2_async_connection *asd)
664 struct csi2_dev *csi2 = notifier_to_dev(notifier);
669 static const struct v4l2_async_notifier_operations csi2_notify_ops = {
670 .bound = csi2_notify_bound,
671 .unbind = csi2_notify_unbind,
674 static int csi2_async_register(struct csi2_dev *csi2)
676 struct v4l2_fwnode_endpoint vep = {
677 .bus_type = V4L2_MBUS_CSI2_DPHY,
679 struct v4l2_async_connection *asd;
680 struct fwnode_handle *ep;
683 v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->sd);
685 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0,
686 FWNODE_GRAPH_ENDPOINT_NEXT);
690 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
694 csi2->data_lanes = vep.bus.mipi_csi2.num_data_lanes;
696 dev_dbg(csi2->dev, "data lanes: %d\n", vep.bus.mipi_csi2.num_data_lanes);
697 dev_dbg(csi2->dev, "flags: 0x%08x\n", vep.bus.mipi_csi2.flags);
699 asd = v4l2_async_nf_add_fwnode_remote(&csi2->notifier, ep,
700 struct v4l2_async_connection);
701 fwnode_handle_put(ep);
706 csi2->notifier.ops = &csi2_notify_ops;
708 ret = v4l2_async_nf_register(&csi2->notifier);
712 return v4l2_async_register_subdev(&csi2->sd);
715 fwnode_handle_put(ep);
719 static int csi2_probe(struct platform_device *pdev)
721 struct csi2_dev *csi2;
722 struct resource *res;
725 csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);
729 csi2->dev = &pdev->dev;
731 v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops);
732 v4l2_set_subdevdata(&csi2->sd, &pdev->dev);
733 csi2->sd.internal_ops = &csi2_internal_ops;
734 csi2->sd.entity.ops = &csi2_entity_ops;
735 csi2->sd.dev = &pdev->dev;
736 csi2->sd.owner = THIS_MODULE;
737 csi2->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
738 strscpy(csi2->sd.name, DEVICE_NAME, sizeof(csi2->sd.name));
739 csi2->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
740 csi2->sd.grp_id = IMX_MEDIA_GRP_ID_CSI2;
742 for (i = 0; i < CSI2_NUM_PADS; i++) {
743 csi2->pad[i].flags = (i == CSI2_SINK_PAD) ?
744 MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
747 ret = media_entity_pads_init(&csi2->sd.entity, CSI2_NUM_PADS,
752 csi2->pllref_clk = devm_clk_get(&pdev->dev, "ref");
753 if (IS_ERR(csi2->pllref_clk)) {
754 v4l2_err(&csi2->sd, "failed to get pll reference clock\n");
755 return PTR_ERR(csi2->pllref_clk);
758 csi2->dphy_clk = devm_clk_get(&pdev->dev, "dphy");
759 if (IS_ERR(csi2->dphy_clk)) {
760 v4l2_err(&csi2->sd, "failed to get dphy clock\n");
761 return PTR_ERR(csi2->dphy_clk);
764 csi2->pix_clk = devm_clk_get(&pdev->dev, "pix");
765 if (IS_ERR(csi2->pix_clk)) {
766 v4l2_err(&csi2->sd, "failed to get pixel clock\n");
767 return PTR_ERR(csi2->pix_clk);
770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
772 v4l2_err(&csi2->sd, "failed to get platform resources\n");
776 csi2->base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
780 mutex_init(&csi2->lock);
782 ret = clk_prepare_enable(csi2->pllref_clk);
784 v4l2_err(&csi2->sd, "failed to enable pllref_clk\n");
788 ret = clk_prepare_enable(csi2->dphy_clk);
790 v4l2_err(&csi2->sd, "failed to enable dphy_clk\n");
794 platform_set_drvdata(pdev, &csi2->sd);
796 ret = csi2_async_register(csi2);
803 v4l2_async_nf_unregister(&csi2->notifier);
804 v4l2_async_nf_cleanup(&csi2->notifier);
805 clk_disable_unprepare(csi2->dphy_clk);
807 clk_disable_unprepare(csi2->pllref_clk);
809 mutex_destroy(&csi2->lock);
813 static void csi2_remove(struct platform_device *pdev)
815 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
816 struct csi2_dev *csi2 = sd_to_dev(sd);
818 v4l2_async_nf_unregister(&csi2->notifier);
819 v4l2_async_nf_cleanup(&csi2->notifier);
820 v4l2_async_unregister_subdev(sd);
821 clk_disable_unprepare(csi2->dphy_clk);
822 clk_disable_unprepare(csi2->pllref_clk);
823 mutex_destroy(&csi2->lock);
824 media_entity_cleanup(&sd->entity);
827 static const struct of_device_id csi2_dt_ids[] = {
828 { .compatible = "fsl,imx6-mipi-csi2", },
831 MODULE_DEVICE_TABLE(of, csi2_dt_ids);
833 static struct platform_driver csi2_driver = {
836 .of_match_table = csi2_dt_ids,
839 .remove_new = csi2_remove,
842 module_platform_driver(csi2_driver);
844 MODULE_DESCRIPTION("i.MX5/6 MIPI CSI-2 Receiver driver");
845 MODULE_AUTHOR("Steve Longerbeam <steve_longerbeam@mentor.com>");
846 MODULE_LICENSE("GPL");