2 * Copyright (C) 2012 Texas Instruments Inc
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Manjunath Hadli <manjunath.hadli@ti.com>
19 * Prabhakar Lad <prabhakar.lad@ti.com>
22 #ifndef _DAVINCI_VPFE_DM365_IPIPE_HW_H
23 #define _DAVINCI_VPFE_DM365_IPIPE_HW_H
25 #include "vpfe_mc_capture.h"
27 #define SET_LOW_ADDR 0x0000ffff
28 #define SET_HIGH_ADDR 0xffff0000
30 /* Below are the internal tables */
31 #define DPC_TB0_START_ADDR 0x8000
32 #define DPC_TB1_START_ADDR 0x8400
34 #define GAMMA_R_START_ADDR 0xa800
35 #define GAMMA_G_START_ADDR 0xb000
36 #define GAMMA_B_START_ADDR 0xb800
38 /* RAM table addresses for edge enhancement correction*/
39 #define YEE_TB_START_ADDR 0x8800
41 /* RAM table address for GBC LUT */
42 #define GBCE_TB_START_ADDR 0x9000
44 /* RAM table for 3D NF LUT */
45 #define D3L_TB0_START_ADDR 0x9800
46 #define D3L_TB1_START_ADDR 0x9c00
47 #define D3L_TB2_START_ADDR 0xa000
48 #define D3L_TB3_START_ADDR 0xa400
50 /* IPIPE Register Offsets from the base address */
51 #define IPIPE_SRC_EN 0x0000
52 #define IPIPE_SRC_MODE 0x0004
53 #define IPIPE_SRC_FMT 0x0008
54 #define IPIPE_SRC_COL 0x000c
55 #define IPIPE_SRC_VPS 0x0010
56 #define IPIPE_SRC_VSZ 0x0014
57 #define IPIPE_SRC_HPS 0x0018
58 #define IPIPE_SRC_HSZ 0x001c
60 #define IPIPE_SEL_SBU 0x0020
62 #define IPIPE_DMA_STA 0x0024
63 #define IPIPE_GCK_MMR 0x0028
64 #define IPIPE_GCK_PIX 0x002c
65 #define IPIPE_RESERVED0 0x0030
67 /* Defect Correction */
68 #define DPC_LUT_EN 0x0034
69 #define DPC_LUT_SEL 0x0038
70 #define DPC_LUT_ADR 0x003c
71 #define DPC_LUT_SIZ 0x0040
72 #define DPC_OTF_EN 0x0044
73 #define DPC_OTF_TYP 0x0048
74 #define DPC_OTF_2D_THR_R 0x004c
75 #define DPC_OTF_2D_THR_GR 0x0050
76 #define DPC_OTF_2D_THR_GB 0x0054
77 #define DPC_OTF_2D_THR_B 0x0058
78 #define DPC_OTF_2C_THR_R 0x005c
79 #define DPC_OTF_2C_THR_GR 0x0060
80 #define DPC_OTF_2C_THR_GB 0x0064
81 #define DPC_OTF_2C_THR_B 0x0068
82 #define DPC_OTF_3_SHF 0x006c
83 #define DPC_OTF_3D_THR 0x0070
84 #define DPC_OTF_3D_SLP 0x0074
85 #define DPC_OTF_3D_MIN 0x0078
86 #define DPC_OTF_3D_MAX 0x007c
87 #define DPC_OTF_3C_THR 0x0080
88 #define DPC_OTF_3C_SLP 0x0084
89 #define DPC_OTF_3C_MIN 0x0088
90 #define DPC_OTF_3C_MAX 0x008c
92 /* Lense Shading Correction */
101 #define LSC_GAIN_R 0xb0
102 #define LSC_GAIN_GR 0xb4
103 #define LSC_GAIN_GB 0xb8
104 #define LSC_GAIN_B 0xbc
105 #define LSC_OFT_R 0xc0
106 #define LSC_OFT_GR 0xc4
107 #define LSC_OFT_GB 0xc8
108 #define LSC_OFT_B 0xcc
112 /* Noise Filter 1. Ofsets from start address given */
119 #define D2F_EDG_MIN 0x68
120 #define D2F_EDG_MAX 0x6c
123 #define D2F_2ND 0x148
127 #define GIC_TYP 0x1bc
128 #define GIC_GAN 0x1c0
129 #define GIC_NFGAN 0x1c4
130 #define GIC_THR 0x1c8
131 #define GIC_SLP 0x1cc
134 #define WB2_OFT_R 0x1d0
135 #define WB2_OFT_GR 0x1d4
136 #define WB2_OFT_GB 0x1d8
137 #define WB2_OFT_B 0x1dc
138 #define WB2_WGN_R 0x1e0
139 #define WB2_WGN_GR 0x1e4
140 #define WB2_WGN_GB 0x1e8
141 #define WB2_WGN_B 0x1ec
143 /* CFA interpolation */
144 #define CFA_MODE 0x1f0
145 #define CFA_2DIR_HPF_THR 0x1f4
146 #define CFA_2DIR_HPF_SLP 0x1f8
147 #define CFA_2DIR_MIX_THR 0x1fc
148 #define CFA_2DIR_MIX_SLP 0x200
149 #define CFA_2DIR_DIR_THR 0x204
150 #define CFA_2DIR_DIR_SLP 0x208
151 #define CFA_2DIR_NDWT 0x20c
152 #define CFA_MONO_HUE_FRA 0x210
153 #define CFA_MONO_EDG_THR 0x214
154 #define CFA_MONO_THR_MIN 0x218
155 #define CFA_MONO_THR_SLP 0x21c
156 #define CFA_MONO_SLP_MIN 0x220
157 #define CFA_MONO_SLP_SLP 0x224
158 #define CFA_MONO_LPWT 0x228
160 /* RGB to RGB conversiona - 1st */
161 #define RGB1_MUL_BASE 0x22c
162 /* Offsets from base */
163 #define RGB_MUL_RR 0x0
164 #define RGB_MUL_GR 0x4
165 #define RGB_MUL_BR 0x8
166 #define RGB_MUL_RG 0xc
167 #define RGB_MUL_GG 0x10
168 #define RGB_MUL_BG 0x14
169 #define RGB_MUL_RB 0x18
170 #define RGB_MUL_GB 0x1c
171 #define RGB_MUL_BB 0x20
172 #define RGB_OFT_OR 0x24
173 #define RGB_OFT_OG 0x28
174 #define RGB_OFT_OB 0x2c
177 #define GMM_CFG 0x25c
179 /* RGB to RGB conversiona - 2nd */
180 #define RGB2_MUL_BASE 0x260
183 #define D3LUT_EN 0x290
185 /* RGB to YUV(YCbCr) conversion */
186 #define YUV_ADJ 0x294
187 #define YUV_MUL_RY 0x298
188 #define YUV_MUL_GY 0x29c
189 #define YUV_MUL_BY 0x2a0
190 #define YUV_MUL_RCB 0x2a4
191 #define YUV_MUL_GCB 0x2a8
192 #define YUV_MUL_BCB 0x2ac
193 #define YUV_MUL_RCR 0x2b0
194 #define YUV_MUL_GCR 0x2b4
195 #define YUV_MUL_BCR 0x2b8
196 #define YUV_OFT_Y 0x2bc
197 #define YUV_OFT_CB 0x2c0
198 #define YUV_OFT_CR 0x2c4
199 #define YUV_PHS 0x2c8
201 /* Global Brightness and Contrast */
202 #define GBCE_EN 0x2cc
203 #define GBCE_TYP 0x2d0
207 #define YEE_TYP 0x2d8
208 #define YEE_SHF 0x2dc
209 #define YEE_MUL_00 0x2e0
210 #define YEE_MUL_01 0x2e4
211 #define YEE_MUL_02 0x2e8
212 #define YEE_MUL_10 0x2ec
213 #define YEE_MUL_11 0x2f0
214 #define YEE_MUL_12 0x2f4
215 #define YEE_MUL_20 0x2f8
216 #define YEE_MUL_21 0x2fc
217 #define YEE_MUL_22 0x300
218 #define YEE_THR 0x304
219 #define YEE_E_GAN 0x308
220 #define YEE_E_THR1 0x30c
221 #define YEE_E_THR2 0x310
222 #define YEE_G_GAN 0x314
223 #define YEE_G_OFT 0x318
225 /* Chroma Artifact Reduction */
227 #define CAR_TYP 0x320
229 #define CAR_HPF_TYP 0x328
230 #define CAR_HPF_SHF 0x32c
231 #define CAR_HPF_THR 0x330
232 #define CAR_GN1_GAN 0x334
233 #define CAR_GN1_SHF 0x338
234 #define CAR_GN1_MIN 0x33c
235 #define CAR_GN2_GAN 0x340
236 #define CAR_GN2_SHF 0x344
237 #define CAR_GN2_MIN 0x348
239 /* Chroma Gain Suppression */
241 #define CGS_GN1_L_THR 0x350
242 #define CGS_GN1_L_GAN 0x354
243 #define CGS_GN1_L_SHF 0x358
244 #define CGS_GN1_L_MIN 0x35c
245 #define CGS_GN1_H_THR 0x360
246 #define CGS_GN1_H_GAN 0x364
247 #define CGS_GN1_H_SHF 0x368
248 #define CGS_GN1_H_MIN 0x36c
249 #define CGS_GN2_L_THR 0x370
250 #define CGS_GN2_L_GAN 0x374
251 #define CGS_GN2_L_SHF 0x378
252 #define CGS_GN2_L_MIN 0x37c
255 #define RSZ_SRC_EN 0x0
256 #define RSZ_SRC_MODE 0x4
257 #define RSZ_SRC_FMT0 0x8
258 #define RSZ_SRC_FMT1 0xc
259 #define RSZ_SRC_VPS 0x10
260 #define RSZ_SRC_VSZ 0x14
261 #define RSZ_SRC_HPS 0x18
262 #define RSZ_SRC_HSZ 0x1c
263 #define RSZ_DMA_RZA 0x20
264 #define RSZ_DMA_RZB 0x24
265 #define RSZ_DMA_STA 0x28
266 #define RSZ_GCK_MMR 0x2c
267 #define RSZ_RESERVED0 0x30
268 #define RSZ_GCK_SDR 0x34
269 #define RSZ_IRQ_RZA 0x38
270 #define RSZ_IRQ_RZB 0x3c
271 #define RSZ_YUV_Y_MIN 0x40
272 #define RSZ_YUV_Y_MAX 0x44
273 #define RSZ_YUV_C_MIN 0x48
274 #define RSZ_YUV_C_MAX 0x4c
275 #define RSZ_YUV_PHS 0x50
278 /* Resizer Rescale Parameters */
279 #define RSZ_EN_A 0x58
280 #define RSZ_EN_B 0xe8
282 * offset of the registers to be added with base register of
283 * either RSZ0 or RSZ1
287 #define RSZ_I_VPS 0xc
288 #define RSZ_I_HPS 0x10
289 #define RSZ_O_VSZ 0x14
290 #define RSZ_O_HSZ 0x18
291 #define RSZ_V_PHS_Y 0x1c
292 #define RSZ_V_PHS_C 0x20
293 #define RSZ_V_DIF 0x24
294 #define RSZ_V_TYP 0x28
295 #define RSZ_V_LPF 0x2c
296 #define RSZ_H_PHS 0x30
297 #define RSZ_H_PHS_ADJ 0x34
298 #define RSZ_H_DIF 0x38
299 #define RSZ_H_TYP 0x3c
300 #define RSZ_H_LPF 0x40
301 #define RSZ_DWN_EN 0x44
302 #define RSZ_DWN_AV 0x48
304 /* Resizer RGB Conversion Parameters */
305 #define RSZ_RGB_EN 0x4c
306 #define RSZ_RGB_TYP 0x50
307 #define RSZ_RGB_BLD 0x54
309 /* Resizer External Memory Parameters */
310 #define RSZ_SDR_Y_BAD_H 0x58
311 #define RSZ_SDR_Y_BAD_L 0x5c
312 #define RSZ_SDR_Y_SAD_H 0x60
313 #define RSZ_SDR_Y_SAD_L 0x64
314 #define RSZ_SDR_Y_OFT 0x68
315 #define RSZ_SDR_Y_PTR_S 0x6c
316 #define RSZ_SDR_Y_PTR_E 0x70
317 #define RSZ_SDR_C_BAD_H 0x74
318 #define RSZ_SDR_C_BAD_L 0x78
319 #define RSZ_SDR_C_SAD_H 0x7c
320 #define RSZ_SDR_C_SAD_L 0x80
321 #define RSZ_SDR_C_OFT 0x84
322 #define RSZ_SDR_C_PTR_S 0x88
323 #define RSZ_SDR_C_PTR_E 0x8c
325 /* Macro for resizer */
326 #define RSZ_YUV_Y_MIN 0x40
327 #define RSZ_YUV_Y_MAX 0x44
328 #define RSZ_YUV_C_MIN 0x48
329 #define RSZ_YUV_C_MAX 0x4c
331 #define IPIPE_GCK_MMR_DEFAULT 1
332 #define IPIPE_GCK_PIX_DEFAULT 0xe
333 #define RSZ_GCK_MMR_DEFAULT 1
334 #define RSZ_GCK_SDR_DEFAULT 1
337 #define LUTDPC_TBL_256_EN 0
338 #define LUTDPC_INF_TBL_EN 1
339 #define LUT_DPC_START_ADDR 0
340 #define LUT_DPC_H_POS_MASK 0x1fff
341 #define LUT_DPC_V_POS_MASK 0x1fff
342 #define LUT_DPC_V_POS_SHIFT 13
343 #define LUT_DPC_CORR_METH_SHIFT 26
344 #define LUT_DPC_MAX_SIZE 256
345 #define LUT_DPC_SIZE_MASK 0x3ff
348 #define OTFDPC_DPC2_THR_MASK 0xfff
349 #define OTF_DET_METHOD_SHIFT 1
350 #define OTF_DPC3_0_SHF_MASK 3
351 #define OTF_DPC3_0_THR_SHIFT 6
352 #define OTF_DPC3_0_THR_MASK 0x3f
353 #define OTF_DPC3_0_SLP_MASK 0x3f
354 #define OTF_DPC3_0_DET_MASK 0xfff
355 #define OTF_DPC3_0_CORR_MASK 0xfff
358 #define D2F_SPR_VAL_MASK 0x1f
359 #define D2F_SPR_VAL_SHIFT 0
360 #define D2F_SHFT_VAL_MASK 3
361 #define D2F_SHFT_VAL_SHIFT 5
362 #define D2F_SAMPLE_METH_SHIFT 7
363 #define D2F_APPLY_LSC_GAIN_SHIFT 8
364 #define D2F_USE_SPR_REG_VAL 0
365 #define D2F_STR_VAL_MASK 0x1f
366 #define D2F_THR_VAL_MASK 0x3ff
367 #define D2F_EDGE_DET_THR_MASK 0x7ff
369 /* Green Imbalance Correction */
370 #define GIC_TYP_SHIFT 0
371 #define GIC_THR_SEL_SHIFT 1
372 #define GIC_APPLY_LSC_GAIN_SHIFT 2
373 #define GIC_GAIN_MASK 0xff
374 #define GIC_THR_MASK 0xfff
375 #define GIC_SLOPE_MASK 0xfff
376 #define GIC_NFGAN_INT_MASK 7
377 #define GIC_NFGAN_DECI_MASK 0x1f
380 #define WB_OFFSET_MASK 0xfff
381 #define WB_GAIN_INT_MASK 0xf
382 #define WB_GAIN_DECI_MASK 0x1ff
385 #define CFA_HPF_THR_2DIR_MASK 0x1fff
386 #define CFA_HPF_SLOPE_2DIR_MASK 0x3ff
387 #define CFA_HPF_MIX_THR_2DIR_MASK 0x1fff
388 #define CFA_HPF_MIX_SLP_2DIR_MASK 0x3ff
389 #define CFA_DIR_THR_2DIR_MASK 0x3ff
390 #define CFA_DIR_SLP_2DIR_MASK 0x7f
391 #define CFA_ND_WT_2DIR_MASK 0x3f
392 #define CFA_DAA_HUE_FRA_MASK 0x3f
393 #define CFA_DAA_EDG_THR_MASK 0xff
394 #define CFA_DAA_THR_MIN_MASK 0x3ff
395 #define CFA_DAA_THR_SLP_MASK 0x3ff
396 #define CFA_DAA_SLP_MIN_MASK 0x3ff
397 #define CFA_DAA_SLP_SLP_MASK 0x3ff
398 #define CFA_DAA_LP_WT_MASK 0x3f
401 #define RGB2RGB_1_OFST_MASK 0x1fff
402 #define RGB2RGB_1_GAIN_INT_MASK 0xf
403 #define RGB2RGB_GAIN_DECI_MASK 0xff
404 #define RGB2RGB_2_OFST_MASK 0x7ff
405 #define RGB2RGB_2_GAIN_INT_MASK 0x7
408 #define GAMMA_BYPR_SHIFT 0
409 #define GAMMA_BYPG_SHIFT 1
410 #define GAMMA_BYPB_SHIFT 2
411 #define GAMMA_TBL_SEL_SHIFT 4
412 #define GAMMA_TBL_SIZE_SHIFT 5
413 #define GAMMA_MASK 0x3ff
414 #define GAMMA_SHIFT 10
417 #define D3_LUT_ENTRY_MASK 0x3ff
418 #define D3_LUT_ENTRY_R_SHIFT 20
419 #define D3_LUT_ENTRY_G_SHIFT 10
420 #define D3_LUT_ENTRY_B_SHIFT 0
423 #define LUM_ADJ_CONTR_SHIFT 0
424 #define LUM_ADJ_BRIGHT_SHIFT 8
427 #define RGB2YCBCR_OFST_MASK 0x7ff
428 #define RGB2YCBCR_COEF_INT_MASK 0xf
429 #define RGB2YCBCR_COEF_DECI_MASK 0xff
432 #define GBCE_Y_VAL_MASK 0xff
433 #define GBCE_GAIN_VAL_MASK 0x3ff
434 #define GBCE_ENTRY_SHIFT 10
436 /* Edge Enhancements */
437 #define YEE_HALO_RED_EN_SHIFT 1
438 #define YEE_HPF_SHIFT_MASK 0xf
439 #define YEE_COEF_MASK 0x3ff
440 #define YEE_THR_MASK 0x3f
441 #define YEE_ES_GAIN_MASK 0xfff
442 #define YEE_ES_THR1_MASK 0xfff
443 #define YEE_ENTRY_SHIFT 9
444 #define YEE_ENTRY_MASK 0x1ff
447 #define CAR_MF_THR 0xff
448 #define CAR_SW1_SHIFT 8
449 #define CAR_GAIN1_SHFT_MASK 7
450 #define CAR_GAIN_MIN_MASK 0x1ff
451 #define CAR_GAIN2_SHFT_MASK 0xf
452 #define CAR_HPF_SHIFT_MASK 3
455 #define CAR_SHIFT_MASK 3
458 #define RSZ_BYPASS_SHIFT 1
459 #define RSZ_SRC_IMG_FMT_SHIFT 1
460 #define RSZ_SRC_Y_C_SEL_SHIFT 2
461 #define IPIPE_RSZ_VPS_MASK 0xffff
462 #define IPIPE_RSZ_HPS_MASK 0xffff
463 #define IPIPE_RSZ_VSZ_MASK 0x1fff
464 #define IPIPE_RSZ_HSZ_MASK 0x1fff
465 #define RSZ_HPS_MASK 0x1fff
466 #define RSZ_VPS_MASK 0x1fff
467 #define RSZ_O_HSZ_MASK 0x1fff
468 #define RSZ_O_VSZ_MASK 0x1fff
469 #define RSZ_V_PHS_MASK 0x3fff
470 #define RSZ_V_DIF_MASK 0x3fff
472 #define RSZA_H_FLIP_SHIFT 0
473 #define RSZA_V_FLIP_SHIFT 1
474 #define RSZB_H_FLIP_SHIFT 2
475 #define RSZB_V_FLIP_SHIFT 3
478 #define RSZ_CEN_SHIFT 1
479 #define RSZ_YEN_SHIFT 0
480 #define RSZ_TYP_Y_SHIFT 0
481 #define RSZ_TYP_C_SHIFT 1
482 #define RSZ_LPF_INT_MASK 0x3f
483 #define RSZ_LPF_INT_C_SHIFT 6
484 #define RSZ_H_PHS_MASK 0x3fff
485 #define RSZ_H_DIF_MASK 0x3fff
486 #define RSZ_DIFF_DOWN_THR 256
487 #define RSZ_DWN_SCALE_AV_SZ_V_SHIFT 3
488 #define RSZ_DWN_SCALE_AV_SZ_MASK 7
489 #define RSZ_RGB_MSK1_SHIFT 2
490 #define RSZ_RGB_MSK0_SHIFT 1
491 #define RSZ_RGB_TYP_SHIFT 0
492 #define RSZ_RGB_ALPHA_MASK 0xff
494 static inline u32 regr_ip(void __iomem *addr, u32 offset)
496 return readl(addr + offset);
499 static inline void regw_ip(void __iomem *addr, u32 val, u32 offset)
501 writel(val, addr + offset);
504 static inline u32 w_ip_table(void __iomem *addr, u32 val, u32 offset)
506 writel(val, addr + offset);
511 static inline u32 regr_rsz(void __iomem *addr, u32 offset)
513 return readl(addr + offset);
516 static inline u32 regw_rsz(void __iomem *addr, u32 val, u32 offset)
518 writel(val, addr + offset);
523 int config_ipipe_hw(struct vpfe_ipipe_device *ipipe);
524 int resizer_set_outaddr(void __iomem *rsz_base, struct resizer_params *params,
525 int resize_no, unsigned int address);
526 int rsz_enable(void __iomem *rsz_base, int rsz_id, int enable);
527 void rsz_src_enable(void __iomem *rsz_base, int enable);
528 void rsz_set_in_pix_format(unsigned char y_c);
529 int config_rsz_hw(struct vpfe_resizer_device *resizer,
530 struct resizer_params *config);
531 void ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id,
532 struct vpfe_ipipe_nf *noise_filter);
533 void ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
534 struct vpfe_ipipe_rgb2rgb *rgb);
535 void ipipe_set_yuv422_conv_regs(void __iomem *base_addr,
536 struct vpfe_ipipe_yuv422_conv *conv);
537 void ipipe_set_lum_adj_regs(void __iomem *base_addr,
538 struct ipipe_lum_adj *lum_adj);
539 void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr,
540 struct vpfe_ipipe_rgb2yuv *yuv);
541 void ipipe_set_lutdpc_regs(void __iomem *base_addr,
542 void __iomem *isp5_base_addr, struct vpfe_ipipe_lutdpc *lutdpc);
543 void ipipe_set_otfdpc_regs(void __iomem *base_addr,
544 struct vpfe_ipipe_otfdpc *otfdpc);
545 void ipipe_set_3d_lut_regs(void __iomem *base_addr,
546 void __iomem *isp5_base_addr, struct vpfe_ipipe_3d_lut *lut_3d);
547 void ipipe_set_gamma_regs(void __iomem *base_addr,
548 void __iomem *isp5_base_addr, struct vpfe_ipipe_gamma *gamma);
549 void ipipe_set_ee_regs(void __iomem *base_addr,
550 void __iomem *isp5_base_addr, struct vpfe_ipipe_yee *ee);
551 void ipipe_set_gbce_regs(void __iomem *base_addr,
552 void __iomem *isp5_base_addr, struct vpfe_ipipe_gbce *gbce);
553 void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic);
554 void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa);
555 void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car);
556 void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs);
557 void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb);
559 #endif /* _DAVINCI_VPFE_DM365_IPIPE_HW_H */