2 * cxd2099.c: Driver for the CXD2099AR Common Interface Controller
4 * Copyright (C) 2010-2011 Digital Devices GmbH
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 only, as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
25 #include <linux/slab.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/i2c.h>
29 #include <linux/wait.h>
30 #include <linux/delay.h>
31 #include <linux/mutex.h>
36 #define MAX_BUFFER_SIZE 248
39 struct dvb_ca_en50221 en;
41 struct i2c_adapter *i2c;
42 struct cxd2099_cfg cfg;
60 static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
63 u8 m[2] = {reg, data};
64 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
66 if (i2c_transfer(adapter, &msg, 1) != 1) {
67 dev_err(&adapter->dev,
68 "Failed to write to I2C register %02x@%02x!\n",
75 static int i2c_write(struct i2c_adapter *adapter, u8 adr,
78 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
80 if (i2c_transfer(adapter, &msg, 1) != 1) {
81 dev_err(&adapter->dev, "Failed to write to I2C!\n");
87 static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
90 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
91 .buf = ®, .len = 1},
92 {.addr = adr, .flags = I2C_M_RD,
93 .buf = val, .len = 1} };
95 if (i2c_transfer(adapter, msgs, 2) != 2) {
96 dev_err(&adapter->dev, "error in i2c_read_reg\n");
102 static int i2c_read(struct i2c_adapter *adapter, u8 adr,
103 u8 reg, u8 *data, u8 n)
105 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
106 .buf = ®, .len = 1},
107 {.addr = adr, .flags = I2C_M_RD,
108 .buf = data, .len = n} };
110 if (i2c_transfer(adapter, msgs, 2) != 2) {
111 dev_err(&adapter->dev, "error in i2c_read\n");
117 static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n)
121 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
123 ci->lastaddress = adr;
124 status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n);
129 static int read_reg(struct cxd *ci, u8 reg, u8 *val)
131 return read_block(ci, reg, val, 1);
135 static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
138 u8 addr[3] = {2, address & 0xff, address >> 8};
140 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
142 status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
146 static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
149 u8 addr[3] = {2, address & 0xff, address >> 8};
151 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
155 memcpy(buf+1, data, n);
156 status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1);
161 static int read_io(struct cxd *ci, u16 address, u8 *val)
164 u8 addr[3] = {2, address & 0xff, address >> 8};
166 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
168 status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
172 static int write_io(struct cxd *ci, u16 address, u8 val)
175 u8 addr[3] = {2, address & 0xff, address >> 8};
176 u8 buf[2] = {3, val};
178 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
180 status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
185 static int read_io_data(struct cxd *ci, u8 *data, u8 n)
188 u8 addr[3] = { 2, 0, 0 };
190 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
192 status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
196 static int write_io_data(struct cxd *ci, u8 *data, u8 n)
199 u8 addr[3] = {2, 0, 0};
201 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
205 memcpy(buf+1, data, n);
206 status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
212 static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
216 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
217 if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
218 status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
219 ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
221 ci->lastaddress = reg;
222 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
225 ci->regs[reg] &= 0x7f;
229 static int write_reg(struct cxd *ci, u8 reg, u8 val)
231 return write_regm(ci, reg, val, 0xff);
235 static int write_block(struct cxd *ci, u8 adr, u8 *data, int n)
240 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
242 ci->lastaddress = adr;
243 memcpy(buf + 1, data, n);
244 status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
250 static void set_mode(struct cxd *ci, int mode)
252 if (mode == ci->mode)
256 case 0x00: /* IO mem */
257 write_regm(ci, 0x06, 0x00, 0x07);
259 case 0x01: /* ATT mem */
260 write_regm(ci, 0x06, 0x02, 0x07);
268 static void cam_mode(struct cxd *ci, int mode)
270 if (mode == ci->cammode)
275 write_regm(ci, 0x20, 0x80, 0x80);
279 if (!ci->en.read_data)
281 dev_info(&ci->i2c->dev, "enable cam buffer mode\n");
282 /* write_reg(ci, 0x0d, 0x00); */
283 /* write_reg(ci, 0x0e, 0x01); */
284 write_regm(ci, 0x08, 0x40, 0x40);
285 /* read_reg(ci, 0x12, &dummy); */
286 write_regm(ci, 0x08, 0x80, 0x80);
297 static int init(struct cxd *ci)
301 mutex_lock(&ci->lock);
304 status = write_reg(ci, 0x00, 0x00);
307 status = write_reg(ci, 0x01, 0x00);
310 status = write_reg(ci, 0x02, 0x10);
313 status = write_reg(ci, 0x03, 0x00);
316 status = write_reg(ci, 0x05, 0xFF);
319 status = write_reg(ci, 0x06, 0x1F);
322 status = write_reg(ci, 0x07, 0x1F);
325 status = write_reg(ci, 0x08, 0x28);
328 status = write_reg(ci, 0x14, 0x20);
333 /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
334 status = write_reg(ci, 0x09, 0x4D);
338 /* TOSTRT = 8, Mode B (gated clock), falling Edge,
339 * Serial, POL=HIGH, MSB */
340 status = write_reg(ci, 0x0A, 0xA7);
344 status = write_reg(ci, 0x0B, 0x33);
347 status = write_reg(ci, 0x0C, 0x33);
351 status = write_regm(ci, 0x14, 0x00, 0x0F);
354 status = write_reg(ci, 0x15, ci->clk_reg_b);
357 status = write_regm(ci, 0x16, 0x00, 0x0F);
360 status = write_reg(ci, 0x17, ci->clk_reg_f);
364 if (ci->cfg.clock_mode) {
365 if (ci->cfg.polarity) {
366 status = write_reg(ci, 0x09, 0x6f);
370 status = write_reg(ci, 0x09, 0x6d);
374 status = write_reg(ci, 0x20, 0x68);
377 status = write_reg(ci, 0x21, 0x00);
380 status = write_reg(ci, 0x22, 0x02);
384 if (ci->cfg.polarity) {
385 status = write_reg(ci, 0x09, 0x4f);
389 status = write_reg(ci, 0x09, 0x4d);
394 status = write_reg(ci, 0x20, 0x28);
397 status = write_reg(ci, 0x21, 0x00);
400 status = write_reg(ci, 0x22, 0x07);
405 status = write_regm(ci, 0x20, 0x80, 0x80);
408 status = write_regm(ci, 0x03, 0x02, 0x02);
411 status = write_reg(ci, 0x01, 0x04);
414 status = write_reg(ci, 0x00, 0x31);
418 /* Put TS in bypass */
419 status = write_regm(ci, 0x09, 0x08, 0x08);
425 mutex_unlock(&ci->lock);
430 static int read_attribute_mem(struct dvb_ca_en50221 *ca,
431 int slot, int address)
433 struct cxd *ci = ca->data;
436 if (address <= 0 || address > 1024)
438 return ci->amem[address];
441 mutex_lock(&ci->lock);
442 write_regm(ci, 0x06, 0x00, 0x05);
443 read_pccard(ci, 0, &ci->amem[0], 128);
444 read_pccard(ci, 128, &ci->amem[0], 128);
445 read_pccard(ci, 256, &ci->amem[0], 128);
446 read_pccard(ci, 384, &ci->amem[0], 128);
447 write_regm(ci, 0x06, 0x05, 0x05);
448 mutex_unlock(&ci->lock);
449 return ci->amem[address];
453 mutex_lock(&ci->lock);
455 read_pccard(ci, address, &val, 1);
456 mutex_unlock(&ci->lock);
457 /* printk(KERN_INFO "%02x:%02x\n", address,val); */
462 static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
463 int address, u8 value)
465 struct cxd *ci = ca->data;
467 mutex_lock(&ci->lock);
469 write_pccard(ci, address, &value, 1);
470 mutex_unlock(&ci->lock);
474 static int read_cam_control(struct dvb_ca_en50221 *ca,
475 int slot, u8 address)
477 struct cxd *ci = ca->data;
480 mutex_lock(&ci->lock);
482 read_io(ci, address, &val);
483 mutex_unlock(&ci->lock);
487 static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
488 u8 address, u8 value)
490 struct cxd *ci = ca->data;
492 mutex_lock(&ci->lock);
494 write_io(ci, address, value);
495 mutex_unlock(&ci->lock);
499 static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
501 struct cxd *ci = ca->data;
503 mutex_lock(&ci->lock);
505 write_reg(ci, 0x00, 0x21);
506 write_reg(ci, 0x06, 0x1F);
507 write_reg(ci, 0x00, 0x31);
510 write_reg(ci, 0x06, 0x1F);
511 write_reg(ci, 0x06, 0x2F);
514 write_reg(ci, 0x00, 0x21);
515 write_reg(ci, 0x06, 0x1F);
516 write_reg(ci, 0x00, 0x31);
517 write_regm(ci, 0x20, 0x80, 0x80);
518 write_reg(ci, 0x03, 0x02);
528 for (i = 0; i < 100; i++) {
529 usleep_range(10000, 11000);
531 read_reg(ci, 0x06, &val);
532 dev_info(&ci->i2c->dev, "%d:%02x\n", i, val);
541 mutex_unlock(&ci->lock);
546 static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
548 struct cxd *ci = ca->data;
550 dev_info(&ci->i2c->dev, "slot_shutdown\n");
551 mutex_lock(&ci->lock);
552 write_regm(ci, 0x09, 0x08, 0x08);
553 write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
554 write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
556 mutex_unlock(&ci->lock);
560 static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
562 struct cxd *ci = ca->data;
564 mutex_lock(&ci->lock);
565 write_regm(ci, 0x09, 0x00, 0x08);
570 mutex_unlock(&ci->lock);
575 static int campoll(struct cxd *ci)
579 read_reg(ci, 0x04, &istat);
582 write_reg(ci, 0x05, istat);
586 dev_info(&ci->i2c->dev, "DR\n");
589 dev_info(&ci->i2c->dev, "WC\n");
594 read_reg(ci, 0x01, &slotstat);
596 if (!ci->slot_stat) {
597 ci->slot_stat = DVB_CA_EN50221_POLL_CAM_PRESENT;
598 write_regm(ci, 0x03, 0x08, 0x08);
604 write_regm(ci, 0x03, 0x00, 0x08);
605 dev_info(&ci->i2c->dev, "NO CAM\n");
610 ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
612 ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
619 static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
621 struct cxd *ci = ca->data;
624 mutex_lock(&ci->lock);
626 read_reg(ci, 0x01, &slotstat);
627 mutex_unlock(&ci->lock);
629 return ci->slot_stat;
633 static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
635 struct cxd *ci = ca->data;
639 mutex_lock(&ci->lock);
641 mutex_unlock(&ci->lock);
643 dev_info(&ci->i2c->dev, "read_data\n");
647 mutex_lock(&ci->lock);
648 read_reg(ci, 0x0f, &msb);
649 read_reg(ci, 0x10, &lsb);
651 read_block(ci, 0x12, ebuf, len);
653 mutex_unlock(&ci->lock);
658 static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
660 struct cxd *ci = ca->data;
662 mutex_lock(&ci->lock);
663 dev_info(&ci->i2c->dev, "write_data %d\n", ecount);
664 write_reg(ci, 0x0d, ecount>>8);
665 write_reg(ci, 0x0e, ecount&0xff);
666 write_block(ci, 0x11, ebuf, ecount);
667 mutex_unlock(&ci->lock);
672 static struct dvb_ca_en50221 en_templ = {
673 .read_attribute_mem = read_attribute_mem,
674 .write_attribute_mem = write_attribute_mem,
675 .read_cam_control = read_cam_control,
676 .write_cam_control = write_cam_control,
677 .slot_reset = slot_reset,
678 .slot_shutdown = slot_shutdown,
679 .slot_ts_enable = slot_ts_enable,
680 .poll_slot_status = poll_slot_status,
682 .read_data = read_data,
683 .write_data = write_data,
688 struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
690 struct i2c_adapter *i2c)
695 if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
696 dev_info(&i2c->dev, "No CXD2099 detected at %02x\n", cfg->adr);
700 ci = kzalloc(sizeof(struct cxd), GFP_KERNEL);
704 mutex_init(&ci->lock);
707 ci->lastaddress = 0xff;
708 ci->clk_reg_b = 0x4a;
709 ci->clk_reg_f = 0x1b;
714 dev_info(&i2c->dev, "Attached CXD2099AR at %02x\n", ci->cfg.adr);
717 EXPORT_SYMBOL(cxd2099_attach);
719 MODULE_DESCRIPTION("cxd2099");
720 MODULE_AUTHOR("Ralph Metzler");
721 MODULE_LICENSE("GPL");