1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #ifndef __SYSTEM_LOCAL_H_INCLUDED__
17 #define __SYSTEM_LOCAL_H_INCLUDED__
19 #ifdef HRT_ISP_CSS_CUSTOM_HOST
20 #ifndef HRT_USE_VIR_ADDRS
21 #define HRT_USE_VIR_ADDRS
25 #include "system_global.h"
27 /* This interface is deprecated */
28 #include "hive_types.h"
31 * Cell specific address maps
34 #define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
37 extern const hrt_address ISP_CTRL_BASE[N_ISP_ID];
38 extern const hrt_address ISP_DMEM_BASE[N_ISP_ID];
39 extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID];
42 extern const hrt_address SP_CTRL_BASE[N_SP_ID];
43 extern const hrt_address SP_DMEM_BASE[N_SP_ID];
47 extern const hrt_address MMU_BASE[N_MMU_ID];
50 extern const hrt_address DMA_BASE[N_DMA_ID];
51 extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID];
54 extern const hrt_address IRQ_BASE[N_IRQ_ID];
57 extern const hrt_address GDC_BASE[N_GDC_ID];
59 /* FIFO_MONITOR (not a subset of GP_DEVICE) */
60 extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID];
62 /* GP_DEVICE (single base for all separate GP_REG instances) */
63 extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID];
65 /*GP TIMER , all timer registers are inter-twined,
66 * so, having multiple base addresses for
67 * different timers does not help*/
68 extern const hrt_address GP_TIMER_BASE;
71 extern const hrt_address GPIO_BASE[N_GPIO_ID];
74 extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID];
77 extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID];
80 extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID];
82 /* RX, the MIPI lane control regs start at offset 0 */
83 extern const hrt_address RX_BASE[N_RX_ID];
85 /* IBUF_CTRL, part of the Input System 2401 */
86 extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID];
88 /* ISYS IRQ Controllers, part of the Input System 2401 */
89 extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID];
91 /* CSI FE, part of the Input System 2401 */
92 extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID];
94 /* CSI BE, part of the Input System 2401 */
95 extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID];
97 /* PIXEL Generator, part of the Input System 2401 */
98 extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID];
100 /* Stream2MMIO, part of the Input System 2401 */
101 extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID];
103 #endif /* __SYSTEM_LOCAL_H_INCLUDED__ */