1 /* SPDX-License-Identifier: GPL-2.0 */
2 // SPDX-License-Identifier: GPL-2.0-or-later
4 * (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
7 #ifndef __SYSTEM_GLOBAL_H_INCLUDED__
8 #define __SYSTEM_GLOBAL_H_INCLUDED__
11 * Create a list of HAS and IS properties that defines the system
12 * Those are common for both ISP2400 and ISP2401
14 * The configuration assumes the following
15 * - The system is hetereogeneous; Multiple cells and devices classes
16 * - The cell and device instances are homogeneous, each device type
17 * belongs to the same class
18 * - Device instances supporting a subset of the class capabilities are
21 * We could manage different device classes through the enumerated
22 * lists (C) or the use of classes (C++), but that is presently not
25 * N.B. the 3 input formatters are of 2 different classess
28 #define DMA_DDR_TO_VAMEM_WORKAROUND
29 #define DMA_DDR_TO_HMEM_WORKAROUND
32 * The longest allowed (uninteruptible) bus transfer, does not
33 * take stalling into account
35 #define HIVE_ISP_MAX_BURST_LENGTH 1024
38 * Maximum allowed burst length in words for the ISP DMA
39 * This value is set to 2 to prevent the ISP DMA from blocking
40 * the bus for too long; as the input system can only buffer
41 * 2 lines on Moorefield and Cherrytrail, the input system buffers
42 * may overflow if blocked for too long (BZ 2726).
44 #define ISP2400_DMA_MAX_BURST_LENGTH 128
45 #define ISP2401_DMA_MAX_BURST_LENGTH 2
47 #include <hive_isp_css_defs.h>
48 #include <type_support.h>
50 /* This interface is deprecated */
51 #include "hive_types.h"
54 * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
56 #define HRT_VADDRESS_WIDTH 32
58 #define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
59 #define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
61 /* The main bus connecting all devices */
62 #define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
63 #define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
65 typedef u32 hrt_bus_align_t;
68 * Enumerate the devices, device access through the API is by ID,
69 * through the DLI by address. The enumerator terminators are used
70 * to size the wiring arrays and as an exception value.
104 /* this extra define is needed because we want to use it also
105 in the preprocessor, and that doesn't work with enums.
107 #define N_GDC_ID_CPP 2
127 IRQ0_ID = 0, /* GP IRQ block */
128 IRQ1_ID, /* Input formatter */
129 IRQ2_ID, /* input system */
130 IRQ3_ID, /* input selector */
135 FIFO_MONITOR0_ID = 0,
167 INPUT_FORMATTER0_ID = 0,
172 } input_formatter_ID_t;
174 /* The IF RST is outside the IF */
175 #define INPUT_FORMATTER0_SRST_OFFSET 0x0824
176 #define INPUT_FORMATTER1_SRST_OFFSET 0x0624
177 #define INPUT_FORMATTER2_SRST_OFFSET 0x0424
178 #define INPUT_FORMATTER3_SRST_OFFSET 0x0224
180 #define INPUT_FORMATTER0_SRST_MASK 0x0001
181 #define INPUT_FORMATTER1_SRST_MASK 0x0002
182 #define INPUT_FORMATTER2_SRST_MASK 0x0004
183 #define INPUT_FORMATTER3_SRST_MASK 0x0008
186 INPUT_SYSTEM0_ID = 0,
202 #define N_RX_CHANNEL_ID 4
204 /* Generic port enumeration with an internal port type ID */
217 CAPTURE_UNIT0_ID = 0,
220 ACQUISITION_UNIT0_ID,
229 #define N_CAPTURE_UNIT_ID 3
230 #define N_ACQUISITION_UNIT_ID 1
231 #define N_CTRL_UNIT_ID 1
234 enum ia_css_isp_memories {
235 IA_CSS_ISP_PMEM0 = 0,
247 #define IA_CSS_NUM_MEMORIES 9
248 /* For driver compatibility */
249 #define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
250 #define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
253 * ISP2401 specific enums
257 ISYS_IRQ0_ID = 0, /* port a */
258 ISYS_IRQ1_ID, /* port b */
259 ISYS_IRQ2_ID, /* port c */
265 * Input-buffer Controller.
268 IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
269 IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
270 IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
273 /* end of Input-buffer Controller */
279 STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
280 STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
281 STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
287 * Stream2MMIO 0 has 8 SIDs that are indexed by
288 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
290 * Stream2MMIO 1 has 4 SIDs that are indexed by
291 * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
293 * Stream2MMIO 2 has 4 SIDs that are indexed by
294 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
296 STREAM2MMIO_SID0_ID = 0,
305 } stream2mmio_sid_ID_t;
306 /* end of Stream2MMIO */
309 * Input System 2401: CSI-MIPI recevier.
312 CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
313 CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
314 CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
316 } csi_rx_backend_ID_t;
319 CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
320 CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
321 CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
322 #define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
323 } csi_rx_frontend_ID_t;
326 CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
327 CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
328 CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
329 CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
331 } csi_rx_fe_dlane_ID_t;
332 /* end of CSI-MIPI receiver */
335 ISYS2401_DMA0_ID = 0,
340 * Pixel-generator. ("system_global.h")
348 /* end of pixel-generator. ("system_global.h") */
351 INPUT_SYSTEM_CSI_PORT0_ID = 0,
352 INPUT_SYSTEM_CSI_PORT1_ID,
353 INPUT_SYSTEM_CSI_PORT2_ID,
355 INPUT_SYSTEM_PIXELGEN_PORT0_ID,
356 INPUT_SYSTEM_PIXELGEN_PORT1_ID,
357 INPUT_SYSTEM_PIXELGEN_PORT2_ID,
359 N_INPUT_SYSTEM_INPUT_PORT_ID
360 } input_system_input_port_ID_t;
362 #define N_INPUT_SYSTEM_CSI_PORT 3
365 ISYS2401_DMA_CHANNEL_0 = 0,
366 ISYS2401_DMA_CHANNEL_1,
367 ISYS2401_DMA_CHANNEL_2,
368 ISYS2401_DMA_CHANNEL_3,
369 ISYS2401_DMA_CHANNEL_4,
370 ISYS2401_DMA_CHANNEL_5,
371 ISYS2401_DMA_CHANNEL_6,
372 ISYS2401_DMA_CHANNEL_7,
373 ISYS2401_DMA_CHANNEL_8,
374 ISYS2401_DMA_CHANNEL_9,
375 ISYS2401_DMA_CHANNEL_10,
376 ISYS2401_DMA_CHANNEL_11,
377 N_ISYS2401_DMA_CHANNEL
378 } isys2401_dma_channel;
380 #endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */