drivers/staging/media/atomisp/pci/isp2400_input_system_public.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Support for Intel Camera Imaging ISP subsystem.
   4  * Copyright (c) 2015, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__
  17 #define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__
  18
  19 #include <type_support.h>
  20 #ifdef ISP2401
  21 #include "isys_public.h"
  22 #else
  23
  24 typedef struct input_system_state_s             input_system_state_t;
  25 typedef struct receiver_state_s                 receiver_state_t;
  26
  27 /*! Read the state of INPUT_SYSTEM[ID]
  28
  29  \param ID[in]                          INPUT_SYSTEM identifier
  30  \param state[out]                      input system state structure
  31
  32  \return none, state = INPUT_SYSTEM[ID].state
  33  */
  34 void input_system_get_state(
  35     const input_system_ID_t             ID,
  36     input_system_state_t                *state);
  37
  38 /*! Read the state of RECEIVER[ID]
  39
  40  \param ID[in]                          RECEIVER identifier
  41  \param state[out]                      receiver state structure
  42
  43  \return none, state = RECEIVER[ID].state
  44  */
  45 void receiver_get_state(
  46     const rx_ID_t                               ID,
  47     receiver_state_t                    *state);
  48
  49 /*! Flag whether a MIPI format is YUV420
  50
  51  \param mipi_format[in]         MIPI format
  52
  53  \return mipi_format == YUV420
  54  */
  55 bool is_mipi_format_yuv420(
  56     const mipi_format_t                 mipi_format);
  57
  58 /*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID]
  59
  60  \param ID[in]                          RECEIVER identifier
  61  \param cfg_ID[in]                      Configuration identifier
  62  \param comp[in]                        Compression method
  63  \param pred[in]                        Predictor method
  64
  65  \NOTE: the storage of compression configuration is
  66         implementation specific. The config can be
  67         carried either on MIPI ports or on MIPI channels
  68
  69  \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred}
  70  */
  71 void receiver_set_compression(
  72     const rx_ID_t                               ID,
  73     const unsigned int                  cfg_ID,
  74     const mipi_compressor_t             comp,
  75     const mipi_predictor_t              pred);
  76
  77 /*! Enable PORT[port_ID] of RECEIVER[ID]
  78
  79  \param ID[in]                          RECEIVER identifier
  80  \param port_ID[in]                     mipi PORT identifier
  81  \param cnd[in]                         irq predicate
  82
  83  \return None, enable(RECEIVER[ID].PORT[port_ID])
  84  */
  85 void receiver_port_enable(
  86     const rx_ID_t                               ID,
  87     const enum mipi_port_id             port_ID,
  88     const bool                                  cnd);
  89
  90 /*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled
  91
  92  \param ID[in]                          RECEIVER identifier
  93  \param port_ID[in]                     mipi PORT identifier
  94
  95  \return enable(RECEIVER[ID].PORT[port_ID]) == true
  96  */
  97 bool is_receiver_port_enabled(
  98     const rx_ID_t                               ID,
  99     const enum mipi_port_id             port_ID);
 100
 101 /*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID]
 102
 103  \param ID[in]                          RECEIVER identifier
 104  \param port_ID[in]                     mipi PORT identifier
 105  \param irq_info[in]            irq channels
 106
 107  \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info)
 108  */
 109 void receiver_irq_enable(
 110     const rx_ID_t                               ID,
 111     const enum mipi_port_id             port_ID,
 112     const rx_irq_info_t                 irq_info);
 113
 114 /*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID]
 115
 116  \param ID[in]                          RECEIVER identifier
 117  \param port_ID[in]                     mipi PORT identifier
 118
 119  \return RECEIVER[ID].PORT[port_ID].irq_info
 120  */
 121 rx_irq_info_t receiver_get_irq_info(
 122     const rx_ID_t                               ID,
 123     const enum mipi_port_id             port_ID);
 124
 125 /*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID]
 126
 127  \param ID[in]                          RECEIVER identifier
 128  \param port_ID[in]                     mipi PORT identifier
 129  \param irq_info[in]            irq status
 130
 131  \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info)
 132  */
 133 void receiver_irq_clear(
 134     const rx_ID_t                               ID,
 135     const enum mipi_port_id                     port_ID,
 136     const rx_irq_info_t                 irq_info);
 137
 138 /*! Write to a control register of INPUT_SYSTEM[ID]
 139
 140  \param ID[in]                          INPUT_SYSTEM identifier
 141  \param reg[in]                         register index
 142  \param value[in]                       The data to be written
 143
 144  \return none, INPUT_SYSTEM[ID].ctrl[reg] = value
 145  */
 146 STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store(
 147     const input_system_ID_t                     ID,
 148     const hrt_address                   reg,
 149     const hrt_data                              value);
 150
 151 /*! Read from a control register of INPUT_SYSTEM[ID]
 152
 153  \param ID[in]                          INPUT_SYSTEM identifier
 154  \param reg[in]                         register index
 155  \param value[in]                       The data to be written
 156
 157  \return INPUT_SYSTEM[ID].ctrl[reg]
 158  */
 159 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load(
 160     const input_system_ID_t                     ID,
 161     const hrt_address                   reg);
 162
 163 /*! Write to a control register of RECEIVER[ID]
 164
 165  \param ID[in]                          RECEIVER identifier
 166  \param reg[in]                         register index
 167  \param value[in]                       The data to be written
 168
 169  \return none, RECEIVER[ID].ctrl[reg] = value
 170  */
 171 STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store(
 172     const rx_ID_t                               ID,
 173     const hrt_address                   reg,
 174     const hrt_data                              value);
 175
 176 /*! Read from a control register of RECEIVER[ID]
 177
 178  \param ID[in]                          RECEIVER identifier
 179  \param reg[in]                         register index
 180  \param value[in]                       The data to be written
 181
 182  \return RECEIVER[ID].ctrl[reg]
 183  */
 184 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load(
 185     const rx_ID_t                               ID,
 186     const hrt_address                   reg);
 187
 188 /*! Write to a control register of PORT[port_ID] of RECEIVER[ID]
 189
 190  \param ID[in]                          RECEIVER identifier
 191  \param port_ID[in]                     mipi PORT identifier
 192  \param reg[in]                         register index
 193  \param value[in]                       The data to be written
 194
 195  \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value
 196  */
 197 STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store(
 198     const rx_ID_t                               ID,
 199     const enum mipi_port_id                     port_ID,
 200     const hrt_address                   reg,
 201     const hrt_data                              value);
 202
 203 /*! Read from a control register PORT[port_ID] of of RECEIVER[ID]
 204
 205  \param ID[in]                          RECEIVER identifier
 206  \param port_ID[in]                     mipi PORT identifier
 207  \param reg[in]                         register index
 208  \param value[in]                       The data to be written
 209
 210  \return RECEIVER[ID].PORT[port_ID].ctrl[reg]
 211  */
 212 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load(
 213     const rx_ID_t                               ID,
 214     const enum mipi_port_id             port_ID,
 215     const hrt_address                   reg);
 216
 217 /*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
 218
 219  \param ID[in]                          INPUT_SYSTEM identifier
 220  \param port_ID[in]                     sub system identifier
 221  \param reg[in]                         register index
 222  \param value[in]                       The data to be written
 223
 224  \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value
 225  */
 226 STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store(
 227     const input_system_ID_t                     ID,
 228     const sub_system_ID_t                       sub_ID,
 229     const hrt_address                   reg,
 230     const hrt_data                              value);
 231
 232 /*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
 233
 234  \param ID[in]                          INPUT_SYSTEM identifier
 235  \param port_ID[in]                     sub system identifier
 236  \param reg[in]                         register index
 237  \param value[in]                       The data to be written
 238
 239  \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg]
 240  */
 241 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load(
 242     const input_system_ID_t             ID,
 243     const sub_system_ID_t               sub_ID,
 244     const hrt_address                   reg);
 245
 246 ///////////////////////////////////////////////////////////////////////////
 247 //
 248 //    Functions for configuration phase on input system.
 249 //
 250 ///////////////////////////////////////////////////////////////////////////
 251
 252 // Function that resets current configuration.
 253 // remove the argument since it should be private.
 254 input_system_err_t input_system_configuration_reset(void);
 255
 256 // Function that commits current configuration.
 257 // remove the argument since it should be private.
 258 input_system_err_t input_system_configuration_commit(void);
 259
 260 ///////////////////////////////////////////////////////////////////////////
 261 //
 262 // User functions:
 263 //              (encoded generic function)
 264 //    - no checking
 265 //    - decoding name and agruments into the generic (channel) configuration
 266 //    function.
 267 //
 268 ///////////////////////////////////////////////////////////////////////////
 269
 270 // FIFO channel config function user
 271
 272 input_system_err_t      input_system_csi_fifo_channel_cfg(
 273     u32                         ch_id,
 274     input_system_csi_port_t     port,
 275     backend_channel_cfg_t       backend_ch,
 276     target_cfg2400_t                    target
 277 );
 278
 279 input_system_err_t      input_system_csi_fifo_channel_with_counting_cfg(
 280     u32                         ch_id,
 281     u32                         nof_frame,
 282     input_system_csi_port_t     port,
 283     backend_channel_cfg_t       backend_ch,
 284     u32                         mem_region_size,
 285     u32                         nof_mem_regions,
 286     target_cfg2400_t                    target
 287 );
 288
 289 // SRAM channel config function user
 290
 291 input_system_err_t      input_system_csi_sram_channel_cfg(
 292     u32                         ch_id,
 293     input_system_csi_port_t     port,
 294     backend_channel_cfg_t       backend_ch,
 295     u32                         csi_mem_region_size,
 296     u32                         csi_nof_mem_regions,
 297     target_cfg2400_t                    target
 298 );
 299
 300 //XMEM channel config function user
 301
 302 input_system_err_t      input_system_csi_xmem_channel_cfg(
 303     u32                         ch_id,
 304     input_system_csi_port_t port,
 305     backend_channel_cfg_t       backend_ch,
 306     u32                         mem_region_size,
 307     u32                         nof_mem_regions,
 308     u32                         acq_mem_region_size,
 309     u32                         acq_nof_mem_regions,
 310     target_cfg2400_t                    target,
 311     uint32_t                            nof_xmem_buffers
 312 );
 313
 314 input_system_err_t      input_system_csi_xmem_capture_only_channel_cfg(
 315     u32                         ch_id,
 316     u32                         nof_frames,
 317     input_system_csi_port_t port,
 318     u32                         csi_mem_region_size,
 319     u32                         csi_nof_mem_regions,
 320     u32                         acq_mem_region_size,
 321     u32                         acq_nof_mem_regions,
 322     target_cfg2400_t                    target
 323 );
 324
 325 input_system_err_t      input_system_csi_xmem_acquire_only_channel_cfg(
 326     u32                         ch_id,
 327     u32                         nof_frames,
 328     input_system_csi_port_t port,
 329     backend_channel_cfg_t       backend_ch,
 330     u32                         acq_mem_region_size,
 331     u32                         acq_nof_mem_regions,
 332     target_cfg2400_t                    target
 333 );
 334
 335 // Non - CSI channel config function user
 336
 337 input_system_err_t      input_system_prbs_channel_cfg(
 338     u32         ch_id,
 339     u32         nof_frames,
 340     u32         seed,
 341     u32         sync_gen_width,
 342     u32         sync_gen_height,
 343     u32         sync_gen_hblank_cycles,
 344     u32         sync_gen_vblank_cycles,
 345     target_cfg2400_t    target
 346 );
 347
 348 input_system_err_t      input_system_tpg_channel_cfg(
 349     u32         ch_id,
 350     u32         nof_frames,//not used yet
 351     u32         x_mask,
 352     u32         y_mask,
 353     u32         x_delta,
 354     u32         y_delta,
 355     u32         xy_mask,
 356     u32         sync_gen_width,
 357     u32         sync_gen_height,
 358     u32         sync_gen_hblank_cycles,
 359     u32         sync_gen_vblank_cycles,
 360     target_cfg2400_t    target
 361 );
 362
 363 input_system_err_t      input_system_gpfifo_channel_cfg(
 364     u32         ch_id,
 365     u32         nof_frames,
 366     target_cfg2400_t    target
 367 );
 368 #endif /* #ifdef ISP2401 */
 369
 370 #endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */