1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #ifndef _IA_CSS_ACC_TYPES_H
17 #define _IA_CSS_ACC_TYPES_H
20 * This file contains types used for acceleration
23 #include <system_local.h> /* HAS_IRQ_MAP_VERSION_# */
24 #include <type_support.h>
25 #include <platform_support.h>
26 #include <debug_global.h>
27 #include <linux/bits.h>
29 #include "ia_css_types.h"
30 #include "ia_css_frame_format.h"
32 /* Should be included without the path.
33 However, that requires adding the path to numerous makefiles
34 that have nothing to do with isp parameters.
36 #include "runtime/isp_param/interface/ia_css_isp_param_types.h"
38 /* Types for the acceleration API.
39 * These should be moved to sh_css_internal.h once the old acceleration
40 * argument handling has been completed.
41 * After that, interpretation of these structures is no longer needed
42 * in the kernel and HAL.
45 /* Type of acceleration.
47 enum ia_css_acc_type {
48 IA_CSS_ACC_NONE, /** Normal binary */
49 IA_CSS_ACC_OUTPUT, /** Accelerator stage on output frame */
50 IA_CSS_ACC_VIEWFINDER, /** Accelerator stage on viewfinder frame */
51 IA_CSS_ACC_STANDALONE, /** Stand-alone acceleration */
56 enum ia_css_cell_type {
66 ia_css_sp_firmware, /** Firmware for the SP */
67 ia_css_isp_firmware, /** Firmware for the ISP */
68 ia_css_bootloader_firmware, /** Firmware for the BootLoader */
69 ia_css_acc_firmware /** Firmware for accelrations */
72 struct ia_css_blob_descr;
75 * This structure describes an SP or ISP blob.
76 * It describes the test, data and bss sections as well as position in a
78 * For convenience, it contains dynamic data after loading.
80 struct ia_css_blob_info {
81 /** Static blob data */
82 u32 offset; /** Blob offset in fw file */
83 struct ia_css_isp_param_memory_offsets
84 memory_offsets; /** offset wrt hdr in bytes */
85 u32 prog_name_offset; /** offset wrt hdr in bytes */
86 u32 size; /** Size of blob */
87 u32 padding_size; /** total cummulative of bytes added due to section alignment */
88 u32 icache_source; /** Position of icache in blob */
89 u32 icache_size; /** Size of icache section */
90 u32 icache_padding;/** bytes added due to icache section alignment */
91 u32 text_source; /** Position of text in blob */
92 u32 text_size; /** Size of text section */
93 u32 text_padding; /** bytes added due to text section alignment */
94 u32 data_source; /** Position of data in blob */
95 u32 data_target; /** Start of data in SP dmem */
96 u32 data_size; /** Size of text section */
97 u32 data_padding; /** bytes added due to data section alignment */
98 u32 bss_target; /** Start position of bss in SP dmem */
99 u32 bss_size; /** Size of bss section */
100 /** Dynamic data filled by loader */
101 CSS_ALIGN(const void *code,
102 8); /** Code section absolute pointer within fw, code = icache + text */
103 CSS_ALIGN(const void *data,
104 8); /** Data section absolute pointer within fw, data = data + bss */
107 struct ia_css_binary_input_info {
112 u32 source; /* memory, sensor, variable */
115 struct ia_css_binary_output_info {
124 struct ia_css_binary_internal_info {
129 struct ia_css_binary_bds_info {
130 u32 supported_bds_factors;
133 struct ia_css_binary_dvs_info {
134 u32 max_envelope_width;
135 u32 max_envelope_height;
138 struct ia_css_binary_vf_dec_info {
140 u32 max_log_downscale;
143 struct ia_css_binary_s3a_info {
145 u32 fixed_s3a_deci_log;
148 /* DPC related binary info */
149 struct ia_css_binary_dpc_info {
150 u32 bnr_lite; /** bnr lite enable flag */
153 struct ia_css_binary_iterator_info {
155 u32 row_stripes_height;
156 u32 row_stripes_overlap_lines;
159 struct ia_css_binary_address_info {
160 u32 isp_addresses; /* Address in ISP dmem */
161 u32 main_entry; /* Address of entry fct */
162 u32 in_frame; /* Address in ISP dmem */
163 u32 out_frame; /* Address in ISP dmem */
164 u32 in_data; /* Address in ISP dmem */
165 u32 out_data; /* Address in ISP dmem */
166 u32 sh_dma_cmd_ptr; /* In ISP dmem */
169 struct ia_css_binary_uds_info {
176 u16 vectors_per_line_in;
177 u16 vectors_per_line_out;
178 u16 vectors_c_per_line_in;
179 u16 vectors_c_per_line_out;
180 u16 vmem_gdc_in_block_height_y;
181 u16 vmem_gdc_in_block_height_c;
182 /* uint16_t padding; */
185 struct ia_css_binary_pipeline_info {
187 u32 isp_pipe_version;
192 u32 variable_resolution;
195 struct ia_css_binary_block_info {
198 u32 output_block_height;
201 /* Structure describing an ISP binary.
202 * It describes the capabilities of a binary, like the maximum resolution,
203 * support features, dma channels, uds features, etc.
204 * This part is to be used by the SP.
205 * Future refactoring should move binary properties to ia_css_binary_xinfo,
206 * thereby making the SP code more binary independent.
208 struct ia_css_binary_info {
209 CSS_ALIGN(u32 id, 8); /* IA_CSS_BINARY_ID_* */
210 struct ia_css_binary_pipeline_info pipeline;
211 struct ia_css_binary_input_info input;
212 struct ia_css_binary_output_info output;
213 struct ia_css_binary_internal_info internal;
214 struct ia_css_binary_bds_info bds;
215 struct ia_css_binary_dvs_info dvs;
216 struct ia_css_binary_vf_dec_info vf_dec;
217 struct ia_css_binary_s3a_info s3a;
218 struct ia_css_binary_dpc_info dpc_bnr; /** DPC related binary info */
219 struct ia_css_binary_iterator_info iterator;
220 struct ia_css_binary_address_info addresses;
221 struct ia_css_binary_uds_info uds;
222 struct ia_css_binary_block_info block;
223 struct ia_css_isp_param_isp_segments mem_initializers;
224 /* MW: Packing (related) bools in an integer ?? */
256 /* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */
261 u8 dvs_coords_channel;
266 u8 vfdec_bits_per_pixel;
272 /* Structure describing an ISP binary.
273 * It describes the capabilities of a binary, like the maximum resolution,
274 * support features, dma channels, uds features, etc.
276 struct ia_css_binary_xinfo {
277 /* Part that is of interest to the SP. */
278 struct ia_css_binary_info sp;
280 /* Rest of the binary info, only interesting to the host. */
281 enum ia_css_acc_type type;
283 CSS_ALIGN(s32 num_output_formats, 8);
284 enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM];
286 CSS_ALIGN(s32 num_vf_formats, 8); /** number of supported vf formats */
287 enum ia_css_frame_format
288 vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /** types of supported vf formats */
290 ia_css_ptr xmem_addr;
292 CSS_ALIGN(const struct ia_css_blob_descr *blob, 8);
293 CSS_ALIGN(u32 blob_index, 8);
294 CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8);
295 CSS_ALIGN(struct ia_css_binary_xinfo *next, 8);
298 /* Structure describing the Bootloader (an ISP binary).
299 * It contains several address, either in ddr, isp_dmem or
300 * the entry function in icache.
302 struct ia_css_bl_info {
303 u32 num_dma_cmds; /** Number of cmds sent by CSS */
304 u32 dma_cmd_list; /** Dma command list sent by CSS */
305 u32 sw_state; /** Polled from css */
306 /* Entry functions */
307 u32 bl_entry; /** The SP entry function */
310 /* Structure describing the SP binary.
311 * It contains several address, either in ddr, sp_dmem or
312 * the entry function in pmem.
314 struct ia_css_sp_info {
315 u32 init_dmem_data; /** data sect config, stored to dmem */
316 u32 per_frame_data; /** Per frame data, stored to dmem */
317 u32 group; /** Per pipeline data, loaded by dma */
318 u32 output; /** SP output data, loaded by dmem */
319 u32 host_sp_queue; /** Host <-> SP queues */
320 u32 host_sp_com;/** Host <-> SP commands */
321 u32 isp_started; /** Polled from sensor thread, csim only */
322 u32 sw_state; /** Polled from css */
323 u32 host_sp_queues_initialized; /** Polled from the SP */
324 u32 sleep_mode; /** different mode to halt SP */
325 u32 invalidate_tlb; /** inform SP to invalidate mmu TLB */
328 u32 stop_copy_preview; /** suspend copy and preview pipe when capture */
330 u32 debug_buffer_ddr_address; /** inform SP the address
331 of DDR debug queue */
332 u32 perf_counter_input_system_error; /** input system perf
334 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
335 u32 debug_wait; /** thread/pipe post mortem debug */
336 u32 debug_stage; /** thread/pipe post mortem debug */
337 u32 debug_stripe; /** thread/pipe post mortem debug */
339 u32 threads_stack; /** sp thread's stack pointers */
340 u32 threads_stack_size; /** sp thread's stack sizes */
341 u32 curr_binary_id; /** current binary id */
342 u32 raw_copy_line_count; /** raw copy line counter */
343 u32 ddr_parameter_address; /** acc param ddrptr, sp dmem */
344 u32 ddr_parameter_size; /** acc param size, sp dmem */
345 /* Entry functions */
346 u32 sp_entry; /** The SP entry function */
347 u32 tagger_frames_addr; /** Base address of tagger state */
350 /* The following #if is there because this header file is also included
351 by SP and ISP code but they do not need this data and HIVECC has alignment
352 issue with the firmware struct/union's.
353 More permanent solution will be to refactor this include.
356 /* Accelerator firmware information.
358 struct ia_css_acc_info {
359 u32 per_frame_data; /** Dummy for now */
362 /* Firmware information.
364 union ia_css_fw_union {
365 struct ia_css_binary_xinfo isp; /** ISP info */
366 struct ia_css_sp_info sp; /** SP info */
367 struct ia_css_bl_info bl; /** Bootloader info */
368 struct ia_css_acc_info acc; /** Accelerator info */
371 /* Firmware information.
373 struct ia_css_fw_info {
374 size_t header_size; /** size of fw header */
376 CSS_ALIGN(u32 type, 8);
377 union ia_css_fw_union info; /** Binary info */
378 struct ia_css_blob_info blob; /** Blob info */
380 struct ia_css_fw_info *next;
382 CSS_ALIGN(u32 loaded, 8); /** Firmware has been loaded */
383 CSS_ALIGN(const u8 *isp_code, 8); /** ISP pointer to code */
384 /** Firmware handle between user space and kernel */
385 CSS_ALIGN(u32 handle, 8);
386 /** Sections to copy from/to ISP */
387 struct ia_css_isp_param_css_segments mem_initializers;
388 /** Initializer for local ISP memories */
391 struct ia_css_blob_descr {
392 const unsigned char *blob;
393 struct ia_css_fw_info header;
395 union ia_css_all_memory_offsets mem_offsets;
398 struct ia_css_acc_fw;
400 /* Structure describing the SP binary of a stand-alone accelerator.
402 struct ia_css_acc_sp {
403 void (*init)(struct ia_css_acc_fw *); /** init for crun */
404 u32 sp_prog_name_offset; /** program name offset wrt hdr in bytes */
405 u32 sp_blob_offset; /** blob offset wrt hdr in bytes */
406 void *entry; /** Address of sp entry point */
407 u32 *css_abort; /** SP dmem abort flag */
408 void *isp_code; /** SP dmem address holding xmem
409 address of isp code */
410 struct ia_css_fw_info fw; /** SP fw descriptor */
411 const u8 *code; /** ISP pointer of allocated SP code */
414 /* Acceleration firmware descriptor.
415 * This descriptor descibes either SP code (stand-alone), or
416 * ISP code (a separate pipeline stage).
418 struct ia_css_acc_fw_hdr {
419 enum ia_css_acc_type type; /** Type of accelerator */
420 u32 isp_prog_name_offset; /** program name offset wrt
422 u32 isp_blob_offset; /** blob offset wrt header
424 u32 isp_size; /** Size of isp blob */
425 const u8 *isp_code; /** ISP pointer to code */
426 struct ia_css_acc_sp sp; /** Standalone sp code */
427 /** Firmware handle between user space and kernel */
429 struct ia_css_data parameters; /** Current SP parameters */
432 /* Firmware structure.
433 * This contains the header and actual blobs.
434 * For standalone, it contains SP and ISP blob.
435 * For a pipeline stage accelerator, it contains ISP code only.
436 * Since its members are variable size, their offsets are described in the
437 * header and computed using the access macros below.
439 struct ia_css_acc_fw {
440 struct ia_css_acc_fw_hdr header; /** firmware header */
442 int8_t isp_progname[]; **< ISP program name
443 int8_t sp_progname[]; **< SP program name, stand-alone only
444 uint8_t sp_code[]; **< SP blob, stand-alone only
445 uint8_t isp_code[]; **< ISP blob
449 /* Access macros for firmware */
450 #define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f) + (f->header.n)))
451 #define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \
452 sp.sp_prog_name_offset)
453 #define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \
454 isp_prog_name_offset)
455 #define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \
457 #define IA_CSS_ACC_SP_DATA(f) (IA_CSS_ACC_SP_CODE(f) + \
458 (f)->header.sp.fw.blob.data_source)
459 #define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\
461 #define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size)
463 /* Binary name follows header immediately */
464 #define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f) + (f)->blob.prog_name_offset)
465 #define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \
466 ((const struct ia_css_memory_offsets *)((const char *)(f) + (f)->blob.mem_offsets))
468 enum ia_css_sp_sleep_mode {
469 SP_DISABLE_SLEEP_MODE = 0,
470 SP_SLEEP_AFTER_FRAME = BIT(0),
471 SP_SLEEP_AFTER_IRQ = BIT(1),
473 #endif /* _IA_CSS_ACC_TYPES_H */