1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #ifndef _hive_isp_css_defs_h__
17 #define _hive_isp_css_defs_h__
19 #define HIVE_ISP_CTRL_DATA_WIDTH 32
20 #define HIVE_ISP_CTRL_ADDRESS_WIDTH 32
21 #define HIVE_ISP_CTRL_MAX_BURST_SIZE 1
22 #define HIVE_ISP_DDR_ADDRESS_WIDTH 36
24 #define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */
25 #define HIVE_ISP_NUM_GPIO_PINS 12
27 /* This list of vector num_elems/elem_bits pairs is valid both in C as initializer
28 and in the DMA parameter list */
29 #define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
30 #define HIVE_ISP_DDR_WORD_BITS 256
31 #define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8)
32 #define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */
33 #define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */
34 #define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
35 #define HIVE_ISP_PAGE_SHIFT 12
36 #define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT)
38 #define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
39 #define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
41 /* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */
42 /* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */
43 #define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */
45 #define HIVE_DMA_ISP_BUS_CONN 0
46 #define HIVE_DMA_ISP_DDR_CONN 1
47 #define HIVE_DMA_BUS_DDR_CONN 2
48 #define HIVE_DMA_ISP_MASTER master_port0
49 #define HIVE_DMA_BUS_MASTER master_port1
50 #define HIVE_DMA_DDR_MASTER master_port2
52 #define HIVE_DMA_NUM_CHANNELS 32 /* old value was 8 */
53 #define HIVE_DMA_CMD_FIFO_DEPTH 24 /* old value was 12 */
55 #define HIVE_IF_PIXEL_WIDTH 12
57 #define HIVE_MMU_TLB_SETS 8
58 #define HIVE_MMU_TLB_SET_BLOCKS 8
59 #define HIVE_MMU_TLB_BLOCK_ELEMENTS 8
60 #define HIVE_MMU_PAGE_TABLE_LEVELS 2
61 #define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE
63 #define HIVE_ISP_CH_ID_BITS 2
64 #define HIVE_ISP_FMT_TYPE_BITS 5
65 #define HIVE_ISP_ISEL_SEL_BITS 2
67 #define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 0
68 #define HIVE_GP_REGS_IDLE_IDX 1
69 #define HIVE_GP_REGS_IRQ_0_IDX 2
70 #define HIVE_GP_REGS_IRQ_1_IDX 3
71 #define HIVE_GP_REGS_SP_STREAM_STAT_IDX 4
72 #define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX 5
73 #define HIVE_GP_REGS_ISP_STREAM_STAT_IDX 6
74 #define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7
75 #define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX 8
76 #define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX 9
77 #define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX 10
78 #define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX 11
79 #define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX 12
80 #define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX 13
81 #define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX 14
82 #define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX 15
83 #define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX 16
84 #define HIVE_GP_REGS_SWITCH_GDC1_IDX 17
85 #define HIVE_GP_REGS_SWITCH_GDC2_IDX 18
86 #define HIVE_GP_REGS_SRST_IDX 19
87 #define HIVE_GP_REGS_SLV_REG_SRST_IDX 20
89 /* Bit numbers of the soft reset register */
90 #define HIVE_GP_REGS_SRST_ISYS_CBUS 0
91 #define HIVE_GP_REGS_SRST_ISEL_CBUS 1
92 #define HIVE_GP_REGS_SRST_IFMT_CBUS 2
93 #define HIVE_GP_REGS_SRST_GPDEV_CBUS 3
94 #define HIVE_GP_REGS_SRST_GPIO 4
95 #define HIVE_GP_REGS_SRST_TC 5
96 #define HIVE_GP_REGS_SRST_GPTIMER 6
97 #define HIVE_GP_REGS_SRST_FACELLFIFOS 7
98 #define HIVE_GP_REGS_SRST_D_OSYS 8
99 #define HIVE_GP_REGS_SRST_IFT_SEC_PIPE 9
100 #define HIVE_GP_REGS_SRST_GDC1 10
101 #define HIVE_GP_REGS_SRST_GDC2 11
102 #define HIVE_GP_REGS_SRST_VEC_BUS 12
103 #define HIVE_GP_REGS_SRST_ISP 13
104 #define HIVE_GP_REGS_SRST_SLV_GRP_BUS 14
105 #define HIVE_GP_REGS_SRST_DMA 15
106 #define HIVE_GP_REGS_SRST_SF_ISP_SP 16
107 #define HIVE_GP_REGS_SRST_SF_PIF_CELLS 17
108 #define HIVE_GP_REGS_SRST_SF_SIF_SP 18
109 #define HIVE_GP_REGS_SRST_SF_MC_SP 19
110 #define HIVE_GP_REGS_SRST_SF_ISYS_SP 20
111 #define HIVE_GP_REGS_SRST_SF_DMA_CELLS 21
112 #define HIVE_GP_REGS_SRST_SF_GDC1_CELLS 22
113 #define HIVE_GP_REGS_SRST_SF_GDC2_CELLS 23
114 #define HIVE_GP_REGS_SRST_SP 24
115 #define HIVE_GP_REGS_SRST_OCP2CIO 25
116 #define HIVE_GP_REGS_SRST_NBUS 26
117 #define HIVE_GP_REGS_SRST_HOST12BUS 27
118 #define HIVE_GP_REGS_SRST_WBUS 28
119 #define HIVE_GP_REGS_SRST_IC_OSYS 29
120 #define HIVE_GP_REGS_SRST_WBUS_IC 30
122 /* Bit numbers of the slave register soft reset register */
123 #define HIVE_GP_REGS_SLV_REG_SRST_DMA 0
124 #define HIVE_GP_REGS_SLV_REG_SRST_GDC1 1
125 #define HIVE_GP_REGS_SLV_REG_SRST_GDC2 2
127 /* order of the input bits for the irq controller */
128 #define HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID 0
129 #define HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID 1
130 #define HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID 2
131 #define HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID 3
132 #define HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID 4
133 #define HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID 5
134 #define HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID 6
135 #define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7
136 #define HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID 8
137 #define HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID 9
138 #define HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID 10
139 #define HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID 11
140 #define HIVE_GP_DEV_IRQ_SP_BIT_ID 12
141 #define HIVE_GP_DEV_IRQ_ISP_BIT_ID 13
142 #define HIVE_GP_DEV_IRQ_ISYS_BIT_ID 14
143 #define HIVE_GP_DEV_IRQ_ISEL_BIT_ID 15
144 #define HIVE_GP_DEV_IRQ_IFMT_BIT_ID 16
145 #define HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID 17
146 #define HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID 18
147 #define HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID 19
148 #define HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID 20
149 #define HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID 21
150 #define HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID 22
151 #define HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID 23
152 #define HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID 24
153 #define HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID 25
154 #define HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID 26
155 #define HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID 27
156 #define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28
157 #define HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID 29
158 #define HIVE_GP_DEV_IRQ_DMA_BIT_ID 30
159 #define HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID 31
161 #define HIVE_GP_REGS_NUM_SW_IRQ_REGS 2
163 /* order of the input bits for the timed controller */
164 #define HIVE_GP_DEV_TC_GPIO_PIN_0_BIT_ID 0
165 #define HIVE_GP_DEV_TC_GPIO_PIN_1_BIT_ID 1
166 #define HIVE_GP_DEV_TC_GPIO_PIN_2_BIT_ID 2
167 #define HIVE_GP_DEV_TC_GPIO_PIN_3_BIT_ID 3
168 #define HIVE_GP_DEV_TC_GPIO_PIN_4_BIT_ID 4
169 #define HIVE_GP_DEV_TC_GPIO_PIN_5_BIT_ID 5
170 #define HIVE_GP_DEV_TC_GPIO_PIN_6_BIT_ID 6
171 #define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7
172 #define HIVE_GP_DEV_TC_GPIO_PIN_8_BIT_ID 8
173 #define HIVE_GP_DEV_TC_GPIO_PIN_9_BIT_ID 9
174 #define HIVE_GP_DEV_TC_GPIO_PIN_10_BIT_ID 10
175 #define HIVE_GP_DEV_TC_GPIO_PIN_11_BIT_ID 11
176 #define HIVE_GP_DEV_TC_SP_BIT_ID 12
177 #define HIVE_GP_DEV_TC_ISP_BIT_ID 13
178 #define HIVE_GP_DEV_TC_ISYS_BIT_ID 14
179 #define HIVE_GP_DEV_TC_ISEL_BIT_ID 15
180 #define HIVE_GP_DEV_TC_IFMT_BIT_ID 16
181 #define HIVE_GP_DEV_TC_GP_TIMER_0_BIT_ID 17
182 #define HIVE_GP_DEV_TC_GP_TIMER_1_BIT_ID 18
183 #define HIVE_GP_DEV_TC_MIPI_SOL_BIT_ID 19
184 #define HIVE_GP_DEV_TC_MIPI_EOL_BIT_ID 20
185 #define HIVE_GP_DEV_TC_MIPI_SOF_BIT_ID 21
186 #define HIVE_GP_DEV_TC_MIPI_EOF_BIT_ID 22
187 #define HIVE_GP_DEV_TC_INPSYS_SM 23
189 /* definitions for the gp_timer block */
190 #define HIVE_GP_TIMER_0 0
191 #define HIVE_GP_TIMER_1 1
192 #define HIVE_GP_TIMER_2 2
193 #define HIVE_GP_TIMER_3 3
194 #define HIVE_GP_TIMER_4 4
195 #define HIVE_GP_TIMER_5 5
196 #define HIVE_GP_TIMER_6 6
197 #define HIVE_GP_TIMER_7 7
198 #define HIVE_GP_TIMER_NUM_COUNTERS 8
200 #define HIVE_GP_TIMER_IRQ_0 0
201 #define HIVE_GP_TIMER_IRQ_1 1
202 #define HIVE_GP_TIMER_NUM_IRQS 2
204 #define HIVE_GP_TIMER_GPIO_0_BIT_ID 0
205 #define HIVE_GP_TIMER_GPIO_1_BIT_ID 1
206 #define HIVE_GP_TIMER_GPIO_2_BIT_ID 2
207 #define HIVE_GP_TIMER_GPIO_3_BIT_ID 3
208 #define HIVE_GP_TIMER_GPIO_4_BIT_ID 4
209 #define HIVE_GP_TIMER_GPIO_5_BIT_ID 5
210 #define HIVE_GP_TIMER_GPIO_6_BIT_ID 6
211 #define HIVE_GP_TIMER_GPIO_7_BIT_ID 7
212 #define HIVE_GP_TIMER_GPIO_8_BIT_ID 8
213 #define HIVE_GP_TIMER_GPIO_9_BIT_ID 9
214 #define HIVE_GP_TIMER_GPIO_10_BIT_ID 10
215 #define HIVE_GP_TIMER_GPIO_11_BIT_ID 11
216 #define HIVE_GP_TIMER_INP_SYS_IRQ 12
217 #define HIVE_GP_TIMER_ISEL_IRQ 13
218 #define HIVE_GP_TIMER_IFMT_IRQ 14
219 #define HIVE_GP_TIMER_SP_STRMON_IRQ 15
220 #define HIVE_GP_TIMER_SP_B_STRMON_IRQ 16
221 #define HIVE_GP_TIMER_ISP_STRMON_IRQ 17
222 #define HIVE_GP_TIMER_MOD_STRMON_IRQ 18
223 #define HIVE_GP_TIMER_ISP_BAMEM_ERROR_IRQ 20
224 #define HIVE_GP_TIMER_ISP_DMEM_ERROR_IRQ 21
225 #define HIVE_GP_TIMER_SP_ICACHE_MEM_ERROR_IRQ 22
226 #define HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ 23
227 #define HIVE_GP_TIMER_SP_OUT_RUN_DP 24
228 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 25
229 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 26
230 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I2 27
231 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I3 28
232 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I4 29
233 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I5 30
234 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I6 31
235 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I7 32
236 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I8 33
237 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I9 34
238 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I10 35
239 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 36
240 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 37
241 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 38
242 #define HIVE_GP_TIMER_ISP_OUT_RUN_DP 39
243 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 40
244 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 41
245 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 42
246 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 43
247 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I1 44
248 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I2 45
249 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I3 46
250 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I4 47
251 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I5 48
252 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I6 49
253 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 50
254 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
255 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
256 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
257 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
258 #define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
259 #define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
260 #define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
261 #define HIVE_GP_TIMER_MIPI_EOF_BIT_ID 58
262 #define HIVE_GP_TIMER_INPSYS_SM 59
264 /* port definitions for the streaming monitors */
265 /* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
266 #define SP_STR_MON_PORT_SP2SIF 0
267 #define SP_STR_MON_PORT_SIF2SP 1
268 #define SP_STR_MON_PORT_SP2MC 2
269 #define SP_STR_MON_PORT_MC2SP 3
270 #define SP_STR_MON_PORT_SP2DMA 4
271 #define SP_STR_MON_PORT_DMA2SP 5
272 #define SP_STR_MON_PORT_SP2ISP 6
273 #define SP_STR_MON_PORT_ISP2SP 7
274 #define SP_STR_MON_PORT_SP2GPD 8
275 #define SP_STR_MON_PORT_FA2SP 9
276 #define SP_STR_MON_PORT_SP2ISYS 10
277 #define SP_STR_MON_PORT_ISYS2SP 11
278 #define SP_STR_MON_PORT_SP2PIFA 12
279 #define SP_STR_MON_PORT_PIFA2SP 13
280 #define SP_STR_MON_PORT_SP2PIFB 14
281 #define SP_STR_MON_PORT_PIFB2SP 15
283 #define SP_STR_MON_PORT_B_SP2GDC1 0
284 #define SP_STR_MON_PORT_B_GDC12SP 1
285 #define SP_STR_MON_PORT_B_SP2GDC2 2
286 #define SP_STR_MON_PORT_B_GDC22SP 3
288 /* previously used SP streaming monitor port identifiers, kept for backward compatibility */
289 #define SP_STR_MON_PORT_SND_SIF SP_STR_MON_PORT_SP2SIF
290 #define SP_STR_MON_PORT_RCV_SIF SP_STR_MON_PORT_SIF2SP
291 #define SP_STR_MON_PORT_SND_MC SP_STR_MON_PORT_SP2MC
292 #define SP_STR_MON_PORT_RCV_MC SP_STR_MON_PORT_MC2SP
293 #define SP_STR_MON_PORT_SND_DMA SP_STR_MON_PORT_SP2DMA
294 #define SP_STR_MON_PORT_RCV_DMA SP_STR_MON_PORT_DMA2SP
295 #define SP_STR_MON_PORT_SND_ISP SP_STR_MON_PORT_SP2ISP
296 #define SP_STR_MON_PORT_RCV_ISP SP_STR_MON_PORT_ISP2SP
297 #define SP_STR_MON_PORT_SND_GPD SP_STR_MON_PORT_SP2GPD
298 #define SP_STR_MON_PORT_RCV_GPD SP_STR_MON_PORT_FA2SP
300 #define SP_STR_MON_PORT_SND_PIF SP_STR_MON_PORT_SP2PIFA
301 #define SP_STR_MON_PORT_RCV_PIF SP_STR_MON_PORT_PIFA2SP
302 #define SP_STR_MON_PORT_SND_PIFB SP_STR_MON_PORT_SP2PIFB
303 #define SP_STR_MON_PORT_RCV_PIFB SP_STR_MON_PORT_PIFB2SP
305 #define SP_STR_MON_PORT_SND_PIF_A SP_STR_MON_PORT_SP2PIFA
306 #define SP_STR_MON_PORT_RCV_PIF_A SP_STR_MON_PORT_PIFA2SP
307 #define SP_STR_MON_PORT_SND_PIF_B SP_STR_MON_PORT_SP2PIFB
308 #define SP_STR_MON_PORT_RCV_PIF_B SP_STR_MON_PORT_PIFB2SP
310 /* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
311 #define ISP_STR_MON_PORT_ISP2PIFA 0
312 #define ISP_STR_MON_PORT_PIFA2ISP 1
313 #define ISP_STR_MON_PORT_ISP2PIFB 2
314 #define ISP_STR_MON_PORT_PIFB2ISP 3
315 #define ISP_STR_MON_PORT_ISP2DMA 4
316 #define ISP_STR_MON_PORT_DMA2ISP 5
317 #define ISP_STR_MON_PORT_ISP2GDC1 6
318 #define ISP_STR_MON_PORT_GDC12ISP 7
319 #define ISP_STR_MON_PORT_ISP2GDC2 8
320 #define ISP_STR_MON_PORT_GDC22ISP 9
321 #define ISP_STR_MON_PORT_ISP2GPD 10
322 #define ISP_STR_MON_PORT_FA2ISP 11
323 #define ISP_STR_MON_PORT_ISP2SP 12
324 #define ISP_STR_MON_PORT_SP2ISP 13
326 /* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
327 #define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
328 #define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
329 #define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
330 #define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
331 #define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
332 #define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
333 #define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
334 #define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
335 #define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
336 #define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
337 #define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
338 #define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
340 /* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
342 #define MOD_STR_MON_PORT_PIFA2CELLS 0
343 #define MOD_STR_MON_PORT_CELLS2PIFA 1
344 #define MOD_STR_MON_PORT_PIFB2CELLS 2
345 #define MOD_STR_MON_PORT_CELLS2PIFB 3
346 #define MOD_STR_MON_PORT_SIF2SP 4
347 #define MOD_STR_MON_PORT_SP2SIF 5
348 #define MOD_STR_MON_PORT_MC2SP 6
349 #define MOD_STR_MON_PORT_SP2MC 7
350 #define MOD_STR_MON_PORT_DMA2ISP 8
351 #define MOD_STR_MON_PORT_ISP2DMA 9
352 #define MOD_STR_MON_PORT_DMA2SP 10
353 #define MOD_STR_MON_PORT_SP2DMA 11
354 #define MOD_STR_MON_PORT_GDC12CELLS 12
355 #define MOD_STR_MON_PORT_CELLS2GDC1 13
356 #define MOD_STR_MON_PORT_GDC22CELLS 14
357 #define MOD_STR_MON_PORT_CELLS2GDC2 15
359 #define MOD_STR_MON_PORT_SND_PIF_A 0
360 #define MOD_STR_MON_PORT_RCV_PIF_A 1
361 #define MOD_STR_MON_PORT_SND_PIF_B 2
362 #define MOD_STR_MON_PORT_RCV_PIF_B 3
363 #define MOD_STR_MON_PORT_SND_SIF 4
364 #define MOD_STR_MON_PORT_RCV_SIF 5
365 #define MOD_STR_MON_PORT_SND_MC 6
366 #define MOD_STR_MON_PORT_RCV_MC 7
367 #define MOD_STR_MON_PORT_SND_DMA2ISP 8
368 #define MOD_STR_MON_PORT_RCV_DMA_FR_ISP 9
369 #define MOD_STR_MON_PORT_SND_DMA2SP 10
370 #define MOD_STR_MON_PORT_RCV_DMA_FR_SP 11
371 #define MOD_STR_MON_PORT_SND_GDC 12
372 #define MOD_STR_MON_PORT_RCV_GDC 13
374 /* testbench signals: */
376 /* testbench GP adapter register ids */
377 #define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0
378 #define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1
379 #define HIVE_TESTBENCH_IRQ_REG_IDX 2
380 #define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3
381 #define HIVE_TESTBENCH_IDLE_REG_IDX 4
382 #define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5
383 #define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6
384 #define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
385 #define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8
387 #define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9
388 #define HIVE_TESTBENCH_ISP_BAMEM_ERROR_IRQ_REG_IDX 10
389 #define HIVE_TESTBENCH_ISP_DMEM_ERROR_IRQ_REG_IDX 11
390 #define HIVE_TESTBENCH_SP_ICACHE_MEM_ERROR_IRQ_REG_IDX 12
391 #define HIVE_TESTBENCH_SP_DMEM_ERROR_IRQ_REG_IDX 13
393 /* Signal monitor input bit ids */
394 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_O_BIT_ID 0
395 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_1_BIT_ID 1
396 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_2_BIT_ID 2
397 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_3_BIT_ID 3
398 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_4_BIT_ID 4
399 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_5_BIT_ID 5
400 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_6_BIT_ID 6
401 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_7_BIT_ID 7
402 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_8_BIT_ID 8
403 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_9_BIT_ID 9
404 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_10_BIT_ID 10
405 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_11_BIT_ID 11
406 #define HIVE_TESTBENCH_SIG_MON_IRQ_PIN_BIT_ID 12
407 #define HIVE_TESTBENCH_SIG_MON_SDRAM_WAKEUP_PIN_BIT_ID 13
408 #define HIVE_TESTBENCH_SIG_MON_IDLE_PIN_BIT_ID 14
410 #define ISP2400_DEBUG_NETWORK 1
412 #endif /* _hive_isp_css_defs_h__ */