1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #ifndef __ISP_GLOBAL_H_INCLUDED__
17 #define __ISP_GLOBAL_H_INCLUDED__
19 #include <system_local.h>
21 #include "mamoiada_params.h"
23 #define ISP_PMEM_WIDTH_LOG2 ISP_LOG2_PMEM_WIDTH
24 #define ISP_PMEM_SIZE ISP_PMEM_DEPTH
26 #define ISP_NWAY_LOG2 6
27 #define ISP_VEC_NELEMS_LOG2 ISP_NWAY_LOG2
29 #ifdef PIPE_GENERATION
30 #define PIPEMEM(x) MEM(x)
31 #define ISP_NWAY BIT(ISP_NWAY_LOG2)
36 /* The number of data bytes in a vector disregarding the reduced precision */
37 #define ISP_VEC_BYTES (ISP_VEC_NELEMS * sizeof(uint16_t))
39 /* ISP SC Registers */
40 #define ISP_SC_REG 0x00
41 #define ISP_PC_REG 0x07
42 #define ISP_IRQ_READY_REG 0x00
43 #define ISP_IRQ_CLEAR_REG 0x00
45 /* ISP SC Register bits */
46 #define ISP_RST_BIT 0x00
47 #define ISP_START_BIT 0x01
48 #define ISP_BREAK_BIT 0x02
49 #define ISP_RUN_BIT 0x03
50 #define ISP_BROKEN_BIT 0x04
51 #define ISP_IDLE_BIT 0x05 /* READY */
52 #define ISP_SLEEPING_BIT 0x06
53 #define ISP_STALLING_BIT 0x07
54 #define ISP_IRQ_CLEAR_BIT 0x08
55 #define ISP_IRQ_READY_BIT 0x0A
56 #define ISP_IRQ_SLEEPING_BIT 0x0B
58 /* ISP Register bits */
59 #define ISP_CTRL_SINK_BIT 0x00
60 #define ISP_PMEM_SINK_BIT 0x01
61 #define ISP_DMEM_SINK_BIT 0x02
62 #define ISP_FIFO0_SINK_BIT 0x03
63 #define ISP_FIFO1_SINK_BIT 0x04
64 #define ISP_FIFO2_SINK_BIT 0x05
65 #define ISP_FIFO3_SINK_BIT 0x06
66 #define ISP_FIFO4_SINK_BIT 0x07
67 #define ISP_FIFO5_SINK_BIT 0x08
68 #define ISP_FIFO6_SINK_BIT 0x09
69 #define ISP_VMEM_SINK_BIT 0x0A
70 #define ISP_VAMEM1_SINK_BIT 0x0B
71 #define ISP_VAMEM2_SINK_BIT 0x0C
72 #define ISP_VAMEM3_SINK_BIT 0x0D
73 #define ISP_HMEM_SINK_BIT 0x0E
75 #define ISP_CTRL_SINK_REG 0x08
76 #define ISP_PMEM_SINK_REG 0x08
77 #define ISP_DMEM_SINK_REG 0x08
78 #define ISP_FIFO0_SINK_REG 0x08
79 #define ISP_FIFO1_SINK_REG 0x08
80 #define ISP_FIFO2_SINK_REG 0x08
81 #define ISP_FIFO3_SINK_REG 0x08
82 #define ISP_FIFO4_SINK_REG 0x08
83 #define ISP_FIFO5_SINK_REG 0x08
84 #define ISP_FIFO6_SINK_REG 0x08
85 #define ISP_VMEM_SINK_REG 0x08
86 #define ISP_VAMEM1_SINK_REG 0x08
87 #define ISP_VAMEM2_SINK_REG 0x08
88 #define ISP_VAMEM3_SINK_REG 0x08
89 #define ISP_HMEM_SINK_REG 0x08
93 #define XNR3_DOWN_BAMEM_BASE_ADDRESS (0x16880)
94 #define XNR3_UP_BAMEM_BASE_ADDRESS (0x12880)
95 #define bmem_ldrow(fu, pid, offset, data) bmem_ldrow_s(fu, pid, offset, data)
96 #define bmem_strow(fu, pid, offset, data) bmem_strow_s(fu, pid, offset, data)
97 #define bmem_ldblk(fu, pid, offset, data) bmem_ldblk_s(fu, pid, offset, data)
98 #define bmem_stblk(fu, pid, offset, data) bmem_stblk_s(fu, pid, offset, data)
100 #endif /* __ISP_GLOBAL_H_INCLUDED__ */