1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #ifndef __GP_DEVICE_GLOBAL_H_INCLUDED__
17 #define __GP_DEVICE_GLOBAL_H_INCLUDED__
19 #define IS_GP_DEVICE_VERSION_2
21 #define _REG_GP_IRQ_REQ0_ADDR 0x08
22 #define _REG_GP_IRQ_REQ1_ADDR 0x0C
23 /* The SP sends SW interrupt info to this register */
24 #define _REG_GP_IRQ_REQUEST0_ADDR _REG_GP_IRQ_REQ0_ADDR
25 #define _REG_GP_IRQ_REQUEST1_ADDR _REG_GP_IRQ_REQ1_ADDR
27 /* The SP configures FIFO switches in these registers */
28 #define _REG_GP_SWITCH_IF_ADDR 0x40
29 #define _REG_GP_SWITCH_GDC1_ADDR 0x44
30 #define _REG_GP_SWITCH_GDC2_ADDR 0x48
31 /* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */
32 #define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800
33 #define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804
34 #define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808
35 #define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C
36 #define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810
37 #define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814
38 #define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818
39 #define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C
40 #define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820
41 #define _REG_GP_IFMT_srst 0x00030824
42 #define _REG_GP_IFMT_slv_reg_srst 0x00030828
43 #define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C
45 /* @ GP_DEVICE_BASE */
46 #define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000
47 #define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004
48 #define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008
49 #define _REG_GP_NR_FRAMES_ADDR 0x0009000C
50 #define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010
51 #define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014
52 #define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018
53 #define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C
54 #define _REG_GP_ISEL_SOF_ADDR 0x00090020
55 #define _REG_GP_ISEL_EOF_ADDR 0x00090024
56 #define _REG_GP_ISEL_SOL_ADDR 0x00090028
57 #define _REG_GP_ISEL_EOL_ADDR 0x0009002C
58 #define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030
59 #define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034
60 #define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038
61 #define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C
62 #define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040
63 #define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044
64 #define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048
65 #define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C
66 #define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050
67 #define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054
68 #define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058
69 #define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C
70 #define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060
71 #define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064
72 #define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068
73 #define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C
74 #define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070
75 #define _REG_GP_ISEL_CH_ID_ADDR 0x00090074
76 #define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078
77 #define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C
78 #define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080
79 #define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084
80 #define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088
81 #define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C
82 #define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090
83 #define _REG_GP_SOFT_RESET_ADDR 0x00090094
85 #endif /* __GP_DEVICE_GLOBAL_H_INCLUDED__ */