2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include "gdc_device.h" /* gdc_lut_store(), ... */
16 #include "isp.h" /* ISP_VEC_ELEMBITS */
18 #if !defined(HAS_NO_HMEM)
19 #ifndef __INLINE_HMEM__
20 #define __INLINE_HMEM__
23 #endif /* !defined(HAS_NO_HMEM) */
24 #define IA_CSS_INCLUDE_PARAMETERS
25 #define IA_CSS_INCLUDE_ACC_PARAMETERS
27 #include "sh_css_params.h"
28 #include "ia_css_queue.h"
29 #include "sw_event_global.h" /* Event IDs */
31 #include "platform_support.h"
32 #include "assert_support.h"
33 #include "misc_support.h" /* NOT_USED */
34 #include "math_support.h" /* max(), min() EVEN_FLOOR()*/
36 #include "ia_css_stream.h"
37 #include "sh_css_params_internal.h"
38 #include "sh_css_param_shading.h"
39 #include "sh_css_param_dvs.h"
40 #include "ia_css_refcount.h"
41 #include "sh_css_internal.h"
42 #include "ia_css_control.h"
43 #include "ia_css_shading.h"
44 #include "sh_css_defs.h"
45 #include "sh_css_sp.h"
46 #include "ia_css_pipeline.h"
47 #include "ia_css_debug.h"
48 #include "memory_access.h"
50 #include "memory_realloc.h"
52 #include "ia_css_isp_param.h"
53 #include "ia_css_isp_params.h"
54 #include "ia_css_mipi.h"
55 #include "ia_css_morph.h"
56 #include "ia_css_host_data.h"
57 #include "ia_css_pipe.h"
58 #include "ia_css_pipe_binarydesc.h"
60 #include "ia_css_system_ctrl.h"
63 /* Include all kernel host interfaces for ISP1 */
65 #include "anr/anr_1.0/ia_css_anr.host.h"
66 #include "cnr/cnr_1.0/ia_css_cnr.host.h"
67 #include "csc/csc_1.0/ia_css_csc.host.h"
68 #include "de/de_1.0/ia_css_de.host.h"
69 #include "dp/dp_1.0/ia_css_dp.host.h"
70 #include "bnr/bnr_1.0/ia_css_bnr.host.h"
71 #include "dvs/dvs_1.0/ia_css_dvs.host.h"
72 #include "fpn/fpn_1.0/ia_css_fpn.host.h"
73 #include "gc/gc_1.0/ia_css_gc.host.h"
74 #include "macc/macc_1.0/ia_css_macc.host.h"
75 #include "ctc/ctc_1.0/ia_css_ctc.host.h"
76 #include "ob/ob_1.0/ia_css_ob.host.h"
77 #include "raw/raw_1.0/ia_css_raw.host.h"
78 #include "fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h"
79 #include "s3a/s3a_1.0/ia_css_s3a.host.h"
80 #include "sc/sc_1.0/ia_css_sc.host.h"
81 #include "sdis/sdis_1.0/ia_css_sdis.host.h"
82 #include "tnr/tnr_1.0/ia_css_tnr.host.h"
83 #include "uds/uds_1.0/ia_css_uds_param.h"
84 #include "wb/wb_1.0/ia_css_wb.host.h"
85 #include "ynr/ynr_1.0/ia_css_ynr.host.h"
86 #include "xnr/xnr_1.0/ia_css_xnr.host.h"
88 /* Include additional kernel host interfaces for ISP2 */
90 #include "aa/aa_2/ia_css_aa2.host.h"
91 #include "anr/anr_2/ia_css_anr2.host.h"
92 #include "bh/bh_2/ia_css_bh.host.h"
93 #include "cnr/cnr_2/ia_css_cnr2.host.h"
94 #include "ctc/ctc1_5/ia_css_ctc1_5.host.h"
95 #include "de/de_2/ia_css_de2.host.h"
96 #include "gc/gc_2/ia_css_gc2.host.h"
97 #include "sdis/sdis_2/ia_css_sdis2.host.h"
98 #include "ynr/ynr_2/ia_css_ynr2.host.h"
99 #include "fc/fc_1.0/ia_css_formats.host.h"
101 #include "xnr/xnr_3.0/ia_css_xnr3.host.h"
103 #if defined(HAS_OUTPUT_SYSTEM)
104 #include <components/output_system/sc_output_system_1.0/host/output_system.host.h>
107 #include "sh_css_frac.h"
108 #include "ia_css_bufq.h"
110 #define FPNTBL_BYTES(binary) \
111 (sizeof(char) * (binary)->in_frame_info.res.height * \
112 (binary)->in_frame_info.padded_width)
116 #define SCTBL_BYTES(binary) \
117 (sizeof(unsigned short) * (binary)->sctbl_height * \
118 (binary)->sctbl_aligned_width_per_color * IA_CSS_SC_NUM_COLORS)
122 #define SCTBL_BYTES(binary) \
123 (sizeof(unsigned short) * max((binary)->sctbl_height, (binary)->sctbl_legacy_height) * \
124 /* height should be the larger height between new api and legacy api */ \
125 (binary)->sctbl_aligned_width_per_color * IA_CSS_SC_NUM_COLORS)
129 #define MORPH_PLANE_BYTES(binary) \
130 (SH_CSS_MORPH_TABLE_ELEM_BYTES * (binary)->morph_tbl_aligned_width * \
131 (binary)->morph_tbl_height)
133 /* We keep a second copy of the ptr struct for the SP to access.
134 Again, this would not be necessary on the chip. */
135 static hrt_vaddress sp_ddr_ptrs;
137 /* sp group address on DDR */
138 static hrt_vaddress xmem_sp_group_ptrs;
140 static hrt_vaddress xmem_sp_stage_ptrs[IA_CSS_PIPE_ID_NUM]
142 static hrt_vaddress xmem_isp_stage_ptrs[IA_CSS_PIPE_ID_NUM]
145 static hrt_vaddress default_gdc_lut;
146 static int interleaved_lut_temp[4][HRT_GDC_N];
148 /* END DO NOT MOVE INTO VIMALS_WORLD */
150 /* Digital Zoom lookup table. See documentation for more details about the
151 * contents of this table.
153 #if defined(HAS_GDC_VERSION_2)
154 #if defined(CONFIG_CSI2_PLUS)
157 * Css_Mizuchi/regressions/20140424_0930/all/applications/common/gdc_v2_common/lut.h
160 static const int zoom_table[4][HRT_GDC_N] = {
161 { 0, 0, 0, 0, 0, 0, 0, 0,
162 0, 0, 0, 0, 0, 0, 0, 0,
163 0, 0, 0, 0, 0, 0, 0, -1,
164 -1, -1, -1, -1, -1, -1, -1, -1,
165 -1, -2, -2, -2, -2, -2, -2, -2,
166 -3, -3, -3, -3, -3, -3, -3, -4,
167 -4, -4, -4, -4, -5, -5, -5, -5,
168 -5, -5, -6, -6, -6, -6, -7, -7,
169 -7, -7, -7, -8, -8, -8, -8, -9,
170 -9, -9, -9, -10, -10, -10, -10, -11,
171 -11, -11, -12, -12, -12, -12, -13, -13,
172 -13, -14, -14, -14, -15, -15, -15, -15,
173 -16, -16, -16, -17, -17, -17, -18, -18,
174 -18, -19, -19, -20, -20, -20, -21, -21,
175 -21, -22, -22, -22, -23, -23, -24, -24,
176 -24, -25, -25, -25, -26, -26, -27, -27,
177 -28, -28, -28, -29, -29, -30, -30, -30,
178 -31, -31, -32, -32, -33, -33, -33, -34,
179 -34, -35, -35, -36, -36, -37, -37, -37,
180 -38, -38, -39, -39, -40, -40, -41, -41,
181 -42, -42, -43, -43, -44, -44, -45, -45,
182 -46, -46, -47, -47, -48, -48, -49, -49,
183 -50, -50, -51, -51, -52, -52, -53, -53,
184 -54, -54, -55, -55, -56, -56, -57, -57,
185 -58, -59, -59, -60, -60, -61, -61, -62,
186 -62, -63, -63, -64, -65, -65, -66, -66,
187 -67, -67, -68, -69, -69, -70, -70, -71,
188 -71, -72, -73, -73, -74, -74, -75, -75,
189 -76, -77, -77, -78, -78, -79, -80, -80,
190 -81, -81, -82, -83, -83, -84, -84, -85,
191 -86, -86, -87, -87, -88, -89, -89, -90,
192 -91, -91, -92, -92, -93, -94, -94, -95,
193 -96, -96, -97, -97, -98, -99, -99, -100,
194 -101, -101, -102, -102, -103, -104, -104, -105,
195 -106, -106, -107, -108, -108, -109, -109, -110,
196 -111, -111, -112, -113, -113, -114, -115, -115,
197 -116, -117, -117, -118, -119, -119, -120, -121,
198 -121, -122, -122, -123, -124, -124, -125, -126,
199 -126, -127, -128, -128, -129, -130, -130, -131,
200 -132, -132, -133, -134, -134, -135, -136, -136,
201 -137, -138, -138, -139, -140, -140, -141, -142,
202 -142, -143, -144, -144, -145, -146, -146, -147,
203 -148, -148, -149, -150, -150, -151, -152, -152,
204 -153, -154, -154, -155, -156, -156, -157, -158,
205 -158, -159, -160, -160, -161, -162, -162, -163,
206 -164, -164, -165, -166, -166, -167, -168, -168,
207 -169, -170, -170, -171, -172, -172, -173, -174,
208 -174, -175, -176, -176, -177, -178, -178, -179,
209 -180, -180, -181, -181, -182, -183, -183, -184,
210 -185, -185, -186, -187, -187, -188, -189, -189,
211 -190, -191, -191, -192, -193, -193, -194, -194,
212 -195, -196, -196, -197, -198, -198, -199, -200,
213 -200, -201, -201, -202, -203, -203, -204, -205,
214 -205, -206, -206, -207, -208, -208, -209, -210,
215 -210, -211, -211, -212, -213, -213, -214, -215,
216 -215, -216, -216, -217, -218, -218, -219, -219,
217 -220, -221, -221, -222, -222, -223, -224, -224,
218 -225, -225, -226, -227, -227, -228, -228, -229,
219 -229, -230, -231, -231, -232, -232, -233, -233,
220 -234, -235, -235, -236, -236, -237, -237, -238,
221 -239, -239, -240, -240, -241, -241, -242, -242,
222 -243, -244, -244, -245, -245, -246, -246, -247,
223 -247, -248, -248, -249, -249, -250, -250, -251,
224 -251, -252, -252, -253, -253, -254, -254, -255,
225 -256, -256, -256, -257, -257, -258, -258, -259,
226 -259, -260, -260, -261, -261, -262, -262, -263,
227 -263, -264, -264, -265, -265, -266, -266, -266,
228 -267, -267, -268, -268, -269, -269, -270, -270,
229 -270, -271, -271, -272, -272, -273, -273, -273,
230 -274, -274, -275, -275, -275, -276, -276, -277,
231 -277, -277, -278, -278, -279, -279, -279, -280,
232 -280, -280, -281, -281, -282, -282, -282, -283,
233 -283, -283, -284, -284, -284, -285, -285, -285,
234 -286, -286, -286, -287, -287, -287, -288, -288,
235 -288, -289, -289, -289, -289, -290, -290, -290,
236 -291, -291, -291, -291, -292, -292, -292, -293,
237 -293, -293, -293, -294, -294, -294, -294, -295,
238 -295, -295, -295, -295, -296, -296, -296, -296,
239 -297, -297, -297, -297, -297, -298, -298, -298,
240 -298, -298, -299, -299, -299, -299, -299, -299,
241 -300, -300, -300, -300, -300, -300, -300, -301,
242 -301, -301, -301, -301, -301, -301, -301, -301,
243 -302, -302, -302, -302, -302, -302, -302, -302,
244 -302, -302, -302, -302, -302, -303, -303, -303,
245 -303, -303, -303, -303, -303, -303, -303, -303,
246 -303, -303, -303, -303, -303, -303, -303, -303,
247 -303, -303, -303, -303, -303, -303, -303, -303,
248 -303, -303, -302, -302, -302, -302, -302, -302,
249 -302, -302, -302, -302, -302, -302, -301, -301,
250 -301, -301, -301, -301, -301, -301, -300, -300,
251 -300, -300, -300, -300, -299, -299, -299, -299,
252 -299, -299, -298, -298, -298, -298, -298, -297,
253 -297, -297, -297, -296, -296, -296, -296, -295,
254 -295, -295, -295, -294, -294, -294, -293, -293,
255 -293, -293, -292, -292, -292, -291, -291, -291,
256 -290, -290, -290, -289, -289, -289, -288, -288,
257 -288, -287, -287, -286, -286, -286, -285, -285,
258 -284, -284, -284, -283, -283, -282, -282, -281,
259 -281, -280, -280, -279, -279, -279, -278, -278,
260 -277, -277, -276, -276, -275, -275, -274, -273,
261 -273, -272, -272, -271, -271, -270, -270, -269,
262 -268, -268, -267, -267, -266, -266, -265, -264,
263 -264, -263, -262, -262, -261, -260, -260, -259,
264 -259, -258, -257, -256, -256, -255, -254, -254,
265 -253, -252, -252, -251, -250, -249, -249, -248,
266 -247, -246, -246, -245, -244, -243, -242, -242,
267 -241, -240, -239, -238, -238, -237, -236, -235,
268 -234, -233, -233, -232, -231, -230, -229, -228,
269 -227, -226, -226, -225, -224, -223, -222, -221,
270 -220, -219, -218, -217, -216, -215, -214, -213,
271 -212, -211, -210, -209, -208, -207, -206, -205,
272 -204, -203, -202, -201, -200, -199, -198, -197,
273 -196, -194, -193, -192, -191, -190, -189, -188,
274 -187, -185, -184, -183, -182, -181, -180, -178,
275 -177, -176, -175, -174, -172, -171, -170, -169,
276 -167, -166, -165, -164, -162, -161, -160, -158,
277 -157, -156, -155, -153, -152, -151, -149, -148,
278 -147, -145, -144, -142, -141, -140, -138, -137,
279 -135, -134, -133, -131, -130, -128, -127, -125,
280 -124, -122, -121, -120, -118, -117, -115, -114,
281 -112, -110, -109, -107, -106, -104, -103, -101,
282 -100, -98, -96, -95, -93, -92, -90, -88,
283 -87, -85, -83, -82, -80, -78, -77, -75,
284 -73, -72, -70, -68, -67, -65, -63, -61,
285 -60, -58, -56, -54, -52, -51, -49, -47,
286 -45, -43, -42, -40, -38, -36, -34, -32,
287 -31, -29, -27, -25, -23, -21, -19, -17,
288 -15, -13, -11, -9, -7, -5, -3, -1
290 { 0, 2, 4, 6, 8, 10, 12, 14,
291 16, 18, 20, 22, 25, 27, 29, 31,
292 33, 36, 38, 40, 43, 45, 47, 50,
293 52, 54, 57, 59, 61, 64, 66, 69,
294 71, 74, 76, 79, 81, 84, 86, 89,
295 92, 94, 97, 99, 102, 105, 107, 110,
296 113, 116, 118, 121, 124, 127, 129, 132,
297 135, 138, 141, 144, 146, 149, 152, 155,
298 158, 161, 164, 167, 170, 173, 176, 179,
299 182, 185, 188, 191, 194, 197, 200, 203,
300 207, 210, 213, 216, 219, 222, 226, 229,
301 232, 235, 239, 242, 245, 248, 252, 255,
302 258, 262, 265, 269, 272, 275, 279, 282,
303 286, 289, 292, 296, 299, 303, 306, 310,
304 313, 317, 321, 324, 328, 331, 335, 338,
305 342, 346, 349, 353, 357, 360, 364, 368,
306 372, 375, 379, 383, 386, 390, 394, 398,
307 402, 405, 409, 413, 417, 421, 425, 429,
308 432, 436, 440, 444, 448, 452, 456, 460,
309 464, 468, 472, 476, 480, 484, 488, 492,
310 496, 500, 504, 508, 512, 516, 521, 525,
311 529, 533, 537, 541, 546, 550, 554, 558,
312 562, 567, 571, 575, 579, 584, 588, 592,
313 596, 601, 605, 609, 614, 618, 622, 627,
314 631, 635, 640, 644, 649, 653, 657, 662,
315 666, 671, 675, 680, 684, 689, 693, 698,
316 702, 707, 711, 716, 720, 725, 729, 734,
317 738, 743, 747, 752, 757, 761, 766, 771,
318 775, 780, 784, 789, 794, 798, 803, 808,
319 813, 817, 822, 827, 831, 836, 841, 846,
320 850, 855, 860, 865, 870, 874, 879, 884,
321 889, 894, 898, 903, 908, 913, 918, 923,
322 928, 932, 937, 942, 947, 952, 957, 962,
323 967, 972, 977, 982, 986, 991, 996, 1001,
324 1006, 1011, 1016, 1021, 1026, 1031, 1036, 1041,
325 1046, 1051, 1056, 1062, 1067, 1072, 1077, 1082,
326 1087, 1092, 1097, 1102, 1107, 1112, 1117, 1122,
327 1128, 1133, 1138, 1143, 1148, 1153, 1158, 1164,
328 1169, 1174, 1179, 1184, 1189, 1195, 1200, 1205,
329 1210, 1215, 1221, 1226, 1231, 1236, 1242, 1247,
330 1252, 1257, 1262, 1268, 1273, 1278, 1284, 1289,
331 1294, 1299, 1305, 1310, 1315, 1321, 1326, 1331,
332 1336, 1342, 1347, 1352, 1358, 1363, 1368, 1374,
333 1379, 1384, 1390, 1395, 1400, 1406, 1411, 1417,
334 1422, 1427, 1433, 1438, 1443, 1449, 1454, 1460,
335 1465, 1470, 1476, 1481, 1487, 1492, 1497, 1503,
336 1508, 1514, 1519, 1525, 1530, 1535, 1541, 1546,
337 1552, 1557, 1563, 1568, 1574, 1579, 1585, 1590,
338 1596, 1601, 1606, 1612, 1617, 1623, 1628, 1634,
339 1639, 1645, 1650, 1656, 1661, 1667, 1672, 1678,
340 1683, 1689, 1694, 1700, 1705, 1711, 1716, 1722,
341 1727, 1733, 1738, 1744, 1749, 1755, 1761, 1766,
342 1772, 1777, 1783, 1788, 1794, 1799, 1805, 1810,
343 1816, 1821, 1827, 1832, 1838, 1844, 1849, 1855,
344 1860, 1866, 1871, 1877, 1882, 1888, 1893, 1899,
345 1905, 1910, 1916, 1921, 1927, 1932, 1938, 1943,
346 1949, 1955, 1960, 1966, 1971, 1977, 1982, 1988,
347 1993, 1999, 2005, 2010, 2016, 2021, 2027, 2032,
348 2038, 2043, 2049, 2055, 2060, 2066, 2071, 2077,
349 2082, 2088, 2093, 2099, 2105, 2110, 2116, 2121,
350 2127, 2132, 2138, 2143, 2149, 2154, 2160, 2165,
351 2171, 2177, 2182, 2188, 2193, 2199, 2204, 2210,
352 2215, 2221, 2226, 2232, 2237, 2243, 2248, 2254,
353 2259, 2265, 2270, 2276, 2281, 2287, 2292, 2298,
354 2304, 2309, 2314, 2320, 2325, 2331, 2336, 2342,
355 2347, 2353, 2358, 2364, 2369, 2375, 2380, 2386,
356 2391, 2397, 2402, 2408, 2413, 2419, 2424, 2429,
357 2435, 2440, 2446, 2451, 2457, 2462, 2467, 2473,
358 2478, 2484, 2489, 2495, 2500, 2505, 2511, 2516,
359 2522, 2527, 2532, 2538, 2543, 2549, 2554, 2559,
360 2565, 2570, 2575, 2581, 2586, 2591, 2597, 2602,
361 2607, 2613, 2618, 2623, 2629, 2634, 2639, 2645,
362 2650, 2655, 2661, 2666, 2671, 2676, 2682, 2687,
363 2692, 2698, 2703, 2708, 2713, 2719, 2724, 2729,
364 2734, 2740, 2745, 2750, 2755, 2760, 2766, 2771,
365 2776, 2781, 2786, 2792, 2797, 2802, 2807, 2812,
366 2817, 2823, 2828, 2833, 2838, 2843, 2848, 2853,
367 2859, 2864, 2869, 2874, 2879, 2884, 2889, 2894,
368 2899, 2904, 2909, 2914, 2919, 2924, 2930, 2935,
369 2940, 2945, 2950, 2955, 2960, 2965, 2970, 2975,
370 2980, 2984, 2989, 2994, 2999, 3004, 3009, 3014,
371 3019, 3024, 3029, 3034, 3039, 3044, 3048, 3053,
372 3058, 3063, 3068, 3073, 3078, 3082, 3087, 3092,
373 3097, 3102, 3106, 3111, 3116, 3121, 3126, 3130,
374 3135, 3140, 3145, 3149, 3154, 3159, 3163, 3168,
375 3173, 3177, 3182, 3187, 3191, 3196, 3201, 3205,
376 3210, 3215, 3219, 3224, 3228, 3233, 3238, 3242,
377 3247, 3251, 3256, 3260, 3265, 3269, 3274, 3279,
378 3283, 3287, 3292, 3296, 3301, 3305, 3310, 3314,
379 3319, 3323, 3327, 3332, 3336, 3341, 3345, 3349,
380 3354, 3358, 3362, 3367, 3371, 3375, 3380, 3384,
381 3388, 3393, 3397, 3401, 3405, 3410, 3414, 3418,
382 3422, 3426, 3431, 3435, 3439, 3443, 3447, 3451,
383 3455, 3460, 3464, 3468, 3472, 3476, 3480, 3484,
384 3488, 3492, 3496, 3500, 3504, 3508, 3512, 3516,
385 3520, 3524, 3528, 3532, 3536, 3540, 3544, 3548,
386 3552, 3555, 3559, 3563, 3567, 3571, 3575, 3578,
387 3582, 3586, 3590, 3593, 3597, 3601, 3605, 3608,
388 3612, 3616, 3619, 3623, 3627, 3630, 3634, 3638,
389 3641, 3645, 3649, 3652, 3656, 3659, 3663, 3666,
390 3670, 3673, 3677, 3680, 3684, 3687, 3691, 3694,
391 3698, 3701, 3704, 3708, 3711, 3714, 3718, 3721,
392 3724, 3728, 3731, 3734, 3738, 3741, 3744, 3747,
393 3751, 3754, 3757, 3760, 3763, 3767, 3770, 3773,
394 3776, 3779, 3782, 3785, 3788, 3791, 3794, 3798,
395 3801, 3804, 3807, 3809, 3812, 3815, 3818, 3821,
396 3824, 3827, 3830, 3833, 3836, 3839, 3841, 3844,
397 3847, 3850, 3853, 3855, 3858, 3861, 3864, 3866,
398 3869, 3872, 3874, 3877, 3880, 3882, 3885, 3887,
399 3890, 3893, 3895, 3898, 3900, 3903, 3905, 3908,
400 3910, 3913, 3915, 3917, 3920, 3922, 3925, 3927,
401 3929, 3932, 3934, 3936, 3939, 3941, 3943, 3945,
402 3948, 3950, 3952, 3954, 3956, 3958, 3961, 3963,
403 3965, 3967, 3969, 3971, 3973, 3975, 3977, 3979,
404 3981, 3983, 3985, 3987, 3989, 3991, 3993, 3994,
405 3996, 3998, 4000, 4002, 4004, 4005, 4007, 4009,
406 4011, 4012, 4014, 4016, 4017, 4019, 4021, 4022,
407 4024, 4025, 4027, 4028, 4030, 4031, 4033, 4034,
408 4036, 4037, 4039, 4040, 4042, 4043, 4044, 4046,
409 4047, 4048, 4050, 4051, 4052, 4053, 4055, 4056,
410 4057, 4058, 4059, 4060, 4062, 4063, 4064, 4065,
411 4066, 4067, 4068, 4069, 4070, 4071, 4072, 4073,
412 4074, 4075, 4075, 4076, 4077, 4078, 4079, 4079,
413 4080, 4081, 4082, 4082, 4083, 4084, 4084, 4085,
414 4086, 4086, 4087, 4087, 4088, 4088, 4089, 4089,
415 4090, 4090, 4091, 4091, 4092, 4092, 4092, 4093,
416 4093, 4093, 4094, 4094, 4094, 4094, 4095, 4095,
417 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095
419 { 4096, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
420 4095, 4095, 4095, 4094, 4094, 4094, 4094, 4093,
421 4093, 4093, 4092, 4092, 4092, 4091, 4091, 4090,
422 4090, 4089, 4089, 4088, 4088, 4087, 4087, 4086,
423 4086, 4085, 4084, 4084, 4083, 4082, 4082, 4081,
424 4080, 4079, 4079, 4078, 4077, 4076, 4075, 4075,
425 4074, 4073, 4072, 4071, 4070, 4069, 4068, 4067,
426 4066, 4065, 4064, 4063, 4062, 4060, 4059, 4058,
427 4057, 4056, 4055, 4053, 4052, 4051, 4050, 4048,
428 4047, 4046, 4044, 4043, 4042, 4040, 4039, 4037,
429 4036, 4034, 4033, 4031, 4030, 4028, 4027, 4025,
430 4024, 4022, 4021, 4019, 4017, 4016, 4014, 4012,
431 4011, 4009, 4007, 4005, 4004, 4002, 4000, 3998,
432 3996, 3994, 3993, 3991, 3989, 3987, 3985, 3983,
433 3981, 3979, 3977, 3975, 3973, 3971, 3969, 3967,
434 3965, 3963, 3961, 3958, 3956, 3954, 3952, 3950,
435 3948, 3945, 3943, 3941, 3939, 3936, 3934, 3932,
436 3929, 3927, 3925, 3922, 3920, 3917, 3915, 3913,
437 3910, 3908, 3905, 3903, 3900, 3898, 3895, 3893,
438 3890, 3887, 3885, 3882, 3880, 3877, 3874, 3872,
439 3869, 3866, 3864, 3861, 3858, 3855, 3853, 3850,
440 3847, 3844, 3841, 3839, 3836, 3833, 3830, 3827,
441 3824, 3821, 3818, 3815, 3812, 3809, 3807, 3804,
442 3801, 3798, 3794, 3791, 3788, 3785, 3782, 3779,
443 3776, 3773, 3770, 3767, 3763, 3760, 3757, 3754,
444 3751, 3747, 3744, 3741, 3738, 3734, 3731, 3728,
445 3724, 3721, 3718, 3714, 3711, 3708, 3704, 3701,
446 3698, 3694, 3691, 3687, 3684, 3680, 3677, 3673,
447 3670, 3666, 3663, 3659, 3656, 3652, 3649, 3645,
448 3641, 3638, 3634, 3630, 3627, 3623, 3619, 3616,
449 3612, 3608, 3605, 3601, 3597, 3593, 3590, 3586,
450 3582, 3578, 3575, 3571, 3567, 3563, 3559, 3555,
451 3552, 3548, 3544, 3540, 3536, 3532, 3528, 3524,
452 3520, 3516, 3512, 3508, 3504, 3500, 3496, 3492,
453 3488, 3484, 3480, 3476, 3472, 3468, 3464, 3460,
454 3455, 3451, 3447, 3443, 3439, 3435, 3431, 3426,
455 3422, 3418, 3414, 3410, 3405, 3401, 3397, 3393,
456 3388, 3384, 3380, 3375, 3371, 3367, 3362, 3358,
457 3354, 3349, 3345, 3341, 3336, 3332, 3327, 3323,
458 3319, 3314, 3310, 3305, 3301, 3296, 3292, 3287,
459 3283, 3279, 3274, 3269, 3265, 3260, 3256, 3251,
460 3247, 3242, 3238, 3233, 3228, 3224, 3219, 3215,
461 3210, 3205, 3201, 3196, 3191, 3187, 3182, 3177,
462 3173, 3168, 3163, 3159, 3154, 3149, 3145, 3140,
463 3135, 3130, 3126, 3121, 3116, 3111, 3106, 3102,
464 3097, 3092, 3087, 3082, 3078, 3073, 3068, 3063,
465 3058, 3053, 3048, 3044, 3039, 3034, 3029, 3024,
466 3019, 3014, 3009, 3004, 2999, 2994, 2989, 2984,
467 2980, 2975, 2970, 2965, 2960, 2955, 2950, 2945,
468 2940, 2935, 2930, 2924, 2919, 2914, 2909, 2904,
469 2899, 2894, 2889, 2884, 2879, 2874, 2869, 2864,
470 2859, 2853, 2848, 2843, 2838, 2833, 2828, 2823,
471 2817, 2812, 2807, 2802, 2797, 2792, 2786, 2781,
472 2776, 2771, 2766, 2760, 2755, 2750, 2745, 2740,
473 2734, 2729, 2724, 2719, 2713, 2708, 2703, 2698,
474 2692, 2687, 2682, 2676, 2671, 2666, 2661, 2655,
475 2650, 2645, 2639, 2634, 2629, 2623, 2618, 2613,
476 2607, 2602, 2597, 2591, 2586, 2581, 2575, 2570,
477 2565, 2559, 2554, 2549, 2543, 2538, 2532, 2527,
478 2522, 2516, 2511, 2505, 2500, 2495, 2489, 2484,
479 2478, 2473, 2467, 2462, 2457, 2451, 2446, 2440,
480 2435, 2429, 2424, 2419, 2413, 2408, 2402, 2397,
481 2391, 2386, 2380, 2375, 2369, 2364, 2358, 2353,
482 2347, 2342, 2336, 2331, 2325, 2320, 2314, 2309,
483 2304, 2298, 2292, 2287, 2281, 2276, 2270, 2265,
484 2259, 2254, 2248, 2243, 2237, 2232, 2226, 2221,
485 2215, 2210, 2204, 2199, 2193, 2188, 2182, 2177,
486 2171, 2165, 2160, 2154, 2149, 2143, 2138, 2132,
487 2127, 2121, 2116, 2110, 2105, 2099, 2093, 2088,
488 2082, 2077, 2071, 2066, 2060, 2055, 2049, 2043,
489 2038, 2032, 2027, 2021, 2016, 2010, 2005, 1999,
490 1993, 1988, 1982, 1977, 1971, 1966, 1960, 1955,
491 1949, 1943, 1938, 1932, 1927, 1921, 1916, 1910,
492 1905, 1899, 1893, 1888, 1882, 1877, 1871, 1866,
493 1860, 1855, 1849, 1844, 1838, 1832, 1827, 1821,
494 1816, 1810, 1805, 1799, 1794, 1788, 1783, 1777,
495 1772, 1766, 1761, 1755, 1749, 1744, 1738, 1733,
496 1727, 1722, 1716, 1711, 1705, 1700, 1694, 1689,
497 1683, 1678, 1672, 1667, 1661, 1656, 1650, 1645,
498 1639, 1634, 1628, 1623, 1617, 1612, 1606, 1601,
499 1596, 1590, 1585, 1579, 1574, 1568, 1563, 1557,
500 1552, 1546, 1541, 1535, 1530, 1525, 1519, 1514,
501 1508, 1503, 1497, 1492, 1487, 1481, 1476, 1470,
502 1465, 1460, 1454, 1449, 1443, 1438, 1433, 1427,
503 1422, 1417, 1411, 1406, 1400, 1395, 1390, 1384,
504 1379, 1374, 1368, 1363, 1358, 1352, 1347, 1342,
505 1336, 1331, 1326, 1321, 1315, 1310, 1305, 1299,
506 1294, 1289, 1284, 1278, 1273, 1268, 1262, 1257,
507 1252, 1247, 1242, 1236, 1231, 1226, 1221, 1215,
508 1210, 1205, 1200, 1195, 1189, 1184, 1179, 1174,
509 1169, 1164, 1158, 1153, 1148, 1143, 1138, 1133,
510 1128, 1122, 1117, 1112, 1107, 1102, 1097, 1092,
511 1087, 1082, 1077, 1072, 1067, 1062, 1056, 1051,
512 1046, 1041, 1036, 1031, 1026, 1021, 1016, 1011,
513 1006, 1001, 996, 991, 986, 982, 977, 972,
514 967, 962, 957, 952, 947, 942, 937, 932,
515 928, 923, 918, 913, 908, 903, 898, 894,
516 889, 884, 879, 874, 870, 865, 860, 855,
517 850, 846, 841, 836, 831, 827, 822, 817,
518 813, 808, 803, 798, 794, 789, 784, 780,
519 775, 771, 766, 761, 757, 752, 747, 743,
520 738, 734, 729, 725, 720, 716, 711, 707,
521 702, 698, 693, 689, 684, 680, 675, 671,
522 666, 662, 657, 653, 649, 644, 640, 635,
523 631, 627, 622, 618, 614, 609, 605, 601,
524 596, 592, 588, 584, 579, 575, 571, 567,
525 562, 558, 554, 550, 546, 541, 537, 533,
526 529, 525, 521, 516, 512, 508, 504, 500,
527 496, 492, 488, 484, 480, 476, 472, 468,
528 464, 460, 456, 452, 448, 444, 440, 436,
529 432, 429, 425, 421, 417, 413, 409, 405,
530 402, 398, 394, 390, 386, 383, 379, 375,
531 372, 368, 364, 360, 357, 353, 349, 346,
532 342, 338, 335, 331, 328, 324, 321, 317,
533 313, 310, 306, 303, 299, 296, 292, 289,
534 286, 282, 279, 275, 272, 269, 265, 262,
535 258, 255, 252, 248, 245, 242, 239, 235,
536 232, 229, 226, 222, 219, 216, 213, 210,
537 207, 203, 200, 197, 194, 191, 188, 185,
538 182, 179, 176, 173, 170, 167, 164, 161,
539 158, 155, 152, 149, 146, 144, 141, 138,
540 135, 132, 129, 127, 124, 121, 118, 116,
541 113, 110, 107, 105, 102, 99, 97, 94,
542 92, 89, 86, 84, 81, 79, 76, 74,
543 71, 69, 66, 64, 61, 59, 57, 54,
544 52, 50, 47, 45, 43, 40, 38, 36,
545 33, 31, 29, 27, 25, 22, 20, 18,
546 16, 14, 12, 10, 8, 6, 4, 2
548 { 0, -1, -3, -5, -7, -9, -11, -13,
549 -15, -17, -19, -20, -23, -25, -27, -28,
550 -30, -33, -34, -36, -39, -40, -42, -43,
551 -45, -46, -49, -50, -52, -54, -56, -58,
552 -60, -61, -62, -65, -66, -68, -70, -72,
553 -73, -74, -77, -78, -80, -82, -83, -85,
554 -87, -89, -90, -92, -93, -95, -96, -98,
555 -100, -102, -103, -105, -106, -107, -108, -110,
556 -112, -114, -116, -116, -118, -120, -122, -122,
557 -124, -126, -127, -128, -130, -131, -133, -133,
558 -136, -137, -138, -139, -141, -142, -144, -145,
559 -147, -147, -150, -151, -151, -153, -155, -156,
560 -157, -159, -160, -161, -163, -164, -165, -166,
561 -168, -168, -170, -171, -172, -174, -174, -176,
562 -177, -178, -180, -181, -182, -183, -184, -185,
563 -187, -188, -189, -190, -191, -192, -193, -195,
564 -196, -196, -198, -199, -200, -200, -202, -204,
565 -204, -205, -206, -207, -208, -209, -211, -212,
566 -212, -213, -214, -215, -216, -217, -218, -220,
567 -220, -221, -222, -223, -224, -225, -225, -227,
568 -227, -228, -229, -230, -230, -231, -233, -234,
569 -234, -235, -235, -237, -238, -239, -239, -240,
570 -240, -242, -242, -243, -243, -245, -246, -247,
571 -247, -249, -248, -249, -250, -251, -251, -253,
572 -253, -253, -255, -255, -256, -256, -257, -258,
573 -259, -259, -260, -261, -261, -262, -262, -264,
574 -263, -265, -265, -265, -266, -267, -267, -268,
575 -269, -269, -269, -270, -271, -271, -272, -273,
576 -273, -273, -274, -274, -276, -275, -276, -277,
577 -277, -278, -278, -278, -279, -279, -280, -281,
578 -280, -281, -282, -283, -283, -282, -284, -284,
579 -284, -285, -285, -286, -286, -286, -287, -287,
580 -288, -288, -288, -289, -289, -289, -290, -290,
581 -290, -291, -291, -292, -291, -291, -292, -292,
582 -292, -293, -293, -293, -294, -294, -295, -295,
583 -294, -295, -295, -296, -297, -297, -297, -297,
584 -297, -297, -298, -298, -297, -298, -298, -298,
585 -299, -299, -300, -299, -299, -300, -299, -300,
586 -301, -300, -300, -301, -300, -301, -301, -301,
587 -301, -301, -302, -301, -302, -301, -302, -302,
588 -302, -302, -302, -302, -302, -302, -303, -302,
589 -303, -302, -303, -303, -302, -303, -303, -303,
590 -302, -303, -303, -302, -303, -303, -302, -303,
591 -303, -302, -303, -303, -302, -303, -303, -303,
592 -303, -302, -303, -303, -302, -302, -302, -303,
593 -302, -302, -302, -301, -303, -302, -301, -302,
594 -301, -301, -301, -302, -301, -301, -301, -300,
595 -301, -300, -300, -300, -300, -299, -300, -299,
596 -300, -300, -299, -300, -299, -299, -299, -299,
597 -298, -299, -298, -297, -297, -297, -296, -297,
598 -296, -296, -296, -296, -295, -296, -295, -296,
599 -295, -294, -294, -294, -293, -294, -294, -293,
600 -293, -292, -293, -292, -292, -292, -291, -290,
601 -291, -290, -291, -289, -289, -290, -289, -289,
602 -288, -288, -288, -288, -286, -287, -286, -286,
603 -286, -285, -286, -284, -284, -284, -284, -283,
604 -283, -283, -282, -282, -282, -281, -280, -281,
605 -279, -280, -280, -278, -279, -278, -278, -277,
606 -278, -276, -276, -277, -275, -276, -274, -275,
607 -274, -273, -273, -272, -273, -272, -272, -271,
608 -270, -270, -269, -269, -269, -268, -268, -267,
609 -267, -266, -266, -266, -265, -265, -264, -264,
610 -263, -263, -262, -262, -261, -261, -260, -260,
611 -259, -259, -258, -258, -257, -257, -256, -256,
612 -256, -255, -254, -254, -253, -253, -252, -252,
613 -251, -251, -250, -250, -249, -249, -248, -248,
614 -247, -247, -246, -246, -245, -245, -244, -244,
615 -243, -242, -242, -241, -241, -240, -239, -239,
616 -239, -238, -238, -237, -237, -235, -235, -235,
617 -234, -234, -232, -233, -232, -232, -231, -229,
618 -230, -229, -228, -228, -227, -226, -227, -225,
619 -224, -225, -223, -223, -222, -222, -221, -221,
620 -220, -219, -219, -218, -218, -216, -217, -216,
621 -215, -215, -214, -213, -212, -213, -211, -211,
622 -210, -210, -209, -209, -208, -206, -207, -206,
623 -205, -204, -204, -204, -203, -202, -202, -200,
624 -200, -200, -200, -198, -197, -197, -196, -195,
625 -195, -195, -194, -194, -192, -192, -191, -191,
626 -189, -189, -188, -188, -187, -186, -186, -186,
627 -185, -185, -183, -183, -182, -182, -181, -181,
628 -180, -178, -178, -177, -177, -176, -176, -174,
629 -174, -173, -173, -172, -172, -172, -170, -170,
630 -168, -168, -167, -167, -167, -165, -165, -164,
631 -164, -164, -162, -162, -161, -160, -160, -158,
632 -158, -158, -157, -156, -155, -155, -154, -153,
633 -153, -152, -151, -151, -150, -149, -149, -148,
634 -147, -147, -146, -146, -144, -144, -144, -142,
635 -142, -141, -142, -140, -140, -139, -138, -138,
636 -137, -136, -136, -134, -134, -133, -134, -132,
637 -132, -131, -130, -130, -128, -128, -128, -127,
638 -127, -126, -124, -124, -124, -123, -123, -122,
639 -121, -120, -120, -119, -118, -118, -117, -117,
640 -116, -115, -115, -115, -114, -113, -111, -111,
641 -110, -110, -109, -109, -108, -107, -107, -106,
642 -105, -104, -104, -103, -102, -103, -102, -101,
643 -101, -100, -99, -99, -98, -97, -97, -96,
644 -96, -95, -94, -94, -93, -92, -92, -91,
645 -91, -90, -89, -88, -88, -88, -87, -86,
646 -85, -86, -84, -84, -83, -82, -82, -81,
647 -81, -80, -80, -78, -79, -77, -77, -77,
648 -76, -76, -75, -74, -74, -73, -72, -72,
649 -72, -71, -70, -70, -69, -68, -68, -68,
650 -66, -67, -66, -65, -65, -65, -63, -63,
651 -62, -62, -61, -61, -60, -60, -60, -58,
652 -58, -58, -56, -56, -56, -55, -54, -55,
653 -54, -54, -53, -52, -51, -51, -51, -50,
654 -49, -49, -49, -49, -48, -47, -46, -46,
655 -46, -46, -45, -43, -43, -43, -43, -42,
656 -42, -42, -40, -40, -40, -39, -39, -38,
657 -38, -38, -37, -37, -36, -36, -35, -35,
658 -34, -35, -34, -33, -33, -32, -32, -31,
659 -31, -31, -30, -29, -29, -29, -28, -27,
660 -28, -28, -27, -26, -26, -25, -25, -25,
661 -24, -24, -24, -23, -23, -22, -22, -22,
662 -21, -21, -20, -20, -20, -20, -19, -18,
663 -19, -18, -18, -17, -18, -17, -16, -17,
664 -16, -15, -15, -15, -14, -14, -15, -13,
665 -13, -13, -13, -12, -12, -11, -12, -11,
666 -12, -10, -10, -10, -10, -10, -9, -10,
667 -9, -9, -9, -8, -8, -7, -8, -7,
668 -7, -7, -6, -6, -6, -7, -6, -6,
669 -5, -5, -5, -5, -5, -4, -4, -5,
670 -4, -4, -3, -3, -3, -3, -3, -2,
671 -3, -2, -2, -2, -1, -2, -1, -2,
672 -1, -1, -1, -1, -1, 0, -1, 0,
673 -1, -1, 0, 0, -1, 0, 0, -1,
674 1, 1, 0, 0, 0, 1, 0, 0,
675 0, 0, 0, 0, 0, 0, 0, 0
678 #else /* defined(CONFIG_CSI2_PLUS) */
679 static const int zoom_table[4][HRT_GDC_N] = {
680 { 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
681 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
682 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
683 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
684 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
685 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
686 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
687 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
688 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
689 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
690 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
691 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
692 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
693 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
694 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
695 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
696 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
697 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
698 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
699 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
700 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
701 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
702 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
703 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
704 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
705 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
706 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
707 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
708 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
709 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
710 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
711 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
712 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
713 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
714 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
715 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
716 -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
717 -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
718 -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
719 -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
720 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
721 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
722 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
723 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
724 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
725 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
726 -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
727 -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
728 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
729 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
730 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
731 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
732 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
733 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
734 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
735 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
736 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
737 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
738 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
739 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
740 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
741 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
742 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
743 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
744 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
745 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
746 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
747 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
748 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
749 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
750 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
751 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
752 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
753 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
754 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
755 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
756 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
757 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
758 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
759 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
760 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
761 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
762 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
763 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
764 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
765 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
766 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
767 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
768 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
769 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
770 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
771 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
772 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
773 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
774 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
775 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
776 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
777 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
778 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
779 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
780 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
781 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
782 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
783 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
784 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
785 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
786 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
787 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
788 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
789 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
790 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
791 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
792 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
793 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
794 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
795 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
796 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
797 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
798 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
799 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
800 -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
801 -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
802 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
803 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
804 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
805 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
806 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
807 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4
809 { 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
810 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
811 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4,
812 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4,
813 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
814 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
815 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
816 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
817 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
818 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
819 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
820 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
821 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
822 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
823 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
824 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
825 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
826 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
827 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
828 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
829 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
830 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
831 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
832 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
833 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
834 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
835 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
836 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
837 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
838 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
839 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
840 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
841 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
842 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
843 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
844 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
845 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
846 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
847 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
848 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
849 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
850 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
851 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
852 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
853 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
854 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
855 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
856 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
857 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
858 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
859 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
860 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
861 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
862 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
863 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
864 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
865 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
866 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
867 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
868 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
869 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
870 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
871 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
872 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
873 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
874 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
875 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
876 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
877 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
878 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
879 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
880 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
881 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
882 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
883 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
884 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
885 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
886 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
887 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
888 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
889 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
890 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
891 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
892 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
893 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
894 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
895 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
896 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
897 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
898 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
899 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
900 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
901 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
902 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
903 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
904 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
905 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
906 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
907 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
908 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
909 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
910 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
911 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
912 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
913 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
914 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
915 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
916 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
917 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
918 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
919 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
920 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
921 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
922 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
923 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
924 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
925 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
926 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
927 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
928 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
929 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
930 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
931 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
932 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
933 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
934 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
935 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
936 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4
938 { 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4,
939 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4,
940 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
941 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
942 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
943 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
944 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
945 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
946 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
947 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
948 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
949 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
950 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
951 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
952 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
953 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
954 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
955 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
956 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
957 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
958 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
959 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
960 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
961 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
962 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
963 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
964 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
965 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
966 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
967 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
968 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
969 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
970 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
971 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
972 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
973 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
974 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
975 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
976 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
977 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
978 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
979 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
980 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
981 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
982 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
983 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
984 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
985 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
986 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
987 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
988 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
989 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
990 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
991 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
992 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
993 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
994 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
995 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
996 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
997 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
998 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
999 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
1000 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
1001 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
1002 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
1003 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
1004 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
1005 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
1006 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
1007 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
1008 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
1009 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
1010 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
1011 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
1012 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
1013 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
1014 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
1015 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
1016 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
1017 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
1018 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
1019 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
1020 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
1021 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
1022 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
1023 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
1024 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
1025 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
1026 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
1027 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
1028 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
1029 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
1030 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
1031 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
1032 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
1033 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
1034 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
1035 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
1036 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
1037 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
1038 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
1039 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
1040 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
1041 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
1042 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
1043 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
1044 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
1045 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
1046 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
1047 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
1048 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
1049 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
1050 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
1051 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
1052 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
1053 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
1054 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
1055 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
1056 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
1057 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
1058 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
1059 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
1060 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
1061 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
1062 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
1063 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
1064 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4,
1065 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4
1067 { 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1068 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1069 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
1070 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
1071 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
1072 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
1073 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
1074 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
1075 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1076 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1077 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
1078 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
1079 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1080 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1081 -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
1082 -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
1083 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1084 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1085 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
1086 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
1087 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
1088 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
1089 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
1090 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
1091 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1092 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1093 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
1094 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
1095 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1096 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1097 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1098 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1099 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1100 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1101 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1102 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1103 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1104 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1105 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1106 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1107 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1108 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1109 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1110 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1111 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1112 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1113 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1114 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1115 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1116 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1117 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1118 -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
1119 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1120 -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
1121 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1122 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1123 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1124 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1125 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1126 -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
1127 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1128 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1129 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1130 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1131 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1132 -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
1133 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
1134 -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
1135 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
1136 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
1137 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
1138 -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
1139 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
1140 -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
1141 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1142 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1143 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1144 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1145 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1146 -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
1147 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
1148 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
1149 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
1150 -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
1151 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1152 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1153 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1154 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1155 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1156 -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
1157 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
1158 -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
1159 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1160 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1161 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1162 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1163 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1164 -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
1165 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
1166 -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
1167 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
1168 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
1169 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
1170 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
1171 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
1172 -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
1173 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
1174 -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
1175 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
1176 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
1177 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
1178 -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
1179 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
1180 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
1181 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1182 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1183 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
1184 -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
1185 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1186 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1187 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4,
1188 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4,
1189 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1190 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1191 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1192 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1193 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
1194 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4
1199 #error "sh_css_params.c: GDC version must be \
1200 one of {GDC_VERSION_2}"
1203 static const struct ia_css_dz_config default_dz_config = {
1212 static const struct ia_css_vector default_motion_config = {
1217 /* ------ deprecated(bz675) : from ------ */
1218 static const struct ia_css_shading_settings default_shading_settings = {
1219 1 /* enable shading table conversion in the css
1220 (This matches the legacy way.) */
1222 /* ------ deprecated(bz675) : to ------ */
1224 struct ia_css_isp_skc_dvs_statistics {
1228 static enum ia_css_err
1229 ref_sh_css_ddr_address_map(
1230 struct sh_css_ddr_address_map *map,
1231 struct sh_css_ddr_address_map *out);
1233 static enum ia_css_err
1234 write_ia_css_isp_parameter_set_info_to_ddr(
1235 struct ia_css_isp_parameter_set_info *me,
1238 static enum ia_css_err
1239 free_ia_css_isp_parameter_set_info(hrt_vaddress ptr);
1241 static enum ia_css_err
1242 sh_css_params_write_to_ddr_internal(
1243 struct ia_css_pipe *pipe,
1245 struct ia_css_isp_parameters *params,
1246 const struct ia_css_pipeline_stage *stage,
1247 struct sh_css_ddr_address_map *ddr_map,
1248 struct sh_css_ddr_address_map_size *ddr_map_size);
1250 static enum ia_css_err
1251 sh_css_create_isp_params(struct ia_css_stream *stream,
1252 struct ia_css_isp_parameters **isp_params_out);
1255 sh_css_init_isp_params_from_global(struct ia_css_stream *stream,
1256 struct ia_css_isp_parameters *params,
1257 bool use_default_config,
1258 struct ia_css_pipe *pipe_in);
1260 static enum ia_css_err
1261 sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe,
1262 struct ia_css_isp_parameters *params,
1263 const struct ia_css_isp_config *config,
1264 struct ia_css_pipe *pipe_in);
1266 static enum ia_css_err
1267 sh_css_set_global_isp_config_on_pipe(
1268 struct ia_css_pipe *curr_pipe,
1269 const struct ia_css_isp_config *config,
1270 struct ia_css_pipe *pipe);
1272 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
1273 static enum ia_css_err
1274 sh_css_set_per_frame_isp_config_on_pipe(
1275 struct ia_css_stream *stream,
1276 const struct ia_css_isp_config *config,
1277 struct ia_css_pipe *pipe);
1280 static enum ia_css_err
1281 sh_css_update_uds_and_crop_info_based_on_zoom_region(
1282 const struct ia_css_binary_info *info,
1283 const struct ia_css_frame_info *in_frame_info,
1284 const struct ia_css_frame_info *out_frame_info,
1285 const struct ia_css_resolution *dvs_env,
1286 const struct ia_css_dz_config *zoom,
1287 const struct ia_css_vector *motion_vector,
1288 struct sh_css_uds_info *uds, /* out */
1289 struct sh_css_crop_pos *sp_out_crop_pos, /* out */
1290 struct ia_css_resolution pipe_in_res,
1294 sh_css_params_ddr_address_map(void)
1299 /* ****************************************************
1300 * Each coefficient is stored as 7bits to fit 2 of them into one
1301 * ISP vector element, so we will store 4 coefficents on every
1302 * memory word (32bits)
1304 * 0: Coefficient 0 used bits
1305 * 1: Coefficient 1 used bits
1306 * 2: Coefficient 2 used bits
1307 * 3: Coefficient 3 used bits
1310 * xx33333332222222 | xx11111110000000
1312 * ***************************************************
1314 static struct ia_css_host_data *
1315 convert_allocate_fpntbl(struct ia_css_isp_parameters *params)
1319 struct ia_css_host_data *me;
1320 unsigned int isp_format_data_size;
1321 uint32_t *isp_format_data_ptr;
1323 assert(params != NULL);
1325 data_ptr = params->fpn_config.data;
1326 isp_format_data_size = params->fpn_config.height * params->fpn_config.width * sizeof(uint32_t);
1328 me = ia_css_host_data_allocate(isp_format_data_size);
1333 isp_format_data_ptr = (uint32_t *)me->address;
1335 for (i = 0; i < params->fpn_config.height; i++) {
1337 j < params->fpn_config.width;
1338 j += 4, data_ptr += 4, isp_format_data_ptr++) {
1339 int data = data_ptr[0] << 0 |
1343 *isp_format_data_ptr = data;
1349 static enum ia_css_err
1350 store_fpntbl(struct ia_css_isp_parameters *params, hrt_vaddress ptr)
1352 struct ia_css_host_data *isp_data;
1354 assert(params != NULL);
1355 assert(ptr != mmgr_NULL);
1357 isp_data = convert_allocate_fpntbl(params);
1359 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
1360 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
1362 ia_css_params_store_ia_css_host_data(ptr, isp_data);
1364 ia_css_host_data_free(isp_data);
1365 return IA_CSS_SUCCESS;
1369 convert_raw_to_fpn(struct ia_css_isp_parameters *params)
1374 assert(params != NULL);
1376 /* Find the maximum value in the table */
1377 for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++) {
1378 int val = params->fpn_config.data[i];
1379 /* Make sure FPN value can be represented in 13-bit unsigned
1380 * number (ISP precision - 1), but note that actual input range
1381 * depends on precision of input frame data.
1384 /* Checkpatch patch */
1386 } else if (val >= (1 << 13)) {
1387 /* Checkpatch patch */
1388 /* MW: BUG, is "13" a system or application property */
1389 val = (1 << 13) - 1;
1391 maxval = max(maxval, val);
1393 /* Find the lowest shift value to remap the values in the range
1394 * 0..maxval to 0..2^shiftval*63.
1396 params->fpn_config.shift = 0;
1397 while (maxval > 63) {
1398 /* MW: BUG, is "63" a system or application property */
1400 params->fpn_config.shift++;
1402 /* Adjust the values in the table for the shift value */
1403 for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++)
1404 ((unsigned short *) params->fpn_config.data)[i] >>= params->fpn_config.shift;
1408 ia_css_process_kernel(struct ia_css_stream *stream,
1409 struct ia_css_isp_parameters *params,
1410 void (*process)(unsigned pipe_id,
1411 const struct ia_css_pipeline_stage *stage,
1412 struct ia_css_isp_parameters *params))
1415 for (i = 0; i < stream->num_pipes; i++) {
1416 struct ia_css_pipe *pipe = stream->pipes[i];
1417 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe);
1418 struct ia_css_pipeline_stage *stage;
1420 /* update the other buffers to the pipe specific copies */
1421 for (stage = pipeline->stages; stage; stage = stage->next) {
1422 if (!stage || !stage->binary) continue;
1423 process(pipeline->pipe_id, stage, params);
1428 static enum ia_css_err
1429 sh_css_select_dp_10bpp_config(const struct ia_css_pipe *pipe, bool *is_dp_10bpp) {
1431 enum ia_css_err err = IA_CSS_SUCCESS;
1432 /* Currently we check if 10bpp DPC configuration is required based
1433 * on the use case,i.e. if BDS and DPC is both enabled. The more cleaner
1434 * design choice would be to expose the type of DPC (either 10bpp or 13bpp)
1435 * using the binary info, but the current control flow does not allow this
1436 * implementation. (This is because the configuration is set before a
1437 * binary is selected, and the binary info is not available)
1439 if((pipe == NULL) || (is_dp_10bpp == NULL)) {
1440 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
1441 err = IA_CSS_ERR_INTERNAL_ERROR;
1443 *is_dp_10bpp = false;
1445 /* check if DPC is enabled from the host */
1446 if (pipe->config.enable_dpc) {
1447 /*check if BDS is enabled*/
1448 unsigned int required_bds_factor = SH_CSS_BDS_FACTOR_1_00;
1449 if ((pipe->config.bayer_ds_out_res.width != 0) &&
1450 (pipe->config.bayer_ds_out_res.height != 0)) {
1451 if (IA_CSS_SUCCESS == binarydesc_calculate_bds_factor(
1452 pipe->config.input_effective_res,
1453 pipe->config.bayer_ds_out_res,
1454 &required_bds_factor)) {
1455 if (SH_CSS_BDS_FACTOR_1_00 != required_bds_factor) {
1456 /*we use 10bpp BDS configuration*/
1457 *is_dp_10bpp = true;
1468 sh_css_set_black_frame(struct ia_css_stream *stream,
1469 const struct ia_css_frame *raw_black_frame)
1471 struct ia_css_isp_parameters *params;
1472 /* this function desperately needs to be moved to the ISP or SP such
1473 * that it can use the DMA.
1475 unsigned int height, width, y, x, k, data;
1478 assert(stream != NULL);
1479 assert(raw_black_frame != NULL);
1481 params = stream->isp_params_configs;
1482 height = raw_black_frame->info.res.height;
1483 width = raw_black_frame->info.padded_width,
1485 ptr = raw_black_frame->data
1486 + raw_black_frame->planes.raw.offset;
1488 IA_CSS_ENTER_PRIVATE("black_frame=%p", raw_black_frame);
1490 if (params->fpn_config.data &&
1491 (params->fpn_config.width != width || params->fpn_config.height != height)) {
1492 sh_css_free(params->fpn_config.data);
1493 params->fpn_config.data = NULL;
1495 if (params->fpn_config.data == NULL) {
1496 params->fpn_config.data = sh_css_malloc(height * width * sizeof(short));
1497 if (!params->fpn_config.data) {
1498 IA_CSS_ERROR("out of memory");
1499 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
1500 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
1502 params->fpn_config.width = width;
1503 params->fpn_config.height = height;
1504 params->fpn_config.shift = 0;
1507 /* store raw to fpntbl */
1508 for (y = 0; y < height; y++) {
1509 for (x = 0; x < width; x += (ISP_VEC_NELEMS * 2)) {
1510 int ofs = y * width + x;
1511 for (k = 0; k < ISP_VEC_NELEMS; k += 2) {
1512 mmgr_load(ptr, (void *)(&data), sizeof(int));
1513 params->fpn_config.data[ofs + 2 * k] =
1514 (short) (data & 0xFFFF);
1515 params->fpn_config.data[ofs + 2 * k + 2] =
1516 (short) ((data >> 16) & 0xFFFF);
1517 ptr += sizeof(int); /* byte system address */
1519 for (k = 0; k < ISP_VEC_NELEMS; k += 2) {
1520 mmgr_load(ptr, (void *)(&data), sizeof(int));
1521 params->fpn_config.data[ofs + 2 * k + 1] =
1522 (short) (data & 0xFFFF);
1523 params->fpn_config.data[ofs + 2 * k + 3] =
1524 (short) ((data >> 16) & 0xFFFF);
1525 ptr += sizeof(int); /* byte system address */
1531 convert_raw_to_fpn(params);
1533 /* overwrite isp parameter */
1534 ia_css_process_kernel(stream, params, ia_css_kernel_process_param[IA_CSS_FPN_ID]);
1536 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS);
1538 return IA_CSS_SUCCESS;
1542 sh_css_params_set_binning_factor(struct ia_css_stream *stream, unsigned int binning_fact)
1544 struct ia_css_isp_parameters *params;
1546 IA_CSS_ENTER_PRIVATE("void");
1547 assert(stream != NULL);
1549 params = stream->isp_params_configs;
1551 if (params->sensor_binning != binning_fact) {
1552 params->sensor_binning = binning_fact;
1553 params->sc_table_changed = true;
1556 IA_CSS_LEAVE_PRIVATE("void");
1558 return params->sc_table_changed;
1562 sh_css_update_shading_table_status(struct ia_css_pipe *pipe,
1563 struct ia_css_isp_parameters *params)
1565 if (params && pipe && (pipe->pipe_num != params->sc_table_last_pipe_num)) {
1566 params->sc_table_dirty = true;
1567 params->sc_table_last_pipe_num = pipe->pipe_num;
1572 sh_css_set_shading_table(struct ia_css_stream *stream,
1573 struct ia_css_isp_parameters *params,
1574 const struct ia_css_shading_table *table)
1576 IA_CSS_ENTER_PRIVATE("");
1579 assert(stream != NULL);
1584 if ((table != params->sc_table) || params->sc_table_dirty) {
1585 params->sc_table = table;
1586 params->sc_table_changed = true;
1587 params->sc_table_dirty = false;
1588 /* Not very clean, this goes to sh_css.c to invalidate the
1589 * shading table for all pipes. Should replaced by a loop
1590 * and a pipe-specific call.
1592 if (!params->output_frame)
1593 sh_css_invalidate_shading_tables(stream);
1596 IA_CSS_LEAVE_PRIVATE("void");
1600 ia_css_params_store_ia_css_host_data(
1601 hrt_vaddress ddr_addr,
1602 struct ia_css_host_data *data)
1604 assert(data != NULL);
1605 assert(data->address != NULL);
1606 assert(ddr_addr != mmgr_NULL);
1608 IA_CSS_ENTER_PRIVATE("");
1610 mmgr_store(ddr_addr,
1611 (void *)(data->address),
1612 (size_t)data->size);
1614 IA_CSS_LEAVE_PRIVATE("void");
1617 struct ia_css_host_data *
1618 ia_css_params_alloc_convert_sctbl(
1619 const struct ia_css_pipeline_stage *stage,
1620 const struct ia_css_shading_table *shading_table)
1622 const struct ia_css_binary *binary = stage->binary;
1623 struct ia_css_host_data *sctbl;
1624 unsigned int i, j, aligned_width, row_padding;
1625 unsigned int sctbl_size;
1628 assert(binary != NULL);
1629 assert(shading_table != NULL);
1631 IA_CSS_ENTER_PRIVATE("");
1633 if (shading_table == NULL) {
1634 IA_CSS_LEAVE_PRIVATE("void");
1638 aligned_width = binary->sctbl_aligned_width_per_color;
1639 row_padding = aligned_width - shading_table->width;
1640 sctbl_size = shading_table->height * IA_CSS_SC_NUM_COLORS * aligned_width * sizeof(short);
1642 sctbl = ia_css_host_data_allocate((size_t)sctbl_size);
1646 ptr = (short int*)sctbl->address;
1651 for (i = 0; i < shading_table->height; i++) {
1652 for (j = 0; j < IA_CSS_SC_NUM_COLORS; j++) {
1654 &shading_table->data[j]
1655 [i*shading_table->width],
1656 shading_table->width * sizeof(short));
1657 ptr += aligned_width;
1661 IA_CSS_LEAVE_PRIVATE("void");
1665 enum ia_css_err ia_css_params_store_sctbl(
1666 const struct ia_css_pipeline_stage *stage,
1667 hrt_vaddress sc_tbl,
1668 const struct ia_css_shading_table *sc_config)
1670 struct ia_css_host_data *isp_sc_tbl;
1672 IA_CSS_ENTER_PRIVATE("");
1674 if (sc_config == NULL) {
1675 IA_CSS_LEAVE_PRIVATE("void");
1676 return IA_CSS_SUCCESS;
1679 isp_sc_tbl = ia_css_params_alloc_convert_sctbl(stage, sc_config);
1681 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
1682 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
1684 /* store the shading table to ddr */
1685 ia_css_params_store_ia_css_host_data(sc_tbl, isp_sc_tbl);
1686 ia_css_host_data_free(isp_sc_tbl);
1688 IA_CSS_LEAVE_PRIVATE("void");
1690 return IA_CSS_SUCCESS;
1694 sh_css_enable_pipeline(const struct ia_css_binary *binary)
1699 IA_CSS_ENTER_PRIVATE("");
1701 ia_css_isp_param_enable_pipeline(&binary->mem_params);
1703 IA_CSS_LEAVE_PRIVATE("void");
1706 static enum ia_css_err
1707 ia_css_process_zoom_and_motion(
1708 struct ia_css_isp_parameters *params,
1709 const struct ia_css_pipeline_stage *first_stage)
1711 /* first_stage can be NULL */
1712 const struct ia_css_pipeline_stage *stage;
1713 enum ia_css_err err = IA_CSS_SUCCESS;
1714 struct ia_css_resolution pipe_in_res;
1715 pipe_in_res.width = 0;
1716 pipe_in_res.height = 0;
1718 assert(params != NULL);
1720 IA_CSS_ENTER_PRIVATE("");
1722 /* Go through all stages to udate uds and cropping */
1723 for (stage = first_stage; stage; stage = stage->next) {
1725 struct ia_css_binary *binary;
1726 /* note: the var below is made static as it is quite large;
1727 if it is not static it ends up on the stack which could
1728 cause issues for drivers
1730 static struct ia_css_binary tmp_binary;
1732 const struct ia_css_binary_xinfo *info = NULL;
1734 binary = stage->binary;
1736 info = binary->info;
1738 const struct sh_css_binary_args *args = &stage->args;
1739 const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL};
1740 if (args->out_frame[0])
1741 out_infos[0] = &args->out_frame[0]->info;
1742 info = &stage->firmware->info.isp;
1743 ia_css_binary_fill_info(info, false, false,
1744 IA_CSS_STREAM_FORMAT_RAW_10,
1745 args->in_frame ? &args->in_frame->info : NULL,
1748 args->out_vf_frame ? &args->out_vf_frame->info
1753 binary = &tmp_binary;
1754 binary->info = info;
1757 if (stage == first_stage) {
1758 /* we will use pipe_in_res to scale the zoom crop region if needed */
1759 pipe_in_res = binary->effective_in_frame_res;
1762 assert(stage->stage_num < SH_CSS_MAX_STAGES);
1763 if (params->dz_config.zoom_region.resolution.width == 0 &&
1764 params->dz_config.zoom_region.resolution.height == 0) {
1765 sh_css_update_uds_and_crop_info(
1767 &binary->in_frame_info,
1768 &binary->out_frame_info[0],
1769 &binary->dvs_envelope,
1771 ¶ms->motion_config,
1772 ¶ms->uds[stage->stage_num].uds,
1773 ¶ms->uds[stage->stage_num].crop_pos,
1774 stage->enable_zoom);
1776 err = sh_css_update_uds_and_crop_info_based_on_zoom_region(
1778 &binary->in_frame_info,
1779 &binary->out_frame_info[0],
1780 &binary->dvs_envelope,
1782 ¶ms->motion_config,
1783 ¶ms->uds[stage->stage_num].uds,
1784 ¶ms->uds[stage->stage_num].crop_pos,
1786 stage->enable_zoom);
1787 if (err != IA_CSS_SUCCESS)
1791 params->isp_params_changed = true;
1793 IA_CSS_LEAVE_PRIVATE("void");
1798 sh_css_set_gamma_table(struct ia_css_isp_parameters *params,
1799 const struct ia_css_gamma_table *table)
1803 IA_CSS_ENTER_PRIVATE("table=%p", table);
1805 assert(params != NULL);
1806 params->gc_table = *table;
1807 params->config_changed[IA_CSS_GC_ID] = true;
1809 IA_CSS_LEAVE_PRIVATE("void");
1813 sh_css_get_gamma_table(const struct ia_css_isp_parameters *params,
1814 struct ia_css_gamma_table *table)
1818 IA_CSS_ENTER_PRIVATE("table=%p", table);
1820 assert(params != NULL);
1821 *table = params->gc_table;
1823 IA_CSS_LEAVE_PRIVATE("void");
1827 sh_css_set_ctc_table(struct ia_css_isp_parameters *params,
1828 const struct ia_css_ctc_table *table)
1833 IA_CSS_ENTER_PRIVATE("table=%p", table);
1835 assert(params != NULL);
1836 params->ctc_table = *table;
1837 params->config_changed[IA_CSS_CTC_ID] = true;
1839 IA_CSS_LEAVE_PRIVATE("void");
1843 sh_css_get_ctc_table(const struct ia_css_isp_parameters *params,
1844 struct ia_css_ctc_table *table)
1849 IA_CSS_ENTER_PRIVATE("table=%p", table);
1851 assert(params != NULL);
1852 *table = params->ctc_table;
1854 IA_CSS_LEAVE_PRIVATE("void");
1858 sh_css_set_macc_table(struct ia_css_isp_parameters *params,
1859 const struct ia_css_macc_table *table)
1864 IA_CSS_ENTER_PRIVATE("table=%p", table);
1866 assert(params != NULL);
1867 params->macc_table = *table;
1868 params->config_changed[IA_CSS_MACC_ID] = true;
1870 IA_CSS_LEAVE_PRIVATE("void");
1874 sh_css_get_macc_table(const struct ia_css_isp_parameters *params,
1875 struct ia_css_macc_table *table)
1880 IA_CSS_ENTER_PRIVATE("table=%p", table);
1882 assert(params != NULL);
1883 *table = params->macc_table;
1885 IA_CSS_LEAVE_PRIVATE("void");
1888 void ia_css_morph_table_free(
1889 struct ia_css_morph_table *me)
1901 for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
1902 if (me->coordinates_x[i]) {
1903 sh_css_free(me->coordinates_x[i]);
1904 me->coordinates_x[i] = NULL;
1906 if (me->coordinates_y[i]) {
1907 sh_css_free(me->coordinates_y[i]);
1908 me->coordinates_y[i] = NULL;
1913 IA_CSS_LEAVE("void");
1918 struct ia_css_morph_table *ia_css_morph_table_allocate(
1920 unsigned int height)
1924 struct ia_css_morph_table *me;
1928 me = sh_css_malloc(sizeof(*me));
1930 IA_CSS_ERROR("out of memory");
1934 for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
1935 me->coordinates_x[i] = NULL;
1936 me->coordinates_y[i] = NULL;
1939 for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
1940 me->coordinates_x[i] =
1941 sh_css_malloc(height * width *
1942 sizeof(*me->coordinates_x[i]));
1943 me->coordinates_y[i] =
1944 sh_css_malloc(height * width *
1945 sizeof(*me->coordinates_y[i]));
1947 if ((me->coordinates_x[i] == NULL) ||
1948 (me->coordinates_y[i] == NULL)) {
1949 ia_css_morph_table_free(me);
1955 me->height = height;
1962 static enum ia_css_err sh_css_params_default_morph_table(
1963 struct ia_css_morph_table **table,
1964 const struct ia_css_binary *binary)
1966 /* MW 2400 advanced requires different scaling */
1967 unsigned int i, j, k, step, width, height;
1968 short start_x[IA_CSS_MORPH_TABLE_NUM_PLANES] = { -8, 0, -8, 0, 0, -8 },
1969 start_y[IA_CSS_MORPH_TABLE_NUM_PLANES] = { 0, 0, -8, -8, -8, 0 };
1970 struct ia_css_morph_table *tab;
1972 assert(table != NULL);
1973 assert(binary != NULL);
1975 IA_CSS_ENTER_PRIVATE("");
1977 step = (ISP_VEC_NELEMS / 16) * 128,
1978 width = binary->morph_tbl_width,
1979 height = binary->morph_tbl_height;
1981 tab = ia_css_morph_table_allocate(width, height);
1983 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
1985 for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
1986 short val_y = start_y[i];
1987 for (j = 0; j < height; j++) {
1988 short val_x = start_x[i];
1989 unsigned short *x_ptr, *y_ptr;
1991 x_ptr = &tab->coordinates_x[i][j * width];
1992 y_ptr = &tab->coordinates_y[i][j * width];
1993 for (k = 0; k < width;
1994 k++, x_ptr++, y_ptr++, val_x += (short)step) {
1997 else if (k == width - 1)
1998 *x_ptr = val_x + 2 * start_x[i];
2006 val_y += (short)step;
2011 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS);
2013 return IA_CSS_SUCCESS;
2017 sh_css_set_morph_table(struct ia_css_isp_parameters *params,
2018 const struct ia_css_morph_table *table)
2023 IA_CSS_ENTER_PRIVATE("table=%p", table);
2025 assert(params != NULL);
2026 if (table->enable == false)
2028 params->morph_table = table;
2029 params->morph_table_changed = true;
2030 IA_CSS_LEAVE_PRIVATE("void");
2034 ia_css_translate_3a_statistics(
2035 struct ia_css_3a_statistics *host_stats,
2036 const struct ia_css_isp_3a_statistics_map *isp_stats)
2039 if (host_stats->grid.use_dmem) {
2040 IA_CSS_LOG("3A: DMEM");
2041 ia_css_s3a_dmem_decode(host_stats, isp_stats->dmem_stats);
2043 IA_CSS_LOG("3A: VMEM");
2044 ia_css_s3a_vmem_decode(host_stats, isp_stats->vmem_stats_hi,
2045 isp_stats->vmem_stats_lo);
2047 #if !defined(HAS_NO_HMEM)
2048 IA_CSS_LOG("3A: HMEM");
2049 ia_css_s3a_hmem_decode(host_stats, isp_stats->hmem_stats);
2052 IA_CSS_LEAVE("void");
2056 ia_css_isp_3a_statistics_map_free(struct ia_css_isp_3a_statistics_map *me)
2059 if (me->data_allocated) {
2060 sh_css_free(me->data_ptr);
2061 me->data_ptr = NULL;
2062 me->data_allocated = false;
2068 struct ia_css_isp_3a_statistics_map *
2069 ia_css_isp_3a_statistics_map_allocate(
2070 const struct ia_css_isp_3a_statistics *isp_stats,
2073 struct ia_css_isp_3a_statistics_map *me;
2074 /* Windows compiler does not like adding sizes to a void *
2075 * so we use a local char * instead. */
2078 me = sh_css_malloc(sizeof(*me));
2080 IA_CSS_LEAVE("cannot allocate memory");
2084 me->data_ptr = data_ptr;
2085 me->data_allocated = data_ptr == NULL;
2087 me->data_ptr = sh_css_malloc(isp_stats->size);
2088 if (!me->data_ptr) {
2089 IA_CSS_LEAVE("cannot allocate memory");
2093 base_ptr = me->data_ptr;
2095 me->size = isp_stats->size;
2096 /* GCC complains when we assign a char * to a void *, so these
2097 * casts are necessary unfortunately. */
2098 me->dmem_stats = (void *)base_ptr;
2099 me->vmem_stats_hi = (void *)(base_ptr + isp_stats->dmem_size);
2100 me->vmem_stats_lo = (void *)(base_ptr + isp_stats->dmem_size +
2101 isp_stats->vmem_size);
2102 me->hmem_stats = (void *)(base_ptr + isp_stats->dmem_size +
2103 2 * isp_stats->vmem_size);
2105 IA_CSS_LEAVE("map=%p", me);
2116 ia_css_get_3a_statistics(struct ia_css_3a_statistics *host_stats,
2117 const struct ia_css_isp_3a_statistics *isp_stats)
2119 struct ia_css_isp_3a_statistics_map *map;
2120 enum ia_css_err ret = IA_CSS_SUCCESS;
2122 IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats);
2124 assert(host_stats != NULL);
2125 assert(isp_stats != NULL);
2127 map = ia_css_isp_3a_statistics_map_allocate(isp_stats, NULL);
2129 mmgr_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size);
2130 ia_css_translate_3a_statistics(host_stats, map);
2131 ia_css_isp_3a_statistics_map_free(map);
2133 IA_CSS_ERROR("out of memory");
2134 ret = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
2137 IA_CSS_LEAVE_ERR(ret);
2141 /* Parameter encoding is not yet orthogonal.
2142 This function hnadles some of the exceptions.
2145 ia_css_set_param_exceptions(const struct ia_css_pipe *pipe,
2146 struct ia_css_isp_parameters *params)
2148 assert(params != NULL);
2150 /* Copy also to DP. Should be done by the driver. */
2151 params->dp_config.gr = params->wb_config.gr;
2152 params->dp_config.r = params->wb_config.r;
2153 params->dp_config.b = params->wb_config.b;
2154 params->dp_config.gb = params->wb_config.gb;
2156 assert(pipe != NULL);
2157 assert(pipe->mode < IA_CSS_PIPE_ID_NUM);
2159 if (pipe->mode < IA_CSS_PIPE_ID_NUM) {
2160 params->pipe_dp_config[pipe->mode].gr = params->wb_config.gr;
2161 params->pipe_dp_config[pipe->mode].r = params->wb_config.r;
2162 params->pipe_dp_config[pipe->mode].b = params->wb_config.b;
2163 params->pipe_dp_config[pipe->mode].gb = params->wb_config.gb;
2170 sh_css_set_dp_config(const struct ia_css_pipe *pipe,
2171 struct ia_css_isp_parameters *params,
2172 const struct ia_css_dp_config *config)
2177 assert(params != NULL);
2178 assert(pipe != NULL);
2179 assert(pipe->mode < IA_CSS_PIPE_ID_NUM);
2181 IA_CSS_ENTER_PRIVATE("config=%p", config);
2182 ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE);
2183 if (pipe->mode < IA_CSS_PIPE_ID_NUM) {
2184 params->pipe_dp_config[pipe->mode] = *config;
2185 params->pipe_dpc_config_changed[pipe->mode] = true;
2187 IA_CSS_LEAVE_PRIVATE("void");
2192 sh_css_get_dp_config(const struct ia_css_pipe *pipe,
2193 const struct ia_css_isp_parameters *params,
2194 struct ia_css_dp_config *config)
2199 assert(params != NULL);
2200 assert(pipe != NULL);
2201 IA_CSS_ENTER_PRIVATE("config=%p", config);
2203 *config = params->pipe_dp_config[pipe->mode];
2205 IA_CSS_LEAVE_PRIVATE("void");
2209 sh_css_set_nr_config(struct ia_css_isp_parameters *params,
2210 const struct ia_css_nr_config *config)
2214 assert(params != NULL);
2216 IA_CSS_ENTER_PRIVATE("config=%p", config);
2218 ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE);
2219 params->nr_config = *config;
2220 params->yee_config.nr = *config;
2221 params->config_changed[IA_CSS_NR_ID] = true;
2222 params->config_changed[IA_CSS_YEE_ID] = true;
2223 params->config_changed[IA_CSS_BNR_ID] = true;
2225 IA_CSS_LEAVE_PRIVATE("void");
2229 sh_css_set_ee_config(struct ia_css_isp_parameters *params,
2230 const struct ia_css_ee_config *config)
2234 assert(params != NULL);
2236 IA_CSS_ENTER_PRIVATE("config=%p", config);
2237 ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE);
2239 params->ee_config = *config;
2240 params->yee_config.ee = *config;
2241 params->config_changed[IA_CSS_YEE_ID] = true;
2243 IA_CSS_LEAVE_PRIVATE("void");
2247 sh_css_get_ee_config(const struct ia_css_isp_parameters *params,
2248 struct ia_css_ee_config *config)
2253 IA_CSS_ENTER_PRIVATE("config=%p", config);
2255 assert(params != NULL);
2256 *config = params->ee_config;
2258 ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE);
2259 IA_CSS_LEAVE_PRIVATE("void");
2263 sh_css_set_pipe_dvs_6axis_config(const struct ia_css_pipe *pipe,
2264 struct ia_css_isp_parameters *params,
2265 const struct ia_css_dvs_6axis_config *dvs_config)
2267 if (dvs_config == NULL)
2269 assert(params != NULL);
2270 assert(pipe != NULL);
2271 assert(dvs_config->height_y == dvs_config->height_uv);
2272 assert((dvs_config->width_y - 1) == 2 * (dvs_config->width_uv - 1));
2273 assert(pipe->mode < IA_CSS_PIPE_ID_NUM);
2275 IA_CSS_ENTER_PRIVATE("dvs_config=%p", dvs_config);
2277 copy_dvs_6axis_table(params->pipe_dvs_6axis_config[pipe->mode], dvs_config);
2279 #if !defined(HAS_NO_DVS_6AXIS_CONFIG_UPDATE)
2280 params->pipe_dvs_6axis_config_changed[pipe->mode] = true;
2283 IA_CSS_LEAVE_PRIVATE("void");
2287 sh_css_get_pipe_dvs_6axis_config(const struct ia_css_pipe *pipe,
2288 const struct ia_css_isp_parameters *params,
2289 struct ia_css_dvs_6axis_config *dvs_config)
2291 if (dvs_config == NULL)
2293 assert(params != NULL);
2294 assert(pipe != NULL);
2295 assert(dvs_config->height_y == dvs_config->height_uv);
2296 assert((dvs_config->width_y - 1) == 2 * dvs_config->width_uv - 1);
2298 IA_CSS_ENTER_PRIVATE("dvs_config=%p", dvs_config);
2300 if ((pipe->mode < IA_CSS_PIPE_ID_NUM) &&
2301 (dvs_config->width_y == params->pipe_dvs_6axis_config[pipe->mode]->width_y) &&
2302 (dvs_config->height_y == params->pipe_dvs_6axis_config[pipe->mode]->height_y) &&
2303 (dvs_config->width_uv == params->pipe_dvs_6axis_config[pipe->mode]->width_uv) &&
2304 (dvs_config->height_uv == params->pipe_dvs_6axis_config[pipe->mode]->height_uv) &&
2305 dvs_config->xcoords_y &&
2306 dvs_config->ycoords_y &&
2307 dvs_config->xcoords_uv &&
2308 dvs_config->ycoords_uv)
2310 copy_dvs_6axis_table(dvs_config, params->pipe_dvs_6axis_config[pipe->mode]);
2313 IA_CSS_LEAVE_PRIVATE("void");
2317 sh_css_set_baa_config(struct ia_css_isp_parameters *params,
2318 const struct ia_css_aa_config *config)
2322 assert(params != NULL);
2324 IA_CSS_ENTER_PRIVATE("config=%p", config);
2326 params->bds_config = *config;
2327 params->config_changed[IA_CSS_BDS_ID] = true;
2329 IA_CSS_LEAVE_PRIVATE("void");
2333 sh_css_get_baa_config(const struct ia_css_isp_parameters *params,
2334 struct ia_css_aa_config *config)
2338 assert(params != NULL);
2340 IA_CSS_ENTER_PRIVATE("config=%p", config);
2342 *config = params->bds_config;
2344 IA_CSS_LEAVE_PRIVATE("void");
2348 sh_css_set_dz_config(struct ia_css_isp_parameters *params,
2349 const struct ia_css_dz_config *config)
2353 assert(params != NULL);
2355 IA_CSS_ENTER_PRIVATE("dx=%d, dy=%d", config->dx, config->dy);
2357 assert(config->dx <= HRT_GDC_N);
2358 assert(config->dy <= HRT_GDC_N);
2360 params->dz_config = *config;
2361 params->dz_config_changed = true;
2362 /* JK: Why isp params changed?? */
2363 params->isp_params_changed = true;
2365 IA_CSS_LEAVE_PRIVATE("void");
2369 sh_css_get_dz_config(const struct ia_css_isp_parameters *params,
2370 struct ia_css_dz_config *config)
2374 assert(params != NULL);
2376 IA_CSS_ENTER_PRIVATE("config=%p", config);
2378 *config = params->dz_config;
2380 IA_CSS_LEAVE_PRIVATE("dx=%d, dy=%d", config->dx, config->dy);
2384 sh_css_set_motion_vector(struct ia_css_isp_parameters *params,
2385 const struct ia_css_vector *motion)
2389 assert(params != NULL);
2391 IA_CSS_ENTER_PRIVATE("x=%d, y=%d", motion->x, motion->y);
2393 params->motion_config = *motion;
2394 /* JK: Why do isp params change? */
2395 params->motion_config_changed = true;
2396 params->isp_params_changed = true;
2398 IA_CSS_LEAVE_PRIVATE("void");
2402 sh_css_get_motion_vector(const struct ia_css_isp_parameters *params,
2403 struct ia_css_vector *motion)
2407 assert(params != NULL);
2409 IA_CSS_ENTER_PRIVATE("motion=%p", motion);
2411 *motion = params->motion_config;
2413 IA_CSS_LEAVE_PRIVATE("x=%d, y=%d", motion->x, motion->y);
2416 struct ia_css_isp_config *
2417 sh_css_pipe_isp_config_get(struct ia_css_pipe *pipe)
2421 IA_CSS_ERROR("pipe=%p", NULL);
2424 return pipe->config.p_isp_config;
2428 ia_css_stream_set_isp_config(
2429 struct ia_css_stream *stream,
2430 const struct ia_css_isp_config *config)
2432 return ia_css_stream_set_isp_config_on_pipe(stream, config, NULL);
2436 ia_css_stream_set_isp_config_on_pipe(
2437 struct ia_css_stream *stream,
2438 const struct ia_css_isp_config *config,
2439 struct ia_css_pipe *pipe)
2441 enum ia_css_err err = IA_CSS_SUCCESS;
2443 if ((stream == NULL) || (config == NULL))
2444 return IA_CSS_ERR_INVALID_ARGUMENTS;
2446 IA_CSS_ENTER("stream=%p, config=%p, pipe=%p", stream, config, pipe);
2448 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
2449 if (config->output_frame)
2450 err = sh_css_set_per_frame_isp_config_on_pipe(stream, config, pipe);
2453 err = sh_css_set_global_isp_config_on_pipe(stream->pipes[0], config, pipe);
2455 IA_CSS_LEAVE_ERR(err);
2460 ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe,
2461 struct ia_css_isp_config *config)
2463 struct ia_css_pipe *pipe_in = pipe;
2464 enum ia_css_err err = IA_CSS_SUCCESS;
2466 IA_CSS_ENTER("pipe=%p", pipe);
2468 if ((pipe == NULL) || (pipe->stream == NULL))
2469 return IA_CSS_ERR_INVALID_ARGUMENTS;
2471 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "config=%p\n", config);
2473 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
2474 if (config->output_frame)
2475 err = sh_css_set_per_frame_isp_config_on_pipe(pipe->stream, config, pipe);
2478 err = sh_css_set_global_isp_config_on_pipe(pipe, config, pipe_in);
2479 IA_CSS_LEAVE_ERR(err);
2483 static enum ia_css_err
2484 sh_css_set_global_isp_config_on_pipe(
2485 struct ia_css_pipe *curr_pipe,
2486 const struct ia_css_isp_config *config,
2487 struct ia_css_pipe *pipe)
2489 enum ia_css_err err = IA_CSS_SUCCESS;
2490 enum ia_css_err err1 = IA_CSS_SUCCESS;
2491 enum ia_css_err err2 = IA_CSS_SUCCESS;
2493 IA_CSS_ENTER_PRIVATE("stream=%p, config=%p, pipe=%p", curr_pipe, config, pipe);
2495 err1 = sh_css_init_isp_params_from_config(curr_pipe, curr_pipe->stream->isp_params_configs, config, pipe);
2497 /* Now commit all changes to the SP */
2498 err2 = sh_css_param_update_isp_params(curr_pipe, curr_pipe->stream->isp_params_configs, sh_css_sp_is_running(), pipe);
2500 /* The following code is intentional. The sh_css_init_isp_params_from_config interface
2501 * throws an error when both DPC and BDS is enabled. The CSS API must pass this error
2502 * information to the caller, ie. the host. We do not return this error immediately,
2503 * but instead continue with updating the ISP params to enable testing of features
2504 * which are currently in TR phase. */
2506 err = (err1 != IA_CSS_SUCCESS ) ? err1 : ((err2 != IA_CSS_SUCCESS) ? err2 : err);
2508 IA_CSS_LEAVE_ERR_PRIVATE(err);
2512 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
2513 static enum ia_css_err
2514 sh_css_set_per_frame_isp_config_on_pipe(
2515 struct ia_css_stream *stream,
2516 const struct ia_css_isp_config *config,
2517 struct ia_css_pipe *pipe)
2520 bool per_frame_config_created = false;
2521 enum ia_css_err err = IA_CSS_SUCCESS;
2522 enum ia_css_err err1 = IA_CSS_SUCCESS;
2523 enum ia_css_err err2 = IA_CSS_SUCCESS;
2524 enum ia_css_err err3 = IA_CSS_SUCCESS;
2526 struct sh_css_ddr_address_map *ddr_ptrs;
2527 struct sh_css_ddr_address_map_size *ddr_ptrs_size;
2528 struct ia_css_isp_parameters *params;
2530 IA_CSS_ENTER_PRIVATE("stream=%p, config=%p, pipe=%p", stream, config, pipe);
2533 err = IA_CSS_ERR_INVALID_ARGUMENTS;
2537 /* create per-frame ISP params object with default values
2538 * from stream->isp_params_configs if one doesn't already exist
2540 if (!stream->per_frame_isp_params_configs)
2542 err = sh_css_create_isp_params(stream,
2543 &stream->per_frame_isp_params_configs);
2544 if(err != IA_CSS_SUCCESS)
2546 per_frame_config_created = true;
2549 params = stream->per_frame_isp_params_configs;
2551 /* update new ISP params object with the new config */
2552 if (!sh_css_init_isp_params_from_global(stream, params, false, pipe)) {
2553 err1 = IA_CSS_ERR_INVALID_ARGUMENTS;
2556 err2 = sh_css_init_isp_params_from_config(stream->pipes[0], params, config, pipe);
2558 if (per_frame_config_created)
2560 ddr_ptrs = ¶ms->ddr_ptrs;
2561 ddr_ptrs_size = ¶ms->ddr_ptrs_size;
2562 /* create per pipe reference to general ddr_ptrs */
2563 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
2564 ref_sh_css_ddr_address_map(ddr_ptrs, ¶ms->pipe_ddr_ptrs[i]);
2565 params->pipe_ddr_ptrs_size[i] = *ddr_ptrs_size;
2569 /* now commit to ddr */
2570 err3 = sh_css_param_update_isp_params(stream->pipes[0], params, sh_css_sp_is_running(), pipe);
2572 /* The following code is intentional. The sh_css_init_sp_params_from_config and
2573 * sh_css_init_isp_params_from_config throws an error when both DPC and BDS is enabled.
2574 * The CSS API must pass this error information to the caller, ie. the host.
2575 * We do not return this error immediately, but instead continue with updating the ISP params
2576 * to enable testing of features which are currently in TR phase. */
2577 err = (err1 != IA_CSS_SUCCESS) ? err1 :
2578 (err2 != IA_CSS_SUCCESS) ? err2 :
2579 (err3 != IA_CSS_SUCCESS) ? err3 : err;
2581 IA_CSS_LEAVE_ERR_PRIVATE(err);
2586 static enum ia_css_err
2587 sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe,
2588 struct ia_css_isp_parameters *params,
2589 const struct ia_css_isp_config *config,
2590 struct ia_css_pipe *pipe_in)
2592 enum ia_css_err err = IA_CSS_SUCCESS;
2593 bool is_dp_10bpp = true;
2594 assert(pipe != NULL);
2596 IA_CSS_ENTER_PRIVATE("pipe=%p, config=%p, params=%p", pipe, config, params);
2598 ia_css_set_configs(params, config);
2601 sh_css_set_nr_config(params, config->nr_config);
2602 sh_css_set_ee_config(params, config->ee_config);
2603 sh_css_set_baa_config(params, config->baa_config);
2604 if ((pipe->mode < IA_CSS_PIPE_ID_NUM) &&
2605 (params->pipe_dvs_6axis_config[pipe->mode]))
2606 sh_css_set_pipe_dvs_6axis_config(pipe, params, config->dvs_6axis_config);
2607 sh_css_set_dz_config(params, config->dz_config);
2608 sh_css_set_motion_vector(params, config->motion_vector);
2609 sh_css_update_shading_table_status(pipe_in, params);
2610 sh_css_set_shading_table(pipe->stream, params, config->shading_table);
2611 sh_css_set_morph_table(params, config->morph_table);
2612 sh_css_set_macc_table(params, config->macc_table);
2613 sh_css_set_gamma_table(params, config->gamma_table);
2614 sh_css_set_ctc_table(params, config->ctc_table);
2615 /* ------ deprecated(bz675) : from ------ */
2616 sh_css_set_shading_settings(params, config->shading_settings);
2617 /* ------ deprecated(bz675) : to ------ */
2619 params->dis_coef_table_changed = (config->dvs_coefs != NULL);
2620 params->dvs2_coef_table_changed = (config->dvs2_coefs != NULL);
2622 params->output_frame = config->output_frame;
2623 params->isp_parameters_id = config->isp_config_id;
2625 /* Currently we do not offer CSS interface to set different
2626 * configurations for DPC, i.e. depending on DPC being enabled
2627 * before (NORM+OBC) or after. The folllowing code to set the
2628 * DPC configuration should be updated when this interface is made
2630 sh_css_set_dp_config(pipe, params, config->dp_config);
2631 ia_css_set_param_exceptions(pipe, params);
2634 if (IA_CSS_SUCCESS ==
2635 sh_css_select_dp_10bpp_config(pipe, &is_dp_10bpp)) {
2636 /* return an error when both DPC and BDS is enabled by the
2638 /* we do not exit from this point immediately to allow internal
2639 * firmware feature testing. */
2641 err = IA_CSS_ERR_INVALID_ARGUMENTS;
2644 err = IA_CSS_ERR_INTERNAL_ERROR;
2649 ia_css_set_param_exceptions(pipe, params);
2652 IA_CSS_LEAVE_ERR_PRIVATE(err);
2657 ia_css_stream_get_isp_config(
2658 const struct ia_css_stream *stream,
2659 struct ia_css_isp_config *config)
2661 IA_CSS_ENTER("void");
2662 ia_css_pipe_get_isp_config(stream->pipes[0], config);
2663 IA_CSS_LEAVE("void");
2667 ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe,
2668 struct ia_css_isp_config *config)
2670 struct ia_css_isp_parameters *params = NULL;
2672 assert(config != NULL);
2674 IA_CSS_ENTER("config=%p", config);
2676 params = pipe->stream->isp_params_configs;
2677 assert(params != NULL);
2679 ia_css_get_configs(params, config);
2681 sh_css_get_ee_config(params, config->ee_config);
2682 sh_css_get_baa_config(params, config->baa_config);
2683 sh_css_get_pipe_dvs_6axis_config(pipe, params, config->dvs_6axis_config);
2684 sh_css_get_dp_config(pipe, params, config->dp_config);
2685 sh_css_get_macc_table(params, config->macc_table);
2686 sh_css_get_gamma_table(params, config->gamma_table);
2687 sh_css_get_ctc_table(params, config->ctc_table);
2688 sh_css_get_dz_config(params, config->dz_config);
2689 sh_css_get_motion_vector(params, config->motion_vector);
2690 /* ------ deprecated(bz675) : from ------ */
2691 sh_css_get_shading_settings(params, config->shading_settings);
2692 /* ------ deprecated(bz675) : to ------ */
2694 config->output_frame = params->output_frame;
2695 config->isp_config_id = params->isp_parameters_id;
2697 IA_CSS_LEAVE("void");
2702 * coding style says the return of "mmgr_NULL" is the error signal
2704 * Deprecated: Implement mmgr_realloc()
2706 static bool realloc_isp_css_mm_buf(
2707 hrt_vaddress *curr_buf,
2711 enum ia_css_err *err,
2712 uint16_t mmgr_attribute)
2716 *err = IA_CSS_SUCCESS;
2717 /* Possible optimization: add a function sh_css_isp_css_mm_realloc()
2718 * and implement on top of hmm. */
2720 IA_CSS_ENTER_PRIVATE("void");
2722 if (!force && *curr_size >= needed_size) {
2723 IA_CSS_LEAVE_PRIVATE("false");
2726 /* don't reallocate if single ref to buffer and same size */
2727 if (*curr_size == needed_size && ia_css_refcount_is_single(*curr_buf)) {
2728 IA_CSS_LEAVE_PRIVATE("false");
2732 id = IA_CSS_REFCOUNT_PARAM_BUFFER;
2733 ia_css_refcount_decrement(id, *curr_buf);
2734 *curr_buf = ia_css_refcount_increment(id, mmgr_alloc_attr(needed_size,
2738 *err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
2741 *curr_size = needed_size;
2743 IA_CSS_LEAVE_PRIVATE("true");
2747 static bool reallocate_buffer(
2748 hrt_vaddress *curr_buf,
2752 enum ia_css_err *err)
2755 uint16_t mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT;
2757 IA_CSS_ENTER_PRIVATE("void");
2759 ret = realloc_isp_css_mm_buf(curr_buf,
2760 curr_size, needed_size, force, err, mmgr_attribute);
2762 IA_CSS_LEAVE_PRIVATE("ret=%d", ret);
2768 struct ia_css_isp_3a_statistics *
2769 ia_css_isp_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid)
2771 struct ia_css_isp_3a_statistics *me;
2773 IA_CSS_ENTER("grid=%p", grid);
2775 assert(grid != NULL);
2777 /* MW: Does "grid->enable" also control the histogram output ?? */
2781 me = sh_css_calloc(1, sizeof(*me));
2785 if (grid->use_dmem) {
2786 me->dmem_size = sizeof(struct ia_css_3a_output) *
2787 grid->aligned_width *
2788 grid->aligned_height;
2790 me->vmem_size = ISP_S3ATBL_HI_LO_STRIDE_BYTES *
2791 grid->aligned_height;
2793 #if !defined(HAS_NO_HMEM)
2794 me->hmem_size = sizeof_hmem(HMEM0_ID);
2797 /* All subsections need to be aligned to the system bus width */
2798 me->dmem_size = CEIL_MUL(me->dmem_size, HIVE_ISP_DDR_WORD_BYTES);
2799 me->vmem_size = CEIL_MUL(me->vmem_size, HIVE_ISP_DDR_WORD_BYTES);
2800 me->hmem_size = CEIL_MUL(me->hmem_size, HIVE_ISP_DDR_WORD_BYTES);
2802 me->size = me->dmem_size + me->vmem_size * 2 + me->hmem_size;
2803 me->data_ptr = mmgr_malloc(me->size);
2804 if (me->data_ptr == mmgr_NULL) {
2810 me->data.dmem.s3a_tbl = me->data_ptr;
2811 if (me->vmem_size) {
2812 me->data.vmem.s3a_tbl_hi = me->data_ptr + me->dmem_size;
2813 me->data.vmem.s3a_tbl_lo = me->data_ptr + me->dmem_size + me->vmem_size;
2816 me->data_hmem.rgby_tbl = me->data_ptr + me->dmem_size + 2 * me->vmem_size;
2820 IA_CSS_LEAVE("return=%p", me);
2825 ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me)
2828 hmm_free(me->data_ptr);
2833 struct ia_css_isp_skc_dvs_statistics *ia_css_skc_dvs_statistics_allocate(void)
2838 struct ia_css_metadata *
2839 ia_css_metadata_allocate(const struct ia_css_metadata_info *metadata_info)
2841 struct ia_css_metadata *md = NULL;
2845 if (metadata_info->size == 0)
2848 md = sh_css_malloc(sizeof(*md));
2852 md->info = *metadata_info;
2854 md->address = mmgr_malloc(metadata_info->size);
2855 if (md->address == mmgr_NULL)
2858 IA_CSS_LEAVE("return=%p", md);
2862 ia_css_metadata_free(md);
2863 IA_CSS_LEAVE("return=%p", NULL);
2868 ia_css_metadata_free(struct ia_css_metadata *me)
2871 /* The enter and leave macros are placed inside
2872 * the condition to avoid false logging of metadata
2873 * free events when metadata is disabled.
2874 * We found this to be confusing during development
2876 IA_CSS_ENTER("me=%p", me);
2877 hmm_free(me->address);
2879 IA_CSS_LEAVE("void");
2884 ia_css_metadata_free_multiple(unsigned int num_bufs, struct ia_css_metadata **bufs)
2889 for (i = 0; i < num_bufs; i++)
2890 ia_css_metadata_free(bufs[i]);
2894 unsigned g_param_buffer_dequeue_count = 0;
2895 unsigned g_param_buffer_enqueue_count = 0;
2898 ia_css_stream_isp_parameters_init(struct ia_css_stream *stream)
2900 enum ia_css_err err = IA_CSS_SUCCESS;
2902 struct sh_css_ddr_address_map *ddr_ptrs;
2903 struct sh_css_ddr_address_map_size *ddr_ptrs_size;
2904 struct ia_css_isp_parameters *params;
2906 assert(stream != NULL);
2907 IA_CSS_ENTER_PRIVATE("void");
2909 if (stream == NULL) {
2910 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
2911 return IA_CSS_ERR_INVALID_ARGUMENTS;
2913 /* TMP: tracking of paramsets */
2914 g_param_buffer_dequeue_count = 0;
2915 g_param_buffer_enqueue_count = 0;
2917 stream->per_frame_isp_params_configs = NULL;
2918 err = sh_css_create_isp_params(stream,
2919 &stream->isp_params_configs);
2920 if(err != IA_CSS_SUCCESS)
2923 params = stream->isp_params_configs;
2924 if (!sh_css_init_isp_params_from_global(stream, params, true, NULL)) {
2925 /* we do not return the error immediately to enable internal
2926 * firmware feature testing */
2927 err = IA_CSS_ERR_INVALID_ARGUMENTS;
2930 ddr_ptrs = ¶ms->ddr_ptrs;
2931 ddr_ptrs_size = ¶ms->ddr_ptrs_size;
2933 /* create per pipe reference to general ddr_ptrs */
2934 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
2935 ref_sh_css_ddr_address_map(ddr_ptrs, ¶ms->pipe_ddr_ptrs[i]);
2936 params->pipe_ddr_ptrs_size[i] = *ddr_ptrs_size;
2940 IA_CSS_LEAVE_ERR_PRIVATE(err);
2945 ia_css_set_sdis_config(
2946 struct ia_css_isp_parameters *params,
2947 const struct ia_css_dvs_coefficients *dvs_coefs)
2949 ia_css_set_sdis_horicoef_config(params, dvs_coefs);
2950 ia_css_set_sdis_vertcoef_config(params, dvs_coefs);
2951 ia_css_set_sdis_horiproj_config(params, dvs_coefs);
2952 ia_css_set_sdis_vertproj_config(params, dvs_coefs);
2956 ia_css_set_sdis2_config(
2957 struct ia_css_isp_parameters *params,
2958 const struct ia_css_dvs2_coefficients *dvs2_coefs)
2960 ia_css_set_sdis2_horicoef_config(params, dvs2_coefs);
2961 ia_css_set_sdis2_vertcoef_config(params, dvs2_coefs);
2962 ia_css_set_sdis2_horiproj_config(params, dvs2_coefs);
2963 ia_css_set_sdis2_vertproj_config(params, dvs2_coefs);
2966 static enum ia_css_err
2967 sh_css_create_isp_params(struct ia_css_stream *stream,
2968 struct ia_css_isp_parameters **isp_params_out)
2972 struct sh_css_ddr_address_map *ddr_ptrs;
2973 struct sh_css_ddr_address_map_size *ddr_ptrs_size;
2974 enum ia_css_err err = IA_CSS_SUCCESS;
2976 struct ia_css_isp_parameters *params =
2977 sh_css_malloc(sizeof(struct ia_css_isp_parameters));
2981 *isp_params_out = NULL;
2982 err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
2983 IA_CSS_ERROR("%s:%d error: cannot allocate memory", __FILE__, __LINE__);
2984 IA_CSS_LEAVE_ERR_PRIVATE(err);
2987 memset(params, 0, sizeof(struct ia_css_isp_parameters));
2990 ddr_ptrs = ¶ms->ddr_ptrs;
2991 ddr_ptrs_size = ¶ms->ddr_ptrs_size;
2993 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
2994 memset(¶ms->pipe_ddr_ptrs[i], 0,
2995 sizeof(params->pipe_ddr_ptrs[i]));
2996 memset(¶ms->pipe_ddr_ptrs_size[i], 0,
2997 sizeof(params->pipe_ddr_ptrs_size[i]));
3000 memset(ddr_ptrs, 0, sizeof(*ddr_ptrs));
3001 memset(ddr_ptrs_size, 0, sizeof(*ddr_ptrs_size));
3003 params_size = sizeof(params->uds);
3004 ddr_ptrs_size->isp_param = params_size;
3005 ddr_ptrs->isp_param =
3006 ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER,
3007 mmgr_malloc(params_size));
3008 succ &= (ddr_ptrs->isp_param != mmgr_NULL);
3010 ddr_ptrs_size->macc_tbl = sizeof(struct ia_css_macc_table);
3011 ddr_ptrs->macc_tbl =
3012 ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER,
3013 mmgr_malloc(sizeof(struct ia_css_macc_table)));
3014 succ &= (ddr_ptrs->macc_tbl != mmgr_NULL);
3016 *isp_params_out = params;
3021 sh_css_init_isp_params_from_global(struct ia_css_stream *stream,
3022 struct ia_css_isp_parameters *params,
3023 bool use_default_config,
3024 struct ia_css_pipe *pipe_in)
3028 bool is_dp_10bpp = true;
3029 unsigned isp_pipe_version = ia_css_pipe_get_isp_pipe_version(stream->pipes[0]);
3030 struct ia_css_isp_parameters *stream_params = stream->isp_params_configs;
3032 if (!use_default_config && !stream_params) {
3037 params->output_frame = NULL;
3038 params->isp_parameters_id = 0;
3040 if (use_default_config)
3042 ia_css_set_xnr3_config(params, &default_xnr3_config);
3044 sh_css_set_nr_config(params, &default_nr_config);
3045 sh_css_set_ee_config(params, &default_ee_config);
3046 if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1)
3047 sh_css_set_macc_table(params, &default_macc_table);
3048 else if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2)
3049 sh_css_set_macc_table(params, &default_macc2_table);
3050 sh_css_set_gamma_table(params, &default_gamma_table);
3051 sh_css_set_ctc_table(params, &default_ctc_table);
3052 sh_css_set_baa_config(params, &default_baa_config);
3053 sh_css_set_dz_config(params, &default_dz_config);
3054 /* ------ deprecated(bz675) : from ------ */
3055 sh_css_set_shading_settings(params, &default_shading_settings);
3056 /* ------ deprecated(bz675) : to ------ */
3058 ia_css_set_s3a_config(params, &default_3a_config);
3059 ia_css_set_wb_config(params, &default_wb_config);
3060 ia_css_set_csc_config(params, &default_cc_config);
3061 ia_css_set_tnr_config(params, &default_tnr_config);
3062 ia_css_set_ob_config(params, &default_ob_config);
3063 ia_css_set_dp_config(params, &default_dp_config);
3065 ia_css_set_param_exceptions(pipe_in, params);
3068 for (i = 0; i < stream->num_pipes; i++) {
3069 if (IA_CSS_SUCCESS == sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp)) {
3070 /* set the return value as false if both DPC and
3071 * BDS is enabled by the user. But we do not return
3072 * the value immediately to enable internal firmware
3073 * feature testing. */
3075 sh_css_set_dp_config(stream->pipes[i], params, &default_dp_10bpp_config);
3077 sh_css_set_dp_config(stream->pipes[i], params, &default_dp_config);
3084 ia_css_set_param_exceptions(stream->pipes[i], params);
3088 ia_css_set_de_config(params, &default_de_config);
3089 ia_css_set_gc_config(params, &default_gc_config);
3090 ia_css_set_anr_config(params, &default_anr_config);
3091 ia_css_set_anr2_config(params, &default_anr_thres);
3092 ia_css_set_ce_config(params, &default_ce_config);
3093 ia_css_set_xnr_table_config(params, &default_xnr_table);
3094 ia_css_set_ecd_config(params, &default_ecd_config);
3095 ia_css_set_ynr_config(params, &default_ynr_config);
3096 ia_css_set_fc_config(params, &default_fc_config);
3097 ia_css_set_cnr_config(params, &default_cnr_config);
3098 ia_css_set_macc_config(params, &default_macc_config);
3099 ia_css_set_ctc_config(params, &default_ctc_config);
3100 ia_css_set_aa_config(params, &default_aa_config);
3101 ia_css_set_r_gamma_config(params, &default_r_gamma_table);
3102 ia_css_set_g_gamma_config(params, &default_g_gamma_table);
3103 ia_css_set_b_gamma_config(params, &default_b_gamma_table);
3104 ia_css_set_yuv2rgb_config(params, &default_yuv2rgb_cc_config);
3105 ia_css_set_rgb2yuv_config(params, &default_rgb2yuv_cc_config);
3106 ia_css_set_xnr_config(params, &default_xnr_config);
3107 ia_css_set_sdis_config(params, &default_sdis_config);
3108 ia_css_set_sdis2_config(params, &default_sdis2_config);
3109 ia_css_set_formats_config(params, &default_formats_config);
3111 params->fpn_config.data = NULL;
3112 params->config_changed[IA_CSS_FPN_ID] = true;
3113 params->fpn_config.enabled = 0;
3115 params->motion_config = default_motion_config;
3116 params->motion_config_changed = true;
3118 params->morph_table = NULL;
3119 params->morph_table_changed = true;
3121 params->sc_table = NULL;
3122 params->sc_table_changed = true;
3123 params->sc_table_dirty = false;
3124 params->sc_table_last_pipe_num = 0;
3126 ia_css_sdis2_clear_coefficients(¶ms->dvs2_coefs);
3127 params->dvs2_coef_table_changed = true;
3129 ia_css_sdis_clear_coefficients(¶ms->dvs_coefs);
3130 params->dis_coef_table_changed = true;
3132 ia_css_tnr3_set_default_config(¶ms->tnr3_config);
3137 ia_css_set_xnr3_config(params, &stream_params->xnr3_config);
3139 sh_css_set_nr_config(params, &stream_params->nr_config);
3140 sh_css_set_ee_config(params, &stream_params->ee_config);
3141 if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1)
3142 sh_css_set_macc_table(params, &stream_params->macc_table);
3143 else if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2)
3144 sh_css_set_macc_table(params, &stream_params->macc_table);
3145 sh_css_set_gamma_table(params, &stream_params->gc_table);
3146 sh_css_set_ctc_table(params, &stream_params->ctc_table);
3147 sh_css_set_baa_config(params, &stream_params->bds_config);
3148 sh_css_set_dz_config(params, &stream_params->dz_config);
3149 /* ------ deprecated(bz675) : from ------ */
3150 sh_css_set_shading_settings(params, &stream_params->shading_settings);
3151 /* ------ deprecated(bz675) : to ------ */
3153 ia_css_set_s3a_config(params, &stream_params->s3a_config);
3154 ia_css_set_wb_config(params, &stream_params->wb_config);
3155 ia_css_set_csc_config(params, &stream_params->cc_config);
3156 ia_css_set_tnr_config(params, &stream_params->tnr_config);
3157 ia_css_set_ob_config(params, &stream_params->ob_config);
3158 ia_css_set_dp_config(params, &stream_params->dp_config);
3159 ia_css_set_de_config(params, &stream_params->de_config);
3160 ia_css_set_gc_config(params, &stream_params->gc_config);
3161 ia_css_set_anr_config(params, &stream_params->anr_config);
3162 ia_css_set_anr2_config(params, &stream_params->anr_thres);
3163 ia_css_set_ce_config(params, &stream_params->ce_config);
3164 ia_css_set_xnr_table_config(params, &stream_params->xnr_table);
3165 ia_css_set_ecd_config(params, &stream_params->ecd_config);
3166 ia_css_set_ynr_config(params, &stream_params->ynr_config);
3167 ia_css_set_fc_config(params, &stream_params->fc_config);
3168 ia_css_set_cnr_config(params, &stream_params->cnr_config);
3169 ia_css_set_macc_config(params, &stream_params->macc_config);
3170 ia_css_set_ctc_config(params, &stream_params->ctc_config);
3171 ia_css_set_aa_config(params, &stream_params->aa_config);
3172 ia_css_set_r_gamma_config(params, &stream_params->r_gamma_table);
3173 ia_css_set_g_gamma_config(params, &stream_params->g_gamma_table);
3174 ia_css_set_b_gamma_config(params, &stream_params->b_gamma_table);
3175 ia_css_set_yuv2rgb_config(params, &stream_params->yuv2rgb_cc_config);
3176 ia_css_set_rgb2yuv_config(params, &stream_params->rgb2yuv_cc_config);
3177 ia_css_set_xnr_config(params, &stream_params->xnr_config);
3178 ia_css_set_formats_config(params, &stream_params->formats_config);
3180 for (i = 0; i < stream->num_pipes; i++) {
3181 if (IA_CSS_SUCCESS ==
3182 sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp)) {
3183 /* set the return value as false if both DPC and
3184 * BDS is enabled by the user. But we do not return
3185 * the value immediately to enable internal firmware
3186 * feature testing. */
3188 retval = !is_dp_10bpp;
3197 if (stream->pipes[i]->mode < IA_CSS_PIPE_ID_NUM) {
3198 sh_css_set_dp_config(stream->pipes[i], params,
3199 &stream_params->pipe_dp_config[stream->pipes[i]->mode]);
3200 ia_css_set_param_exceptions(stream->pipes[i], params);
3209 ia_css_set_param_exceptions(pipe_in, params);
3212 params->fpn_config.data = stream_params->fpn_config.data;
3213 params->config_changed[IA_CSS_FPN_ID] = stream_params->config_changed[IA_CSS_FPN_ID];
3214 params->fpn_config.enabled = stream_params->fpn_config.enabled;
3216 sh_css_set_motion_vector(params, &stream_params->motion_config);
3217 sh_css_set_morph_table(params, stream_params->morph_table);
3219 if (stream_params->sc_table) {
3220 sh_css_update_shading_table_status(pipe_in, params);
3221 sh_css_set_shading_table(stream, params, stream_params->sc_table);
3224 params->sc_table = NULL;
3225 params->sc_table_changed = true;
3226 params->sc_table_dirty = false;
3227 params->sc_table_last_pipe_num = 0;
3230 /* Only IA_CSS_PIPE_ID_VIDEO & IA_CSS_PIPE_ID_CAPTURE will support dvs_6axis_config*/
3231 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
3232 if (stream_params->pipe_dvs_6axis_config[i]) {
3233 if (params->pipe_dvs_6axis_config[i]) {
3234 copy_dvs_6axis_table(params->pipe_dvs_6axis_config[i],
3235 stream_params->pipe_dvs_6axis_config[i]);
3237 params->pipe_dvs_6axis_config[i] =
3238 generate_dvs_6axis_table_from_config(stream_params->pipe_dvs_6axis_config[i]);
3242 ia_css_set_sdis_config(params, &stream_params->dvs_coefs);
3243 params->dis_coef_table_changed = stream_params->dis_coef_table_changed;
3245 ia_css_set_sdis2_config(params, &stream_params->dvs2_coefs);
3246 params->dvs2_coef_table_changed = stream_params->dvs2_coef_table_changed;
3247 params->sensor_binning = stream_params->sensor_binning;
3255 sh_css_params_init(void)
3259 IA_CSS_ENTER_PRIVATE("void");
3261 /* TMP: tracking of paramsets */
3262 g_param_buffer_dequeue_count = 0;
3263 g_param_buffer_enqueue_count = 0;
3265 for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++) {
3266 for (i = 0; i < SH_CSS_MAX_STAGES; i++) {
3267 xmem_sp_stage_ptrs[p][i] =
3268 ia_css_refcount_increment(-1,
3270 sizeof(struct sh_css_sp_stage)));
3271 xmem_isp_stage_ptrs[p][i] =
3272 ia_css_refcount_increment(-1,
3274 sizeof(struct sh_css_isp_stage)));
3276 if ((xmem_sp_stage_ptrs[p][i] == mmgr_NULL) ||
3277 (xmem_isp_stage_ptrs[p][i] == mmgr_NULL)) {
3278 sh_css_params_uninit();
3279 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
3280 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
3285 ia_css_config_gamma_table();
3286 ia_css_config_ctc_table();
3287 ia_css_config_rgb_gamma_tables();
3288 ia_css_config_xnr_table();
3290 sp_ddr_ptrs = ia_css_refcount_increment(-1, mmgr_calloc(1,
3291 CEIL_MUL(sizeof(struct sh_css_ddr_address_map),
3292 HIVE_ISP_DDR_WORD_BYTES)));
3293 xmem_sp_group_ptrs = ia_css_refcount_increment(-1, mmgr_calloc(1,
3294 sizeof(struct sh_css_sp_group)));
3296 if ((sp_ddr_ptrs == mmgr_NULL) ||
3297 (xmem_sp_group_ptrs == mmgr_NULL)) {
3299 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
3300 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
3302 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS);
3303 return IA_CSS_SUCCESS;
3306 static void host_lut_store(const void *lut)
3310 for (i = 0; i < N_GDC_ID; i++)
3311 gdc_lut_store((gdc_ID_t)i, (const int (*)[HRT_GDC_N]) lut);
3314 /* Note that allocation is in ipu address space. */
3315 inline hrt_vaddress sh_css_params_alloc_gdc_lut(void)
3317 return mmgr_malloc(sizeof(zoom_table));
3320 inline void sh_css_params_free_gdc_lut(hrt_vaddress addr)
3322 if (addr != mmgr_NULL)
3326 enum ia_css_err ia_css_pipe_set_bci_scaler_lut(struct ia_css_pipe *pipe,
3329 enum ia_css_err err = IA_CSS_SUCCESS;
3333 bool stream_started = false;
3335 IA_CSS_ENTER("pipe=%p lut=%p", pipe, lut);
3337 if (lut == NULL || pipe == NULL) {
3338 err = IA_CSS_ERR_INVALID_ARGUMENTS;
3339 IA_CSS_LEAVE("err=%d", err);
3343 /* If the pipe belongs to a stream and the stream has started, it is not
3344 * safe to store lut to gdc HW. If pipe->stream is NULL, then no stream is
3345 * created with this pipe, so it is safe to do this operation as long as
3346 * ia_css_init() has been called. */
3347 if (pipe->stream && pipe->stream->started) {
3348 ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
3349 "unable to set scaler lut since stream has started\n");
3353 stream_started = true;
3355 err = IA_CSS_ERR_NOT_SUPPORTED;
3358 /* Free any existing tables. */
3359 sh_css_params_free_gdc_lut(pipe->scaler_pp_lut);
3360 pipe->scaler_pp_lut = mmgr_NULL;
3364 pipe->scaler_pp_lut = mmgr_malloc(sizeof(zoom_table));
3366 if (!stream_started) {
3367 pipe->scaler_pp_lut = sh_css_params_alloc_gdc_lut();
3369 if (pipe->scaler_pp_lut == mmgr_NULL) {
3371 IA_CSS_LEAVE("lut(%u) err=%d", pipe->scaler_pp_lut, err);
3372 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
3374 ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
3375 "unable to allocate scaler_pp_lut\n");
3376 err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
3378 gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])lut,
3379 interleaved_lut_temp);
3380 mmgr_store(pipe->scaler_pp_lut,
3381 (int *)interleaved_lut_temp,
3382 sizeof(zoom_table));
3387 gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])lut, interleaved_lut_temp);
3388 mmgr_store(pipe->scaler_pp_lut, (int *)interleaved_lut_temp,
3389 sizeof(zoom_table));
3393 IA_CSS_LEAVE("lut(%u) err=%d", pipe->scaler_pp_lut, err);
3397 /* if pipe is NULL, returns default lut addr. */
3398 hrt_vaddress sh_css_pipe_get_pp_gdc_lut(const struct ia_css_pipe *pipe)
3400 assert(pipe != NULL);
3402 if (pipe->scaler_pp_lut != mmgr_NULL)
3403 return pipe->scaler_pp_lut;
3405 return sh_css_params_get_default_gdc_lut();
3408 enum ia_css_err sh_css_params_map_and_store_default_gdc_lut(void)
3410 enum ia_css_err err = IA_CSS_SUCCESS;
3412 IA_CSS_ENTER_PRIVATE("void");
3414 /* Is table already mapped? Nothing to do if it is mapped. */
3415 if (default_gdc_lut != mmgr_NULL)
3418 host_lut_store((void *)zoom_table);
3421 default_gdc_lut = mmgr_malloc(sizeof(zoom_table));
3423 default_gdc_lut = sh_css_params_alloc_gdc_lut();
3425 if (default_gdc_lut == mmgr_NULL)
3426 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
3428 gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])zoom_table,
3429 interleaved_lut_temp);
3430 mmgr_store(default_gdc_lut, (int *)interleaved_lut_temp,
3431 sizeof(zoom_table));
3433 IA_CSS_LEAVE_PRIVATE("lut(%u) err=%d", default_gdc_lut, err);
3437 void sh_css_params_free_default_gdc_lut(void)
3439 IA_CSS_ENTER_PRIVATE("void");
3441 sh_css_params_free_gdc_lut(default_gdc_lut);
3442 default_gdc_lut = mmgr_NULL;
3444 IA_CSS_LEAVE_PRIVATE("void");
3448 hrt_vaddress sh_css_params_get_default_gdc_lut(void)
3450 return default_gdc_lut;
3453 static void free_param_set_callback(
3456 IA_CSS_ENTER_PRIVATE("void");
3458 free_ia_css_isp_parameter_set_info(ptr);
3460 IA_CSS_LEAVE_PRIVATE("void");
3463 static void free_buffer_callback(
3466 IA_CSS_ENTER_PRIVATE("void");
3470 IA_CSS_LEAVE_PRIVATE("void");
3474 sh_css_param_clear_param_sets(void)
3476 IA_CSS_ENTER_PRIVATE("void");
3478 ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_SET_POOL, &free_param_set_callback);
3480 IA_CSS_LEAVE_PRIVATE("void");
3484 * MW: we can define hmm_free() to return a NULL
3485 * then you can write ptr = hmm_free(ptr);
3487 #define safe_free(id, x) \
3489 ia_css_refcount_decrement(id, x); \
3493 static void free_map(struct sh_css_ddr_address_map *map)
3497 hrt_vaddress *addrs = (hrt_vaddress *)map;
3499 IA_CSS_ENTER_PRIVATE("void");
3502 for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/
3503 sizeof(size_t)); i++) {
3504 if (addrs[i] == mmgr_NULL)
3506 safe_free(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]);
3509 IA_CSS_LEAVE_PRIVATE("void");
3513 ia_css_stream_isp_parameters_uninit(struct ia_css_stream *stream)
3516 struct ia_css_isp_parameters *params = stream->isp_params_configs;
3517 struct ia_css_isp_parameters *per_frame_params =
3518 stream->per_frame_isp_params_configs;
3520 IA_CSS_ENTER_PRIVATE("void");
3521 if (params == NULL) {
3522 IA_CSS_LEAVE_PRIVATE("isp_param_configs is NULL");
3526 /* free existing ddr_ptr maps */
3527 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++)
3529 free_map(¶ms->pipe_ddr_ptrs[i]);
3530 if (per_frame_params)
3531 free_map(&per_frame_params->pipe_ddr_ptrs[i]);
3532 /* Free up theDVS table memory blocks before recomputing new table */
3533 if (params->pipe_dvs_6axis_config[i])
3534 free_dvs_6axis_table(&(params->pipe_dvs_6axis_config[i]));
3535 if (per_frame_params && per_frame_params->pipe_dvs_6axis_config[i])
3536 free_dvs_6axis_table(&(per_frame_params->pipe_dvs_6axis_config[i]));
3538 free_map(¶ms->ddr_ptrs);
3539 if (per_frame_params)
3540 free_map(&per_frame_params->ddr_ptrs);
3542 if (params->fpn_config.data) {
3543 sh_css_free(params->fpn_config.data);
3544 params->fpn_config.data = NULL;
3547 /* Free up sc_config (temporal shading table) if it is allocated. */
3548 if (params->sc_config) {
3549 ia_css_shading_table_free(params->sc_config);
3550 params->sc_config = NULL;
3552 if (per_frame_params) {
3553 if (per_frame_params->sc_config) {
3554 ia_css_shading_table_free(per_frame_params->sc_config);
3555 per_frame_params->sc_config = NULL;
3559 sh_css_free(params);
3560 if (per_frame_params)
3561 sh_css_free(per_frame_params);
3562 stream->isp_params_configs = NULL;
3563 stream->per_frame_isp_params_configs = NULL;
3565 IA_CSS_LEAVE_PRIVATE("void");
3569 sh_css_params_uninit(void)
3573 IA_CSS_ENTER_PRIVATE("void");
3575 ia_css_refcount_decrement(-1, sp_ddr_ptrs);
3576 sp_ddr_ptrs = mmgr_NULL;
3577 ia_css_refcount_decrement(-1, xmem_sp_group_ptrs);
3578 xmem_sp_group_ptrs = mmgr_NULL;
3580 for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++)
3581 for (i = 0; i < SH_CSS_MAX_STAGES; i++) {
3582 ia_css_refcount_decrement(-1, xmem_sp_stage_ptrs[p][i]);
3583 xmem_sp_stage_ptrs[p][i] = mmgr_NULL;
3584 ia_css_refcount_decrement(-1, xmem_isp_stage_ptrs[p][i]);
3585 xmem_isp_stage_ptrs[p][i] = mmgr_NULL;
3588 /* go through the pools to clear references */
3589 ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_SET_POOL, &free_param_set_callback);
3590 ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_BUFFER, &free_buffer_callback);
3591 ia_css_refcount_clear(-1, &free_buffer_callback);
3593 IA_CSS_LEAVE_PRIVATE("void");
3596 static struct ia_css_host_data *
3597 convert_allocate_morph_plane(
3598 unsigned short *data,
3600 unsigned int height,
3601 unsigned int aligned_width)
3603 unsigned int i, j, padding, w;
3604 struct ia_css_host_data *me;
3605 unsigned int isp_data_size;
3606 uint16_t *isp_data_ptr;
3608 IA_CSS_ENTER_PRIVATE("void");
3610 /* currently we don't have morph table interpolation yet,
3611 * so we allow a wider table to be used. This will be removed
3613 if (width > aligned_width) {
3617 padding = aligned_width - width;
3620 isp_data_size = height * (w + padding) * sizeof(uint16_t);
3622 me = ia_css_host_data_allocate((size_t) isp_data_size);
3625 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
3629 isp_data_ptr = (uint16_t *)me->address;
3631 memset(isp_data_ptr, 0, (size_t)isp_data_size);
3633 for (i = 0; i < height; i++) {
3634 for (j = 0; j < w; j++)
3635 *isp_data_ptr++ = (uint16_t)data[j];
3636 isp_data_ptr += padding;
3640 IA_CSS_LEAVE_PRIVATE("void");
3644 static enum ia_css_err
3646 unsigned short *data,
3648 unsigned int height,
3650 unsigned int aligned_width)
3652 struct ia_css_host_data *isp_data;
3654 assert(dest != mmgr_NULL);
3656 isp_data = convert_allocate_morph_plane(data, width, height, aligned_width);
3658 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
3659 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
3661 ia_css_params_store_ia_css_host_data(dest, isp_data);
3663 ia_css_host_data_free(isp_data);
3664 return IA_CSS_SUCCESS;
3667 static void sh_css_update_isp_params_to_ddr(
3668 struct ia_css_isp_parameters *params,
3669 hrt_vaddress ddr_ptr)
3671 size_t size = sizeof(params->uds);
3673 IA_CSS_ENTER_PRIVATE("void");
3675 assert(params != NULL);
3677 mmgr_store(ddr_ptr, &(params->uds), size);
3678 IA_CSS_LEAVE_PRIVATE("void");
3681 static void sh_css_update_isp_mem_params_to_ddr(
3682 const struct ia_css_binary *binary,
3683 hrt_vaddress ddr_mem_ptr,
3685 enum ia_css_isp_memories mem)
3687 const struct ia_css_host_data *params;
3689 IA_CSS_ENTER_PRIVATE("void");
3691 params = ia_css_isp_param_get_mem_init(&binary->mem_params, IA_CSS_PARAM_CLASS_PARAM, mem);
3692 mmgr_store(ddr_mem_ptr, params->address, size);
3694 IA_CSS_LEAVE_PRIVATE("void");
3697 void ia_css_dequeue_param_buffers(/*unsigned int pipe_num*/ void)
3701 enum sh_css_queue_id param_queue_ids[3] = { IA_CSS_PARAMETER_SET_QUEUE_ID,
3702 IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID,
3703 SH_CSS_INVALID_QUEUE_ID};
3705 IA_CSS_ENTER_PRIVATE("void");
3707 if (!sh_css_sp_is_running()) {
3708 IA_CSS_LEAVE_PRIVATE("sp is not running");
3709 /* SP is not running. The queues are not valid */
3713 for (i = 0; SH_CSS_INVALID_QUEUE_ID != param_queue_ids[i]; i++) {
3714 cpy = (hrt_vaddress)0;
3715 /* clean-up old copy */
3716 while (IA_CSS_SUCCESS == ia_css_bufq_dequeue_buffer(param_queue_ids[i], (uint32_t *)&cpy)) {
3717 /* TMP: keep track of dequeued param set count
3719 g_param_buffer_dequeue_count++;
3720 ia_css_bufq_enqueue_psys_event(
3721 IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED,
3726 IA_CSS_LOG("dequeued param set %x from %d, release ref", cpy, 0);
3727 free_ia_css_isp_parameter_set_info(cpy);
3728 cpy = (hrt_vaddress)0;
3732 IA_CSS_LEAVE_PRIVATE("void");
3736 process_kernel_parameters(unsigned int pipe_id,
3737 struct ia_css_pipeline_stage *stage,
3738 struct ia_css_isp_parameters *params,
3739 unsigned int isp_pipe_version,
3740 unsigned int raw_bit_depth)
3744 (void)isp_pipe_version;
3745 (void)raw_bit_depth;
3747 sh_css_enable_pipeline(stage->binary);
3749 if (params->config_changed[IA_CSS_OB_ID]) {
3750 ia_css_ob_configure(¶ms->stream_configs.ob,
3751 isp_pipe_version, raw_bit_depth);
3753 if (params->config_changed[IA_CSS_S3A_ID]) {
3754 ia_css_s3a_configure(raw_bit_depth);
3756 /* Copy stage uds parameters to config, since they can differ per stage.
3758 params->crop_config.crop_pos = params->uds[stage->stage_num].crop_pos;
3759 params->uds_config.crop_pos = params->uds[stage->stage_num].crop_pos;
3760 params->uds_config.uds = params->uds[stage->stage_num].uds;
3761 /* Call parameter process functions for all kernels */
3762 /* Skip SC, since that is called on a temp sc table */
3763 for (param_id = 0; param_id < IA_CSS_NUM_PARAMETER_IDS; param_id++) {
3764 if (param_id == IA_CSS_SC_ID) continue;
3765 if (params->config_changed[param_id])
3766 ia_css_kernel_process_param[param_id](pipe_id, stage, params);
3771 sh_css_param_update_isp_params(struct ia_css_pipe *curr_pipe,
3772 struct ia_css_isp_parameters *params,
3774 struct ia_css_pipe *pipe_in)
3776 enum ia_css_err err = IA_CSS_SUCCESS;
3779 unsigned int raw_bit_depth = 10;
3780 unsigned int isp_pipe_version = SH_CSS_ISP_PIPE_VERSION_1;
3781 bool acc_cluster_params_changed = false;
3782 unsigned int thread_id, pipe_num;
3784 (void)acc_cluster_params_changed;
3786 assert(curr_pipe != NULL);
3788 IA_CSS_ENTER_PRIVATE("pipe=%p, isp_parameters_id=%d", pipe_in, params->isp_parameters_id);
3789 raw_bit_depth = ia_css_stream_input_format_bits_per_pixel(curr_pipe->stream);
3791 /* now make the map available to the sp */
3793 IA_CSS_LEAVE_ERR_PRIVATE(err);
3796 /* enqueue a copies of the mem_map to
3797 the designated pipelines */
3798 for (i = 0; i < curr_pipe->stream->num_pipes; i++) {
3799 struct ia_css_pipe *pipe;
3800 struct sh_css_ddr_address_map *cur_map;
3801 struct sh_css_ddr_address_map_size *cur_map_size;
3802 struct ia_css_isp_parameter_set_info isp_params_info;
3803 struct ia_css_pipeline *pipeline;
3804 struct ia_css_pipeline_stage *stage;
3806 enum sh_css_queue_id queue_id;
3809 pipe = curr_pipe->stream->pipes[i];
3810 pipeline = ia_css_pipe_get_pipeline(pipe);
3811 pipe_num = ia_css_pipe_get_pipe_num(pipe);
3812 isp_pipe_version = ia_css_pipe_get_isp_pipe_version(pipe);
3813 ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id);
3815 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
3816 ia_css_query_internal_queue_id(params->output_frame
3817 ? IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET
3818 : IA_CSS_BUFFER_TYPE_PARAMETER_SET,
3819 thread_id, &queue_id);
3821 ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_PARAMETER_SET, thread_id, &queue_id);
3823 if (!sh_css_sp_is_running()) {
3824 /* SP is not running. The queues are not valid */
3825 err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
3828 cur_map = ¶ms->pipe_ddr_ptrs[pipeline->pipe_id];
3829 cur_map_size = ¶ms->pipe_ddr_ptrs_size[pipeline->pipe_id];
3831 /* TODO: Normally, zoom and motion parameters shouldn't
3832 * be part of "isp_params" as it is resolution/pipe dependant
3833 * Therefore, move the zoom config elsewhere (e.g. shading
3834 * table can be taken as an example! @GC
3837 /* we have to do this per pipeline because */
3838 /* the processing is a.o. resolution dependent */
3839 err = ia_css_process_zoom_and_motion(params,
3841 if (err != IA_CSS_SUCCESS)
3844 /* check if to actually update the parameters for this pipe */
3845 /* When API change is implemented making good distinction between
3846 * stream config and pipe config this skipping code can be moved out of the #ifdef */
3847 if (pipe_in && (pipe != pipe_in)) {
3848 IA_CSS_LOG("skipping pipe %p", pipe);
3852 /* BZ 125915, should be moved till after "update other buff" */
3853 /* update the other buffers to the pipe specific copies */
3854 for (stage = pipeline->stages; stage; stage = stage->next) {
3857 if (!stage || !stage->binary)
3860 process_kernel_parameters(pipeline->pipe_id,
3862 isp_pipe_version, raw_bit_depth);
3864 err = sh_css_params_write_to_ddr_internal(
3872 if (err != IA_CSS_SUCCESS)
3874 for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) {
3875 params->isp_mem_params_changed
3876 [pipeline->pipe_id][stage->stage_num][mem] = false;
3879 if (err != IA_CSS_SUCCESS)
3881 /* update isp_params to pipe specific copies */
3882 if (params->isp_params_changed) {
3883 reallocate_buffer(&cur_map->isp_param,
3884 &cur_map_size->isp_param,
3885 cur_map_size->isp_param,
3888 if (err != IA_CSS_SUCCESS)
3890 sh_css_update_isp_params_to_ddr(params, cur_map->isp_param);
3893 /* last make referenced copy */
3894 err = ref_sh_css_ddr_address_map(
3896 &isp_params_info.mem_map);
3897 if (err != IA_CSS_SUCCESS)
3900 /* Update Parameters ID */
3901 isp_params_info.isp_parameters_id = params->isp_parameters_id;
3903 /* Update output frame pointer */
3904 isp_params_info.output_frame_ptr =
3905 (params->output_frame) ? params->output_frame->data : mmgr_NULL;
3907 /* now write the copy to ddr */
3908 err = write_ia_css_isp_parameter_set_info_to_ddr(&isp_params_info, &cpy);
3909 if (err != IA_CSS_SUCCESS)
3912 /* enqueue the set to sp */
3913 IA_CSS_LOG("queue param set %x to %d", cpy, thread_id);
3915 err = ia_css_bufq_enqueue_buffer(thread_id, queue_id, (uint32_t)cpy);
3916 if (IA_CSS_SUCCESS != err) {
3917 free_ia_css_isp_parameter_set_info(cpy);
3918 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
3919 IA_CSS_LOG("pfp: FAILED to add config id %d for OF %d to q %d on thread %d",
3920 isp_params_info.isp_parameters_id,
3921 isp_params_info.output_frame_ptr,
3922 queue_id, thread_id);
3927 /* TMP: check discrepancy between nr of enqueued
3928 * parameter sets and dequeued sets
3930 g_param_buffer_enqueue_count++;
3931 assert(g_param_buffer_enqueue_count < g_param_buffer_dequeue_count+50);
3933 ia_css_save_latest_paramset_ptr(pipe, cpy);
3936 * Tell the SP which queues are not empty,
3937 * by sending the software event.
3939 if (!sh_css_sp_is_running()) {
3940 /* SP is not running. The queues are not valid */
3941 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE);
3942 return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
3944 ia_css_bufq_enqueue_psys_event(
3945 IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED,
3949 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
3950 IA_CSS_LOG("pfp: added config id %d for OF %d to q %d on thread %d",
3951 isp_params_info.isp_parameters_id,
3952 isp_params_info.output_frame_ptr,
3953 queue_id, thread_id);
3956 /* clean-up old copy */
3957 ia_css_dequeue_param_buffers(/*pipe_num*/);
3958 params->pipe_dvs_6axis_config_changed[pipeline->pipe_id] = false;
3959 } /* end for each 'active' pipeline */
3960 /* clear the changed flags after all params
3961 for all pipelines have been updated */
3962 params->isp_params_changed = false;
3963 params->sc_table_changed = false;
3964 params->dis_coef_table_changed = false;
3965 params->dvs2_coef_table_changed = false;
3966 params->morph_table_changed = false;
3967 params->dz_config_changed = false;
3968 params->motion_config_changed = false;
3969 /* ------ deprecated(bz675) : from ------ */
3970 params->shading_settings_changed = false;
3971 /* ------ deprecated(bz675) : to ------ */
3973 memset(¶ms->config_changed[0], 0, sizeof(params->config_changed));
3975 IA_CSS_LEAVE_ERR_PRIVATE(err);
3979 static enum ia_css_err
3980 sh_css_params_write_to_ddr_internal(
3981 struct ia_css_pipe *pipe,
3983 struct ia_css_isp_parameters *params,
3984 const struct ia_css_pipeline_stage *stage,
3985 struct sh_css_ddr_address_map *ddr_map,
3986 struct sh_css_ddr_address_map_size *ddr_map_size)
3988 enum ia_css_err err;
3989 const struct ia_css_binary *binary;
3993 bool buff_realloced;
3995 /* struct is > 128 bytes so it should not be on stack (see checkpatch) */
3996 static struct ia_css_macc_table converted_macc_table;
3998 IA_CSS_ENTER_PRIVATE("void");
3999 assert(params != NULL);
4000 assert(ddr_map != NULL);
4001 assert(ddr_map_size != NULL);
4002 assert(stage != NULL);
4004 binary = stage->binary;
4005 assert(binary != NULL);
4008 stage_num = stage->stage_num;
4010 if (binary->info->sp.enable.fpnr) {
4011 buff_realloced = reallocate_buffer(&ddr_map->fpn_tbl,
4012 &ddr_map_size->fpn_tbl,
4013 (size_t)(FPNTBL_BYTES(binary)),
4014 params->config_changed[IA_CSS_FPN_ID],
4016 if (err != IA_CSS_SUCCESS) {
4017 IA_CSS_LEAVE_ERR_PRIVATE(err);
4020 if (params->config_changed[IA_CSS_FPN_ID] || buff_realloced) {
4021 if (params->fpn_config.enabled) {
4022 err = store_fpntbl(params, ddr_map->fpn_tbl);
4023 if (err != IA_CSS_SUCCESS) {
4024 IA_CSS_LEAVE_ERR_PRIVATE(err);
4031 if (binary->info->sp.enable.sc) {
4032 uint32_t enable_conv = params->
4033 shading_settings.enable_shading_table_conversion;
4035 buff_realloced = reallocate_buffer(&ddr_map->sc_tbl,
4036 &ddr_map_size->sc_tbl,
4037 (size_t)(SCTBL_BYTES(binary)),
4038 params->sc_table_changed,
4040 if (err != IA_CSS_SUCCESS) {
4041 IA_CSS_LEAVE_ERR_PRIVATE(err);
4045 if (params->shading_settings_changed ||
4046 params->sc_table_changed || buff_realloced) {
4047 if (enable_conv == 0) {
4048 if (params->sc_table) {
4049 /* store the shading table to ddr */
4050 err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_table);
4051 if (err != IA_CSS_SUCCESS) {
4052 IA_CSS_LEAVE_ERR_PRIVATE(err);
4055 /* set sc_config to isp */
4056 params->sc_config = (struct ia_css_shading_table *)params->sc_table;
4057 ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params);
4058 params->sc_config = NULL;
4060 /* generate the identical shading table */
4061 if (params->sc_config) {
4062 ia_css_shading_table_free(params->sc_config);
4063 params->sc_config = NULL;
4066 sh_css_params_shading_id_table_generate(¶ms->sc_config, binary);
4068 sh_css_params_shading_id_table_generate(¶ms->sc_config,
4069 binary->sctbl_width_per_color, binary->sctbl_height);
4071 if (params->sc_config == NULL) {
4072 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
4073 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
4076 /* store the shading table to ddr */
4077 err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_config);
4078 if (err != IA_CSS_SUCCESS) {
4079 IA_CSS_LEAVE_ERR_PRIVATE(err);
4083 /* set sc_config to isp */
4084 ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params);
4086 /* free the shading table */
4087 ia_css_shading_table_free(params->sc_config);
4088 params->sc_config = NULL;
4090 } else { /* legacy */
4091 /* ------ deprecated(bz675) : from ------ */
4092 /* shading table is full resolution, reduce */
4093 if (params->sc_config) {
4094 ia_css_shading_table_free(params->sc_config);
4095 params->sc_config = NULL;
4097 prepare_shading_table(
4098 (const struct ia_css_shading_table *)params->sc_table,
4099 params->sensor_binning,
4101 binary, pipe->required_bds_factor);
4102 if (params->sc_config == NULL) {
4103 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
4104 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
4107 /* store the shading table to ddr */
4108 err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_config);
4109 if (err != IA_CSS_SUCCESS) {
4110 IA_CSS_LEAVE_ERR_PRIVATE(err);
4114 /* set sc_config to isp */
4115 ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params);
4117 /* free the shading table */
4118 ia_css_shading_table_free(params->sc_config);
4119 params->sc_config = NULL;
4120 /* ------ deprecated(bz675) : to ------ */
4125 /* DPC configuration is made pipe specific to allow flexibility in positioning of the
4126 * DPC kernel. The code below sets the pipe specific configuration to
4127 * individual binaries. */
4128 if (params->pipe_dpc_config_changed[pipe_id] && binary->info->sp.enable.dpc) {
4129 unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
4131 unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
4133 ia_css_dp_encode((struct sh_css_isp_dp_params *)
4134 &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
4135 ¶ms->pipe_dp_config[pipe_id], size);
4139 params->isp_params_changed = true;
4140 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true;
4144 if (params->config_changed[IA_CSS_MACC_ID] && binary->info->sp.enable.macc) {
4145 unsigned int i, j, idx;
4146 unsigned int idx_map[] = {
4147 0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8};
4149 for (i = 0; i < IA_CSS_MACC_NUM_AXES; i++) {
4153 if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) {
4154 converted_macc_table.data[idx] =
4155 (int16_t)sDIGIT_FITTING(params->macc_table.data[j],
4156 13, SH_CSS_MACC_COEF_SHIFT);
4157 converted_macc_table.data[idx+1] =
4158 (int16_t)sDIGIT_FITTING(params->macc_table.data[j+1],
4159 13, SH_CSS_MACC_COEF_SHIFT);
4160 converted_macc_table.data[idx+2] =
4161 (int16_t)sDIGIT_FITTING(params->macc_table.data[j+2],
4162 13, SH_CSS_MACC_COEF_SHIFT);
4163 converted_macc_table.data[idx+3] =
4164 (int16_t)sDIGIT_FITTING(params->macc_table.data[j+3],
4165 13, SH_CSS_MACC_COEF_SHIFT);
4166 } else if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) {
4167 converted_macc_table.data[idx] =
4168 params->macc_table.data[j];
4169 converted_macc_table.data[idx+1] =
4170 params->macc_table.data[j+1];
4171 converted_macc_table.data[idx+2] =
4172 params->macc_table.data[j+2];
4173 converted_macc_table.data[idx+3] =
4174 params->macc_table.data[j+3];
4177 reallocate_buffer(&ddr_map->macc_tbl,
4178 &ddr_map_size->macc_tbl,
4179 ddr_map_size->macc_tbl,
4182 if (err != IA_CSS_SUCCESS) {
4183 IA_CSS_LEAVE_ERR_PRIVATE(err);
4186 mmgr_store(ddr_map->macc_tbl,
4187 converted_macc_table.data,
4188 sizeof(converted_macc_table.data));
4191 if (binary->info->sp.enable.dvs_6axis) {
4192 /* because UV is packed into the Y plane, calc total
4193 * YYU size = /2 gives size of UV-only,
4194 * total YYU size = UV-only * 3.
4196 buff_realloced = reallocate_buffer(
4197 &ddr_map->dvs_6axis_params_y,
4198 &ddr_map_size->dvs_6axis_params_y,
4199 (size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3),
4200 params->pipe_dvs_6axis_config_changed[pipe_id],
4202 if (err != IA_CSS_SUCCESS) {
4203 IA_CSS_LEAVE_ERR_PRIVATE(err);
4207 if (params->pipe_dvs_6axis_config_changed[pipe_id] || buff_realloced) {
4208 const struct ia_css_frame_info *dvs_in_frame_info;
4210 if ( stage->args.delay_frames[0] ) {
4211 /*When delay frames are present(as in case of video),
4212 they are used for dvs. Configure DVS using those params*/
4213 dvs_in_frame_info = &stage->args.delay_frames[0]->info;
4215 /*Otherwise, use input frame to configure DVS*/
4216 dvs_in_frame_info = &stage->args.in_frame->info;
4219 /* Generate default DVS unity table on start up*/
4220 if (params->pipe_dvs_6axis_config[pipe_id] == NULL) {
4223 struct ia_css_resolution dvs_offset;
4226 struct ia_css_resolution dvs_offset = {0, 0};
4227 if (binary->dvs_envelope.width || binary->dvs_envelope.height) {
4230 (PIX_SHIFT_FILTER_RUN_IN_X + binary->dvs_envelope.width) / 2;
4236 (PIX_SHIFT_FILTER_RUN_IN_Y + binary->dvs_envelope.height) / 2;
4241 params->pipe_dvs_6axis_config[pipe_id] =
4242 generate_dvs_6axis_table(&binary->out_frame_info[0].res, &dvs_offset);
4243 if (params->pipe_dvs_6axis_config[pipe_id] == NULL) {
4244 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
4245 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
4247 params->pipe_dvs_6axis_config_changed[pipe_id] = true;
4250 store_dvs_6axis_config(params->pipe_dvs_6axis_config[pipe_id],
4253 ddr_map->dvs_6axis_params_y);
4254 params->isp_params_changed = true;
4258 if (binary->info->sp.enable.ca_gdc) {
4260 hrt_vaddress *virt_addr_tetra_x[
4261 IA_CSS_MORPH_TABLE_NUM_PLANES];
4262 size_t *virt_size_tetra_x[
4263 IA_CSS_MORPH_TABLE_NUM_PLANES];
4264 hrt_vaddress *virt_addr_tetra_y[
4265 IA_CSS_MORPH_TABLE_NUM_PLANES];
4266 size_t *virt_size_tetra_y[
4267 IA_CSS_MORPH_TABLE_NUM_PLANES];
4269 virt_addr_tetra_x[0] = &ddr_map->tetra_r_x;
4270 virt_addr_tetra_x[1] = &ddr_map->tetra_gr_x;
4271 virt_addr_tetra_x[2] = &ddr_map->tetra_gb_x;
4272 virt_addr_tetra_x[3] = &ddr_map->tetra_b_x;
4273 virt_addr_tetra_x[4] = &ddr_map->tetra_ratb_x;
4274 virt_addr_tetra_x[5] = &ddr_map->tetra_batr_x;
4276 virt_size_tetra_x[0] = &ddr_map_size->tetra_r_x;
4277 virt_size_tetra_x[1] = &ddr_map_size->tetra_gr_x;
4278 virt_size_tetra_x[2] = &ddr_map_size->tetra_gb_x;
4279 virt_size_tetra_x[3] = &ddr_map_size->tetra_b_x;
4280 virt_size_tetra_x[4] = &ddr_map_size->tetra_ratb_x;
4281 virt_size_tetra_x[5] = &ddr_map_size->tetra_batr_x;
4283 virt_addr_tetra_y[0] = &ddr_map->tetra_r_y;
4284 virt_addr_tetra_y[1] = &ddr_map->tetra_gr_y;
4285 virt_addr_tetra_y[2] = &ddr_map->tetra_gb_y;
4286 virt_addr_tetra_y[3] = &ddr_map->tetra_b_y;
4287 virt_addr_tetra_y[4] = &ddr_map->tetra_ratb_y;
4288 virt_addr_tetra_y[5] = &ddr_map->tetra_batr_y;
4290 virt_size_tetra_y[0] = &ddr_map_size->tetra_r_y;
4291 virt_size_tetra_y[1] = &ddr_map_size->tetra_gr_y;
4292 virt_size_tetra_y[2] = &ddr_map_size->tetra_gb_y;
4293 virt_size_tetra_y[3] = &ddr_map_size->tetra_b_y;
4294 virt_size_tetra_y[4] = &ddr_map_size->tetra_ratb_y;
4295 virt_size_tetra_y[5] = &ddr_map_size->tetra_batr_y;
4297 buff_realloced = false;
4298 for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
4300 reallocate_buffer(virt_addr_tetra_x[i],
4301 virt_size_tetra_x[i],
4303 (MORPH_PLANE_BYTES(binary)),
4304 params->morph_table_changed,
4306 if (err != IA_CSS_SUCCESS) {
4307 IA_CSS_LEAVE_ERR_PRIVATE(err);
4311 reallocate_buffer(virt_addr_tetra_y[i],
4312 virt_size_tetra_y[i],
4314 (MORPH_PLANE_BYTES(binary)),
4315 params->morph_table_changed,
4317 if (err != IA_CSS_SUCCESS) {
4318 IA_CSS_LEAVE_ERR_PRIVATE(err);
4322 if (params->morph_table_changed || buff_realloced) {
4323 const struct ia_css_morph_table *table = params->morph_table;
4324 struct ia_css_morph_table *id_table = NULL;
4326 if ((table != NULL) &&
4327 (table->width < binary->morph_tbl_width ||
4328 table->height < binary->morph_tbl_height)) {
4331 if (table == NULL) {
4332 err = sh_css_params_default_morph_table(&id_table,
4334 if (err != IA_CSS_SUCCESS) {
4335 IA_CSS_LEAVE_ERR_PRIVATE(err);
4341 for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
4342 store_morph_plane(table->coordinates_x[i],
4345 *virt_addr_tetra_x[i],
4346 binary->morph_tbl_aligned_width);
4347 store_morph_plane(table->coordinates_y[i],
4350 *virt_addr_tetra_y[i],
4351 binary->morph_tbl_aligned_width);
4353 if (id_table != NULL)
4354 ia_css_morph_table_free(id_table);
4358 /* After special cases like SC, FPN since they may change parameters */
4359 for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) {
4360 const struct ia_css_isp_data *isp_data =
4361 ia_css_isp_param_get_isp_mem_init(&binary->info->sp.mem_initializers, IA_CSS_PARAM_CLASS_PARAM, mem);
4362 size_t size = isp_data->size;
4363 if (!size) continue;
4364 buff_realloced = reallocate_buffer(&ddr_map->isp_mem_param[stage_num][mem],
4365 &ddr_map_size->isp_mem_param[stage_num][mem],
4367 params->isp_mem_params_changed[pipe_id][stage_num][mem],
4369 if (err != IA_CSS_SUCCESS) {
4370 IA_CSS_LEAVE_ERR_PRIVATE(err);
4373 if (params->isp_mem_params_changed[pipe_id][stage_num][mem] || buff_realloced) {
4374 sh_css_update_isp_mem_params_to_ddr(binary,
4375 ddr_map->isp_mem_param[stage_num][mem],
4376 ddr_map_size->isp_mem_param[stage_num][mem], mem);
4380 IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS);
4381 return IA_CSS_SUCCESS;
4384 const struct ia_css_fpn_table *ia_css_get_fpn_table(struct ia_css_stream *stream)
4386 struct ia_css_isp_parameters *params;
4388 IA_CSS_ENTER_LEAVE("void");
4389 assert(stream != NULL);
4391 params = stream->isp_params_configs;
4393 return &(params->fpn_config);
4396 struct ia_css_shading_table *ia_css_get_shading_table(struct ia_css_stream *stream)
4398 struct ia_css_shading_table *table = NULL;
4399 struct ia_css_isp_parameters *params;
4401 IA_CSS_ENTER("void");
4403 assert(stream != NULL);
4405 params = stream->isp_params_configs;
4409 if (params->shading_settings.enable_shading_table_conversion == 0) {
4410 if (params->sc_table) {
4411 table = (struct ia_css_shading_table *)params->sc_table;
4413 const struct ia_css_binary *binary
4414 = ia_css_stream_get_shading_correction_binary(stream);
4416 /* generate the identical shading table */
4417 if (params->sc_config) {
4418 ia_css_shading_table_free(params->sc_config);
4419 params->sc_config = NULL;
4422 sh_css_params_shading_id_table_generate(¶ms->sc_config, binary);
4425 sh_css_params_shading_id_table_generate(¶ms->sc_config,
4426 binary->sctbl_width_per_color, binary->sctbl_height);
4428 table = params->sc_config;
4429 /* The sc_config will be freed in the
4430 * ia_css_stream_isp_parameters_uninit function. */
4434 /* ------ deprecated(bz675) : from ------ */
4435 const struct ia_css_binary *binary
4436 = ia_css_stream_get_shading_correction_binary(stream);
4437 struct ia_css_pipe *pipe;
4439 /**********************************************************************/
4440 /* following code is copied from function ia_css_stream_get_shading_correction_binary()
4441 * to match with the binary */
4442 pipe = stream->pipes[0];
4444 if (stream->num_pipes == 2) {
4445 assert(stream->pipes[1] != NULL);
4446 if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO ||
4447 stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW)
4448 pipe = stream->pipes[1];
4450 /**********************************************************************/
4452 if (params->sc_config) {
4453 ia_css_shading_table_free(params->sc_config);
4454 params->sc_config = NULL;
4456 prepare_shading_table(
4457 (const struct ia_css_shading_table *)params->sc_table,
4458 params->sensor_binning,
4460 binary, pipe->required_bds_factor);
4462 table = params->sc_config;
4463 /* The sc_config will be freed in the
4464 * ia_css_stream_isp_parameters_uninit function. */
4466 /* ------ deprecated(bz675) : to ------ */
4469 IA_CSS_LEAVE("table=%p", table);
4475 hrt_vaddress sh_css_store_sp_group_to_ddr(void)
4477 IA_CSS_ENTER_LEAVE_PRIVATE("void");
4478 mmgr_store(xmem_sp_group_ptrs,
4480 sizeof(struct sh_css_sp_group));
4481 return xmem_sp_group_ptrs;
4484 hrt_vaddress sh_css_store_sp_stage_to_ddr(
4488 IA_CSS_ENTER_LEAVE_PRIVATE("void");
4489 mmgr_store(xmem_sp_stage_ptrs[pipe][stage],
4491 sizeof(struct sh_css_sp_stage));
4492 return xmem_sp_stage_ptrs[pipe][stage];
4495 hrt_vaddress sh_css_store_isp_stage_to_ddr(
4499 IA_CSS_ENTER_LEAVE_PRIVATE("void");
4500 mmgr_store(xmem_isp_stage_ptrs[pipe][stage],
4502 sizeof(struct sh_css_isp_stage));
4503 return xmem_isp_stage_ptrs[pipe][stage];
4506 static enum ia_css_err ref_sh_css_ddr_address_map(
4507 struct sh_css_ddr_address_map *map,
4508 struct sh_css_ddr_address_map *out)
4510 enum ia_css_err err = IA_CSS_SUCCESS;
4513 /* we will use a union to copy things; overlaying an array
4514 with the struct; that way adding fields in the struct
4515 will keep things working, and we will not get type errors.
4518 struct sh_css_ddr_address_map *map;
4519 hrt_vaddress *addrs;
4520 } in_addrs, to_addrs;
4522 IA_CSS_ENTER_PRIVATE("void");
4523 assert(map != NULL);
4524 assert(out != NULL);
4529 assert(sizeof(struct sh_css_ddr_address_map_size)/sizeof(size_t) ==
4530 sizeof(struct sh_css_ddr_address_map)/sizeof(hrt_vaddress));
4532 /* copy map using size info */
4533 for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/
4534 sizeof(size_t)); i++) {
4535 if (in_addrs.addrs[i] == mmgr_NULL)
4536 to_addrs.addrs[i] = mmgr_NULL;
4538 to_addrs.addrs[i] = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, in_addrs.addrs[i]);
4541 IA_CSS_LEAVE_ERR_PRIVATE(err);
4545 static enum ia_css_err write_ia_css_isp_parameter_set_info_to_ddr(
4546 struct ia_css_isp_parameter_set_info *me,
4549 enum ia_css_err err = IA_CSS_SUCCESS;
4552 IA_CSS_ENTER_PRIVATE("void");
4555 assert(out != NULL);
4557 *out = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_SET_POOL, mmgr_malloc(
4558 sizeof(struct ia_css_isp_parameter_set_info)));
4559 succ = (*out != mmgr_NULL);
4562 me, sizeof(struct ia_css_isp_parameter_set_info));
4564 err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
4566 IA_CSS_LEAVE_ERR_PRIVATE(err);
4570 static enum ia_css_err
4571 free_ia_css_isp_parameter_set_info(
4574 enum ia_css_err err = IA_CSS_SUCCESS;
4575 struct ia_css_isp_parameter_set_info isp_params_info;
4577 hrt_vaddress *addrs = (hrt_vaddress *)&isp_params_info.mem_map;
4579 IA_CSS_ENTER_PRIVATE("ptr = %u", ptr);
4581 /* sanity check - ptr must be valid */
4582 if (!ia_css_refcount_is_valid(ptr)) {
4583 IA_CSS_ERROR("%s: IA_CSS_REFCOUNT_PARAM_SET_POOL(0x%x) invalid arg", __func__, ptr);
4584 err = IA_CSS_ERR_INVALID_ARGUMENTS;
4585 IA_CSS_LEAVE_ERR_PRIVATE(err);
4589 mmgr_load(ptr, &isp_params_info.mem_map, sizeof(struct sh_css_ddr_address_map));
4590 /* copy map using size info */
4591 for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/
4592 sizeof(size_t)); i++) {
4593 if (addrs[i] == mmgr_NULL)
4596 /* sanity check - ptr must be valid */
4598 if (!ia_css_refcount_is_valid(addrs[i])) {
4600 if (ia_css_refcount_is_valid(addrs[i])) {
4601 ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]);
4604 IA_CSS_ERROR("%s: IA_CSS_REFCOUNT_PARAM_BUFFER(0x%x) invalid arg", __func__, ptr);
4605 err = IA_CSS_ERR_INVALID_ARGUMENTS;
4610 ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]);
4613 ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_SET_POOL, ptr);
4615 IA_CSS_LEAVE_ERR_PRIVATE(err);
4619 /* Mark all parameters as changed to force recomputing the derived ISP parameters */
4621 sh_css_invalidate_params(struct ia_css_stream *stream)
4623 struct ia_css_isp_parameters *params;
4626 IA_CSS_ENTER_PRIVATE("void");
4627 assert(stream != NULL);
4629 params = stream->isp_params_configs;
4630 params->isp_params_changed = true;
4631 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
4632 for (j = 0; j < SH_CSS_MAX_STAGES; j++) {
4633 for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) {
4634 params->isp_mem_params_changed[i][j][mem] = true;
4639 memset(¶ms->config_changed[0], 1, sizeof(params->config_changed));
4640 params->dis_coef_table_changed = true;
4641 params->dvs2_coef_table_changed = true;
4642 params->morph_table_changed = true;
4643 params->sc_table_changed = true;
4644 params->dz_config_changed = true;
4645 params->motion_config_changed = true;
4647 /*Free up theDVS table memory blocks before recomputing new table */
4648 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
4649 if (params->pipe_dvs_6axis_config[i]) {
4650 free_dvs_6axis_table(&(params->pipe_dvs_6axis_config[i]));
4651 params->pipe_dvs_6axis_config_changed[i] = true;
4655 IA_CSS_LEAVE_PRIVATE("void");
4659 sh_css_update_uds_and_crop_info(
4660 const struct ia_css_binary_info *info,
4661 const struct ia_css_frame_info *in_frame_info,
4662 const struct ia_css_frame_info *out_frame_info,
4663 const struct ia_css_resolution *dvs_env,
4664 const struct ia_css_dz_config *zoom,
4665 const struct ia_css_vector *motion_vector,
4666 struct sh_css_uds_info *uds, /* out */
4667 struct sh_css_crop_pos *sp_out_crop_pos, /* out */
4670 IA_CSS_ENTER_PRIVATE("void");
4672 assert(info != NULL);
4673 assert(in_frame_info != NULL);
4674 assert(out_frame_info != NULL);
4675 assert(dvs_env != NULL);
4676 assert(zoom != NULL);
4677 assert(motion_vector != NULL);
4678 assert(uds != NULL);
4679 assert(sp_out_crop_pos != NULL);
4681 uds->curr_dx = enable_zoom ? (uint16_t)zoom->dx : HRT_GDC_N;
4682 uds->curr_dy = enable_zoom ? (uint16_t)zoom->dy : HRT_GDC_N;
4684 if (info->enable.dvs_envelope) {
4685 unsigned int crop_x = 0,
4689 env_width, env_height;
4690 int half_env_x, half_env_y;
4691 int motion_x = motion_vector->x;
4692 int motion_y = motion_vector->y;
4693 bool upscale_x = in_frame_info->res.width < out_frame_info->res.width;
4694 bool upscale_y = in_frame_info->res.height < out_frame_info->res.height;
4696 if (info->enable.uds && !info->enable.ds) {
4698 * we calculate with the envelope that we can actually
4699 * use, the min dvs envelope is for the filter
4702 env_width = dvs_env->width -
4703 SH_CSS_MIN_DVS_ENVELOPE;
4704 env_height = dvs_env->height -
4705 SH_CSS_MIN_DVS_ENVELOPE;
4706 half_env_x = env_width / 2;
4707 half_env_y = env_height / 2;
4709 * for digital zoom, we use the dvs envelope and make
4710 * sure that we don't include the 8 leftmost pixels or
4714 uds_xc = (in_frame_info->res.width
4716 + SH_CSS_MIN_DVS_ENVELOPE) / 2;
4718 uds_xc = (out_frame_info->res.width
4720 + SH_CSS_MIN_DVS_ENVELOPE;
4723 uds_yc = (in_frame_info->res.height
4725 + SH_CSS_MIN_DVS_ENVELOPE) / 2;
4727 uds_yc = (out_frame_info->res.height
4729 + SH_CSS_MIN_DVS_ENVELOPE;
4731 /* clip the motion vector to +/- half the envelope */
4732 motion_x = clamp(motion_x, -half_env_x, half_env_x);
4733 motion_y = clamp(motion_y, -half_env_y, half_env_y);
4736 /* uds can be pipelined, remove top lines */
4738 } else if (info->enable.ds) {
4739 env_width = dvs_env->width;
4740 env_height = dvs_env->height;
4741 half_env_x = env_width / 2;
4742 half_env_y = env_height / 2;
4743 /* clip the motion vector to +/- half the envelope */
4744 motion_x = clamp(motion_x, -half_env_x, half_env_x);
4745 motion_y = clamp(motion_y, -half_env_y, half_env_y);
4746 /* for video with downscaling, the envelope is included
4747 in the input resolution. */
4748 uds_xc = in_frame_info->res.width/2 + motion_x;
4749 uds_yc = in_frame_info->res.height/2 + motion_y;
4750 crop_x = info->pipeline.left_cropping;
4751 /* ds == 2 (yuv_ds) can be pipelined, remove top
4753 if (info->enable.ds & 1)
4754 crop_y = info->pipeline.top_cropping;
4758 /* video nodz: here we can only crop. We make sure we
4759 crop at least the first 8x8 pixels away. */
4760 env_width = dvs_env->width -
4761 SH_CSS_MIN_DVS_ENVELOPE;
4762 env_height = dvs_env->height -
4763 SH_CSS_MIN_DVS_ENVELOPE;
4764 half_env_x = env_width / 2;
4765 half_env_y = env_height / 2;
4766 motion_x = clamp(motion_x, -half_env_x, half_env_x);
4767 motion_y = clamp(motion_y, -half_env_y, half_env_y);
4768 crop_x = SH_CSS_MIN_DVS_ENVELOPE
4769 + half_env_x + motion_x;
4770 crop_y = SH_CSS_MIN_DVS_ENVELOPE
4771 + half_env_y + motion_y;
4774 /* Must enforce that the crop position is even */
4775 crop_x = EVEN_FLOOR(crop_x);
4776 crop_y = EVEN_FLOOR(crop_y);
4777 uds_xc = EVEN_FLOOR(uds_xc);
4778 uds_yc = EVEN_FLOOR(uds_yc);
4780 uds->xc = (uint16_t)uds_xc;
4781 uds->yc = (uint16_t)uds_yc;
4782 sp_out_crop_pos->x = (uint16_t)crop_x;
4783 sp_out_crop_pos->y = (uint16_t)crop_y;
4786 /* for down scaling, we always use the center of the image */
4787 uds->xc = (uint16_t)in_frame_info->res.width / 2;
4788 uds->yc = (uint16_t)in_frame_info->res.height / 2;
4789 sp_out_crop_pos->x = (uint16_t)info->pipeline.left_cropping;
4790 sp_out_crop_pos->y = (uint16_t)info->pipeline.top_cropping;
4792 IA_CSS_LEAVE_PRIVATE("void");
4795 static enum ia_css_err
4796 sh_css_update_uds_and_crop_info_based_on_zoom_region(
4797 const struct ia_css_binary_info *info,
4798 const struct ia_css_frame_info *in_frame_info,
4799 const struct ia_css_frame_info *out_frame_info,
4800 const struct ia_css_resolution *dvs_env,
4801 const struct ia_css_dz_config *zoom,
4802 const struct ia_css_vector *motion_vector,
4803 struct sh_css_uds_info *uds, /* out */
4804 struct sh_css_crop_pos *sp_out_crop_pos, /* out */
4805 struct ia_css_resolution pipe_in_res,
4808 unsigned int x0 = 0, y0 = 0, x1 = 0, y1 = 0;
4809 enum ia_css_err err = IA_CSS_SUCCESS;
4811 * Filter_Envelope = 0 for NND/LUT
4812 * Filter_Envelope = 1 for BCI
4813 * Filter_Envelope = 3 for BLI
4814 * Currently, not considering this filter envelope because, In uds.sp.c is recalculating
4815 * the dx/dy based on filter envelope and other information (ia_css_uds_sp_scale_params)
4816 * Ideally, That should be done on host side not on sp side.
4818 unsigned int filter_envelope = 0;
4819 IA_CSS_ENTER_PRIVATE("void");
4821 assert(info != NULL);
4822 assert(in_frame_info != NULL);
4823 assert(out_frame_info != NULL);
4824 assert(dvs_env != NULL);
4825 assert(zoom != NULL);
4826 assert(motion_vector != NULL);
4827 assert(uds != NULL);
4828 assert(sp_out_crop_pos != NULL);
4829 x0 = zoom->zoom_region.origin.x;
4830 y0 = zoom->zoom_region.origin.y;
4831 x1 = zoom->zoom_region.resolution.width + x0;
4832 y1 = zoom->zoom_region.resolution.height + y0;
4834 if ((x0 > x1) || (y0 > y1) || (x1 > pipe_in_res.width) || (y1 > pipe_in_res.height))
4835 return IA_CSS_ERR_INVALID_ARGUMENTS;
4838 uds->curr_dx = HRT_GDC_N;
4839 uds->curr_dy = HRT_GDC_N;
4842 if (info->enable.dvs_envelope) {
4843 /* Zoom region is only supported by the UDS module on ISP
4844 * 2 and higher. It is not supported in video mode on ISP 1 */
4845 return IA_CSS_ERR_INVALID_ARGUMENTS;
4848 /* A. Calculate dx/dy based on crop region using in_frame_info
4849 * Scale the crop region if in_frame_info to the stage is not same as
4850 * actual effective input of the pipeline
4852 if (in_frame_info->res.width != pipe_in_res.width ||
4853 in_frame_info->res.height != pipe_in_res.height) {
4854 x0 = (x0 * in_frame_info->res.width) / (pipe_in_res.width);
4855 y0 = (y0 * in_frame_info->res.height) / (pipe_in_res.height);
4856 x1 = (x1 * in_frame_info->res.width) / (pipe_in_res.width);
4857 y1 = (y1 * in_frame_info->res.height) / (pipe_in_res.height);
4860 ((x1 - x0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.width;
4862 ((y1 - y0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.height;
4864 /* B. Calculate xc/yc based on crop region */
4865 uds->xc = (uint16_t) x0 + (((x1)-(x0)) / 2);
4866 uds->yc = (uint16_t) y0 + (((y1)-(y0)) / 2);
4868 uds->xc = (uint16_t)in_frame_info->res.width / 2;
4869 uds->yc = (uint16_t)in_frame_info->res.height / 2;
4872 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "uds->curr_dx=%d, uds->xc=%d, uds->yc=%d\n",
4873 uds->curr_dx, uds->xc, uds->yc);
4874 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x0=%d, y0=%d, x1=%d, y1=%d\n",
4876 sp_out_crop_pos->x = (uint16_t)info->pipeline.left_cropping;
4877 sp_out_crop_pos->y = (uint16_t)info->pipeline.top_cropping;
4879 IA_CSS_LEAVE_PRIVATE("void");
4883 struct ia_css_3a_statistics *
4884 ia_css_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid)
4886 struct ia_css_3a_statistics *me;
4889 IA_CSS_ENTER("grid=%p", grid);
4891 assert(grid != NULL);
4893 me = sh_css_calloc(1, sizeof(*me));
4898 grid_size = grid->width * grid->height;
4899 me->data = sh_css_malloc(grid_size * sizeof(*me->data));
4902 #if !defined(HAS_NO_HMEM)
4903 /* No weighted histogram, no structure, treat the histogram data as a byte dump in a byte array */
4904 me->rgby_data = (struct ia_css_3a_rgby_output *)sh_css_malloc(sizeof_hmem(HMEM0_ID));
4906 me->rgby_data = NULL;
4909 IA_CSS_LEAVE("return=%p", me);
4912 ia_css_3a_statistics_free(me);
4914 IA_CSS_LEAVE("return=%p", NULL);
4919 ia_css_3a_statistics_free(struct ia_css_3a_statistics *me)
4922 sh_css_free(me->rgby_data);
4923 sh_css_free(me->data);
4924 memset(me, 0, sizeof(struct ia_css_3a_statistics));
4929 struct ia_css_dvs_statistics *
4930 ia_css_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid)
4932 struct ia_css_dvs_statistics *me;
4934 assert(grid != NULL);
4936 me = sh_css_calloc(1, sizeof(*me));
4941 me->hor_proj = sh_css_malloc(grid->height * IA_CSS_DVS_NUM_COEF_TYPES *
4942 sizeof(*me->hor_proj));
4946 me->ver_proj = sh_css_malloc(grid->width * IA_CSS_DVS_NUM_COEF_TYPES *
4947 sizeof(*me->ver_proj));
4953 ia_css_dvs_statistics_free(me);
4959 ia_css_dvs_statistics_free(struct ia_css_dvs_statistics *me)
4962 sh_css_free(me->hor_proj);
4963 sh_css_free(me->ver_proj);
4964 memset(me, 0, sizeof(struct ia_css_dvs_statistics));
4969 struct ia_css_dvs_coefficients *
4970 ia_css_dvs_coefficients_allocate(const struct ia_css_dvs_grid_info *grid)
4972 struct ia_css_dvs_coefficients *me;
4974 assert(grid != NULL);
4976 me = sh_css_calloc(1, sizeof(*me));
4982 me->hor_coefs = sh_css_malloc(grid->num_hor_coefs *
4983 IA_CSS_DVS_NUM_COEF_TYPES *
4984 sizeof(*me->hor_coefs));
4988 me->ver_coefs = sh_css_malloc(grid->num_ver_coefs *
4989 IA_CSS_DVS_NUM_COEF_TYPES *
4990 sizeof(*me->ver_coefs));
4996 ia_css_dvs_coefficients_free(me);
5001 ia_css_dvs_coefficients_free(struct ia_css_dvs_coefficients *me)
5004 sh_css_free(me->hor_coefs);
5005 sh_css_free(me->ver_coefs);
5006 memset(me, 0, sizeof(struct ia_css_dvs_coefficients));
5011 struct ia_css_dvs2_statistics *
5012 ia_css_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid)
5014 struct ia_css_dvs2_statistics *me;
5016 assert(grid != NULL);
5018 me = sh_css_calloc(1, sizeof(*me));
5024 me->hor_prod.odd_real = sh_css_malloc(grid->aligned_width *
5025 grid->aligned_height * sizeof(*me->hor_prod.odd_real));
5026 if (!me->hor_prod.odd_real)
5029 me->hor_prod.odd_imag = sh_css_malloc(grid->aligned_width *
5030 grid->aligned_height * sizeof(*me->hor_prod.odd_imag));
5031 if (!me->hor_prod.odd_imag)
5034 me->hor_prod.even_real = sh_css_malloc(grid->aligned_width *
5035 grid->aligned_height * sizeof(*me->hor_prod.even_real));
5036 if (!me->hor_prod.even_real)
5039 me->hor_prod.even_imag = sh_css_malloc(grid->aligned_width *
5040 grid->aligned_height * sizeof(*me->hor_prod.even_imag));
5041 if (!me->hor_prod.even_imag)
5044 me->ver_prod.odd_real = sh_css_malloc(grid->aligned_width *
5045 grid->aligned_height * sizeof(*me->ver_prod.odd_real));
5046 if (!me->ver_prod.odd_real)
5049 me->ver_prod.odd_imag = sh_css_malloc(grid->aligned_width *
5050 grid->aligned_height * sizeof(*me->ver_prod.odd_imag));
5051 if (!me->ver_prod.odd_imag)
5054 me->ver_prod.even_real = sh_css_malloc(grid->aligned_width *
5055 grid->aligned_height * sizeof(*me->ver_prod.even_real));
5056 if (!me->ver_prod.even_real)
5059 me->ver_prod.even_imag = sh_css_malloc(grid->aligned_width *
5060 grid->aligned_height * sizeof(*me->ver_prod.even_imag));
5061 if (!me->ver_prod.even_imag)
5066 ia_css_dvs2_statistics_free(me);
5072 ia_css_dvs2_statistics_free(struct ia_css_dvs2_statistics *me)
5075 sh_css_free(me->hor_prod.odd_real);
5076 sh_css_free(me->hor_prod.odd_imag);
5077 sh_css_free(me->hor_prod.even_real);
5078 sh_css_free(me->hor_prod.even_imag);
5079 sh_css_free(me->ver_prod.odd_real);
5080 sh_css_free(me->ver_prod.odd_imag);
5081 sh_css_free(me->ver_prod.even_real);
5082 sh_css_free(me->ver_prod.even_imag);
5083 memset(me, 0, sizeof(struct ia_css_dvs2_statistics));
5089 struct ia_css_dvs2_coefficients *
5090 ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid)
5092 struct ia_css_dvs2_coefficients *me;
5094 assert(grid != NULL);
5096 me = sh_css_calloc(1, sizeof(*me));
5102 me->hor_coefs.odd_real = sh_css_malloc(grid->num_hor_coefs *
5103 sizeof(*me->hor_coefs.odd_real));
5104 if (!me->hor_coefs.odd_real)
5107 me->hor_coefs.odd_imag = sh_css_malloc(grid->num_hor_coefs *
5108 sizeof(*me->hor_coefs.odd_imag));
5109 if (!me->hor_coefs.odd_imag)
5112 me->hor_coefs.even_real = sh_css_malloc(grid->num_hor_coefs *
5113 sizeof(*me->hor_coefs.even_real));
5114 if (!me->hor_coefs.even_real)
5117 me->hor_coefs.even_imag = sh_css_malloc(grid->num_hor_coefs *
5118 sizeof(*me->hor_coefs.even_imag));
5119 if (!me->hor_coefs.even_imag)
5122 me->ver_coefs.odd_real = sh_css_malloc(grid->num_ver_coefs *
5123 sizeof(*me->ver_coefs.odd_real));
5124 if (!me->ver_coefs.odd_real)
5127 me->ver_coefs.odd_imag = sh_css_malloc(grid->num_ver_coefs *
5128 sizeof(*me->ver_coefs.odd_imag));
5129 if (!me->ver_coefs.odd_imag)
5132 me->ver_coefs.even_real = sh_css_malloc(grid->num_ver_coefs *
5133 sizeof(*me->ver_coefs.even_real));
5134 if (!me->ver_coefs.even_real)
5137 me->ver_coefs.even_imag = sh_css_malloc(grid->num_ver_coefs *
5138 sizeof(*me->ver_coefs.even_imag));
5139 if (!me->ver_coefs.even_imag)
5144 ia_css_dvs2_coefficients_free(me);
5149 ia_css_dvs2_coefficients_free(struct ia_css_dvs2_coefficients *me)
5152 sh_css_free(me->hor_coefs.odd_real);
5153 sh_css_free(me->hor_coefs.odd_imag);
5154 sh_css_free(me->hor_coefs.even_real);
5155 sh_css_free(me->hor_coefs.even_imag);
5156 sh_css_free(me->ver_coefs.odd_real);
5157 sh_css_free(me->ver_coefs.odd_imag);
5158 sh_css_free(me->ver_coefs.even_real);
5159 sh_css_free(me->ver_coefs.even_imag);
5160 memset(me, 0, sizeof(struct ia_css_dvs2_coefficients));
5165 struct ia_css_dvs_6axis_config *
5166 ia_css_dvs2_6axis_config_allocate(const struct ia_css_stream *stream)
5168 struct ia_css_dvs_6axis_config *dvs_config = NULL;
5169 struct ia_css_isp_parameters *params = NULL;
5170 unsigned int width_y;
5171 unsigned int height_y;
5172 unsigned int width_uv;
5173 unsigned int height_uv;
5175 assert(stream != NULL);
5176 params = stream->isp_params_configs;
5178 /* Backward compatibility by default consider pipe as Video*/
5179 if (!params || (params && !params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO])) {
5183 dvs_config = (struct ia_css_dvs_6axis_config *)sh_css_calloc(1, sizeof(struct ia_css_dvs_6axis_config));
5187 dvs_config->width_y = width_y = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->width_y;
5188 dvs_config->height_y = height_y = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->height_y;
5189 dvs_config->width_uv = width_uv = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->width_uv;
5190 dvs_config->height_uv = height_uv = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->height_uv;
5191 IA_CSS_LOG("table Y: W %d H %d", width_y, height_y);
5192 IA_CSS_LOG("table UV: W %d H %d", width_uv, height_uv);
5193 dvs_config->xcoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t));
5194 if (!dvs_config->xcoords_y)
5197 dvs_config->ycoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t));
5198 if (!dvs_config->ycoords_y)
5201 dvs_config->xcoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t));
5202 if (!dvs_config->xcoords_uv)
5205 dvs_config->ycoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t));
5206 if (!dvs_config->ycoords_uv)
5211 ia_css_dvs2_6axis_config_free(dvs_config);
5216 ia_css_dvs2_6axis_config_free(struct ia_css_dvs_6axis_config *dvs_6axis_config)
5218 if (dvs_6axis_config) {
5219 sh_css_free(dvs_6axis_config->xcoords_y);
5220 sh_css_free(dvs_6axis_config->ycoords_y);
5221 sh_css_free(dvs_6axis_config->xcoords_uv);
5222 sh_css_free(dvs_6axis_config->ycoords_uv);
5223 memset(dvs_6axis_config, 0, sizeof(struct ia_css_dvs_6axis_config));
5224 sh_css_free(dvs_6axis_config);
5229 ia_css_en_dz_capt_pipe(struct ia_css_stream *stream, bool enable)
5231 struct ia_css_pipe *pipe;
5232 struct ia_css_pipeline *pipeline;
5233 struct ia_css_pipeline_stage *stage;
5234 enum ia_css_pipe_id pipe_id;
5235 enum ia_css_err err;
5241 for (i = 0; i < stream->num_pipes; i++) {
5242 pipe = stream->pipes[i];
5243 pipeline = ia_css_pipe_get_pipeline(pipe);
5244 pipe_id = pipeline->pipe_id;
5246 if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) {
5247 err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, &stage);
5248 if (err == IA_CSS_SUCCESS)
5249 stage->enable_zoom = enable;
projects / releases.git / blob