2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __IA_CSS_EED1_8_PARAM_H
16 #define __IA_CSS_EED1_8_PARAM_H
18 #include "type_support.h"
19 #include "vmem.h" /* needed for VMEM_ARRAY */
21 #include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */
24 /* Configuration parameters: */
26 /* Enable median for false color correction
27 * 0: Do not use median
31 #define EED1_8_FC_ENABLE_MEDIAN 1
33 /* Coring Threshold minima
34 * Used in Tint color suppression.
37 #define EED1_8_CORINGTHMIN 1
39 /* Define size of the state..... TODO: check if this is the correct place */
40 /* 4 planes : GR, R, B, GB */
43 /* 5 lines state per color plane input_line_state */
44 #define EED1_8_STATE_INPUT_BUFFER_HEIGHT (5 * NUM_PLANES)
46 /* Each plane has width equal to half frame line */
47 #define EED1_8_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
49 /* 1 line state per color plane LD_H state */
50 #define EED1_8_STATE_LD_H_HEIGHT (1 * NUM_PLANES)
51 #define EED1_8_STATE_LD_H_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
53 /* 1 line state per color plane LD_V state */
54 #define EED1_8_STATE_LD_V_HEIGHT (1 * NUM_PLANES)
55 #define EED1_8_STATE_LD_V_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
57 /* 1 line (single plane) state for D_Hr state */
58 #define EED1_8_STATE_D_HR_HEIGHT 1
59 #define EED1_8_STATE_D_HR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
61 /* 1 line (single plane) state for D_Hb state */
62 #define EED1_8_STATE_D_HB_HEIGHT 1
63 #define EED1_8_STATE_D_HB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
65 /* 2 lines (single plane) state for D_Vr state */
66 #define EED1_8_STATE_D_VR_HEIGHT 2
67 #define EED1_8_STATE_D_VR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
69 /* 2 line (single plane) state for D_Vb state */
70 #define EED1_8_STATE_D_VB_HEIGHT 2
71 #define EED1_8_STATE_D_VB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
73 /* 2 lines state for R and B (= 2 planes) rb_zipped_state */
74 #define EED1_8_STATE_RB_ZIPPED_HEIGHT (2 * 2)
75 #define EED1_8_STATE_RB_ZIPPED_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
77 #if EED1_8_FC_ENABLE_MEDIAN
78 /* 1 full input line (GR-R color line) for Yc state */
79 #define EED1_8_STATE_YC_HEIGHT 1
80 #define EED1_8_STATE_YC_WIDTH MAX_FRAME_SIMDWIDTH
82 /* 1 line state per color plane Cg_state */
83 #define EED1_8_STATE_CG_HEIGHT (1 * NUM_PLANES)
84 #define EED1_8_STATE_CG_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
86 /* 1 line state per color plane Co_state */
87 #define EED1_8_STATE_CO_HEIGHT (1 * NUM_PLANES)
88 #define EED1_8_STATE_CO_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2)
90 /* 1 full input line (GR-R color line) for AbsK state */
91 #define EED1_8_STATE_ABSK_HEIGHT 1
92 #define EED1_8_STATE_ABSK_WIDTH MAX_FRAME_SIMDWIDTH
95 struct eed1_8_vmem_params {
96 VMEM_ARRAY(e_dew_enh_x, ISP_VEC_NELEMS);
97 VMEM_ARRAY(e_dew_enh_y, ISP_VEC_NELEMS);
98 VMEM_ARRAY(e_dew_enh_a, ISP_VEC_NELEMS);
99 VMEM_ARRAY(e_dew_enh_f, ISP_VEC_NELEMS);
100 VMEM_ARRAY(chgrinv_x, ISP_VEC_NELEMS);
101 VMEM_ARRAY(chgrinv_a, ISP_VEC_NELEMS);
102 VMEM_ARRAY(chgrinv_b, ISP_VEC_NELEMS);
103 VMEM_ARRAY(chgrinv_c, ISP_VEC_NELEMS);
104 VMEM_ARRAY(fcinv_x, ISP_VEC_NELEMS);
105 VMEM_ARRAY(fcinv_a, ISP_VEC_NELEMS);
106 VMEM_ARRAY(fcinv_b, ISP_VEC_NELEMS);
107 VMEM_ARRAY(fcinv_c, ISP_VEC_NELEMS);
108 VMEM_ARRAY(tcinv_x, ISP_VEC_NELEMS);
109 VMEM_ARRAY(tcinv_a, ISP_VEC_NELEMS);
110 VMEM_ARRAY(tcinv_b, ISP_VEC_NELEMS);
111 VMEM_ARRAY(tcinv_c, ISP_VEC_NELEMS);
114 /* EED (Edge Enhancing Demosaic) ISP parameters */
115 struct eed1_8_dmem_params {
116 int32_t rbzp_strength;
121 int32_t fc_coring_prm;
124 int32_t aerel_thres0;
126 int32_t aerel_thres_diff;
127 int32_t aerel_gain_diff;
129 int32_t derel_thres0;
131 int32_t derel_thres_diff;
132 int32_t derel_gain_diff;
135 int32_t coring_pos_diff;
137 int32_t coring_neg_diff;
141 int32_t gain_pos_diff;
143 int32_t gain_neg_diff;
146 int32_t margin_pos_diff;
148 int32_t margin_neg_diff;
150 int32_t e_dew_enh_asr;
154 #endif /* __IA_CSS_EED1_8_PARAM_H */