drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl.c

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include "timed_ctrl.h"
  16
  17 #ifndef __INLINE_TIMED_CTRL__
  18 #include "timed_ctrl_private.h"
  19 #endif /* __INLINE_TIMED_CTRL__ */
  20
  21 #include "assert_support.h"
  22
  23 void timed_ctrl_snd_commnd(
  24         const timed_ctrl_ID_t                   ID,
  25         hrt_data                                mask,
  26         hrt_data                                condition,
  27         hrt_data                                counter,
  28         hrt_address                             addr,
  29         hrt_data                                value)
  30 {
  31         OP___assert(ID == TIMED_CTRL0_ID);
  32         OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1);
  33
  34         timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, mask);
  35         timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, condition);
  36         timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, counter);
  37         timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, (hrt_data)addr);
  38         timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, value);
  39 }
  40
  41 /* pqiao TODO: make sure the following commands get
  42         correct BASE address both for csim and android */
  43
  44 void timed_ctrl_snd_sp_commnd(
  45         const timed_ctrl_ID_t                   ID,
  46         hrt_data                                mask,
  47         hrt_data                                condition,
  48         hrt_data                                counter,
  49         const sp_ID_t                           SP_ID,
  50         hrt_address                             offset,
  51         hrt_data                                value)
  52 {
  53         OP___assert(SP_ID < N_SP_ID);
  54         OP___assert(SP_DMEM_BASE[SP_ID] != (hrt_address)-1);
  55
  56         timed_ctrl_snd_commnd(ID, mask, condition, counter,
  57                                 SP_DMEM_BASE[SP_ID]+offset, value);
  58 }
  59
  60 void timed_ctrl_snd_gpio_commnd(
  61         const timed_ctrl_ID_t                   ID,
  62         hrt_data                                mask,
  63         hrt_data                                condition,
  64         hrt_data                                counter,
  65         const gpio_ID_t                         GPIO_ID,
  66         hrt_address                             offset,
  67         hrt_data                                value)
  68 {
  69         OP___assert(GPIO_ID < N_GPIO_ID);
  70         OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1);
  71
  72         timed_ctrl_snd_commnd(ID, mask, condition, counter,
  73                                 GPIO_BASE[GPIO_ID]+offset, value);
  74 }