2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2010-2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __SYSTEM_LOCAL_H_INCLUDED__
16 #define __SYSTEM_LOCAL_H_INCLUDED__
18 #ifdef HRT_ISP_CSS_CUSTOM_HOST
19 #ifndef HRT_USE_VIR_ADDRS
20 #define HRT_USE_VIR_ADDRS
22 /* This interface is deprecated */
23 /*#include "hive_isp_css_custom_host_hrt.h"*/
26 #include "system_global.h"
29 #define HRT_ADDRESS_WIDTH 32 /* Surprise, this is a local property and even differs per platform */
31 /* HRT assumes 32 by default (see Linux/include/hrt/hive_types.h), overrule it in case it is different */
32 #undef HRT_ADDRESS_WIDTH
33 #define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
36 #if !defined(__KERNEL__) || (1==1)
37 /* This interface is deprecated */
38 #include "hrt/hive_types.h"
39 #else /* __KERNEL__ */
40 #include <linux/types.h>
42 #if HRT_ADDRESS_WIDTH==64
43 typedef uint64_t hrt_address;
44 #elif HRT_ADDRESS_WIDTH==32
45 typedef uint32_t hrt_address;
47 #error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
50 typedef uint32_t hrt_vaddress;
51 typedef uint32_t hrt_data;
52 #endif /* __KERNEL__ */
55 * Cell specific address maps
57 #if HRT_ADDRESS_WIDTH==64
59 #define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
62 static const hrt_address DDR_BASE[N_DDR_ID] = {
63 (hrt_address)0x0000000120000000ULL};
66 static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
67 (hrt_address)0x0000000000020000ULL};
69 static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
70 (hrt_address)0x0000000000200000ULL};
72 static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
73 (hrt_address)0x0000000000100000ULL};
75 static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
76 (hrt_address)0x00000000001C0000ULL,
77 (hrt_address)0x00000000001D0000ULL,
78 (hrt_address)0x00000000001E0000ULL};
80 static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
81 (hrt_address)0x00000000001F0000ULL};
84 static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
85 (hrt_address)0x0000000000010000ULL};
87 static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
88 (hrt_address)0x0000000000300000ULL};
90 static const hrt_address SP_PMEM_BASE[N_SP_ID] = {
91 (hrt_address)0x00000000000B0000ULL};
94 #if defined (IS_ISP_2400_MAMOIADA_SYSTEM) || defined (IS_ISP_2401_MAMOIADA_SYSTEM)
96 * MMU0_ID: The data MMU
97 * MMU1_ID: The icache MMU
99 static const hrt_address MMU_BASE[N_MMU_ID] = {
100 (hrt_address)0x0000000000070000ULL,
101 (hrt_address)0x00000000000A0000ULL};
103 #error "system_local.h: SYSTEM must be one of {2400, 2401 }"
107 static const hrt_address DMA_BASE[N_DMA_ID] = {
108 (hrt_address)0x0000000000040000ULL};
111 static const hrt_address IRQ_BASE[N_IRQ_ID] = {
112 (hrt_address)0x0000000000000500ULL,
113 (hrt_address)0x0000000000030A00ULL,
114 (hrt_address)0x000000000008C000ULL,
115 (hrt_address)0x0000000000090200ULL};
117 (hrt_address)0x0000000000000500ULL};
121 static const hrt_address GDC_BASE[N_GDC_ID] = {
122 (hrt_address)0x0000000000050000ULL,
123 (hrt_address)0x0000000000060000ULL};
125 /* FIFO_MONITOR (not a subset of GP_DEVICE) */
126 static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
127 (hrt_address)0x0000000000000000ULL};
130 static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
131 (hrt_address)0x0000000000000000ULL};
133 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
134 (hrt_address)0x0000000000090000ULL};
137 /* GP_DEVICE (single base for all separate GP_REG instances) */
138 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
139 (hrt_address)0x0000000000000000ULL};
141 /*GP TIMER , all timer registers are inter-twined,
142 * so, having multiple base addresses for
143 * different timers does not help*/
144 static const hrt_address GP_TIMER_BASE =
145 (hrt_address)0x0000000000000600ULL;
147 static const hrt_address GPIO_BASE[N_GPIO_ID] = {
148 (hrt_address)0x0000000000000400ULL};
151 static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
152 (hrt_address)0x0000000000000100ULL};
155 /* INPUT_FORMATTER */
156 static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
157 (hrt_address)0x0000000000030000ULL,
158 (hrt_address)0x0000000000030200ULL,
159 (hrt_address)0x0000000000030400ULL,
160 (hrt_address)0x0000000000030600ULL}; /* memcpy() */
163 static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
164 (hrt_address)0x0000000000080000ULL};
165 /* (hrt_address)0x0000000000081000ULL, */ /* capture A */
166 /* (hrt_address)0x0000000000082000ULL, */ /* capture B */
167 /* (hrt_address)0x0000000000083000ULL, */ /* capture C */
168 /* (hrt_address)0x0000000000084000ULL, */ /* Acquisition */
169 /* (hrt_address)0x0000000000085000ULL, */ /* DMA */
170 /* (hrt_address)0x0000000000089000ULL, */ /* ctrl */
171 /* (hrt_address)0x000000000008A000ULL, */ /* GP regs */
172 /* (hrt_address)0x000000000008B000ULL, */ /* FIFO */
173 /* (hrt_address)0x000000000008C000ULL, */ /* IRQ */
175 /* RX, the MIPI lane control regs start at offset 0 */
176 static const hrt_address RX_BASE[N_RX_ID] = {
177 (hrt_address)0x0000000000080100ULL};
179 #elif HRT_ADDRESS_WIDTH==32
181 #define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
183 /* DDR : Attention, this value not defined in 32-bit */
184 static const hrt_address DDR_BASE[N_DDR_ID] = {
185 (hrt_address)0x00000000UL};
188 static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
189 (hrt_address)0x00020000UL};
191 static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
192 (hrt_address)0x00200000UL};
194 static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
195 (hrt_address)0x100000UL};
197 static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
198 (hrt_address)0xffffffffUL,
199 (hrt_address)0xffffffffUL,
200 (hrt_address)0xffffffffUL};
202 static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
203 (hrt_address)0xffffffffUL};
206 static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
207 (hrt_address)0x00010000UL};
209 static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
210 (hrt_address)0x00300000UL};
212 static const hrt_address SP_PMEM_BASE[N_SP_ID] = {
213 (hrt_address)0x000B0000UL};
216 #if defined (IS_ISP_2400_MAMOIADA_SYSTEM) || defined (IS_ISP_2401_MAMOIADA_SYSTEM)
218 * MMU0_ID: The data MMU
219 * MMU1_ID: The icache MMU
221 static const hrt_address MMU_BASE[N_MMU_ID] = {
222 (hrt_address)0x00070000UL,
223 (hrt_address)0x000A0000UL};
225 #error "system_local.h: SYSTEM must be one of {2400, 2401 }"
229 static const hrt_address DMA_BASE[N_DMA_ID] = {
230 (hrt_address)0x00040000UL};
233 static const hrt_address IRQ_BASE[N_IRQ_ID] = {
234 (hrt_address)0x00000500UL,
235 (hrt_address)0x00030A00UL,
236 (hrt_address)0x0008C000UL,
237 (hrt_address)0x00090200UL};
239 (hrt_address)0x00000500UL};
243 static const hrt_address GDC_BASE[N_GDC_ID] = {
244 (hrt_address)0x00050000UL,
245 (hrt_address)0x00060000UL};
247 /* FIFO_MONITOR (not a subset of GP_DEVICE) */
248 static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
249 (hrt_address)0x00000000UL};
252 static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
253 (hrt_address)0x00000000UL};
255 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
256 (hrt_address)0x00090000UL};
259 /* GP_DEVICE (single base for all separate GP_REG instances) */
260 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
261 (hrt_address)0x00000000UL};
263 /*GP TIMER , all timer registers are inter-twined,
264 * so, having multiple base addresses for
265 * different timers does not help*/
266 static const hrt_address GP_TIMER_BASE =
267 (hrt_address)0x00000600UL;
270 static const hrt_address GPIO_BASE[N_GPIO_ID] = {
271 (hrt_address)0x00000400UL};
274 static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
275 (hrt_address)0x00000100UL};
278 /* INPUT_FORMATTER */
279 static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
280 (hrt_address)0x00030000UL,
281 (hrt_address)0x00030200UL,
282 (hrt_address)0x00030400UL};
283 /* (hrt_address)0x00030600UL, */ /* memcpy() */
286 static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
287 (hrt_address)0x00080000UL};
288 /* (hrt_address)0x00081000UL, */ /* capture A */
289 /* (hrt_address)0x00082000UL, */ /* capture B */
290 /* (hrt_address)0x00083000UL, */ /* capture C */
291 /* (hrt_address)0x00084000UL, */ /* Acquisition */
292 /* (hrt_address)0x00085000UL, */ /* DMA */
293 /* (hrt_address)0x00089000UL, */ /* ctrl */
294 /* (hrt_address)0x0008A000UL, */ /* GP regs */
295 /* (hrt_address)0x0008B000UL, */ /* FIFO */
296 /* (hrt_address)0x0008C000UL, */ /* IRQ */
298 /* RX, the MIPI lane control regs start at offset 0 */
299 static const hrt_address RX_BASE[N_RX_ID] = {
300 (hrt_address)0x00080100UL};
303 #error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
306 #endif /* __SYSTEM_LOCAL_H_INCLUDED__ */