drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system.c

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2010-015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include "system_global.h"
  16
  17 #ifdef USE_INPUT_SYSTEM_VERSION_2
  18
  19 #include "input_system.h"
  20 #include <type_support.h>
  21 #include "gp_device.h"
  22
  23 #include "assert_support.h"
  24
  25 #ifndef __INLINE_INPUT_SYSTEM__
  26 #include "input_system_private.h"
  27 #endif /* __INLINE_INPUT_SYSTEM__ */
  28
  29 #define ZERO (0x0)
  30 #define ONE  (1U)
  31
  32 const ib_buffer_t   IB_BUFFER_NULL = {0 ,0, 0 };
  33
  34 static input_system_error_t input_system_configure_channel(
  35         const channel_cfg_t             channel);
  36
  37 static input_system_error_t input_system_configure_channel_sensor(
  38         const channel_cfg_t             channel);
  39
  40 static input_system_error_t input_buffer_configuration(void);
  41
  42 static input_system_error_t configuration_to_registers(void);
  43
  44 static void receiver_rst(const rx_ID_t ID);
  45 static void input_system_network_rst(const input_system_ID_t ID);
  46
  47 static void capture_unit_configure(
  48         const input_system_ID_t                 ID,
  49         const sub_system_ID_t                   sub_id,
  50         const ib_buffer_t* const                cfg);
  51
  52 static void acquisition_unit_configure(
  53         const input_system_ID_t                 ID,
  54         const sub_system_ID_t                   sub_id,
  55         const ib_buffer_t* const                cfg);
  56
  57 static void ctrl_unit_configure(
  58         const input_system_ID_t                 ID,
  59         const sub_system_ID_t                   sub_id,
  60         const ctrl_unit_cfg_t* const    cfg);
  61
  62 static void input_system_network_configure(
  63         const input_system_ID_t                 ID,
  64         const input_system_network_cfg_t * const        cfg);
  65
  66 // MW: CSI is previously named as "rx" short for "receiver"
  67 static input_system_error_t set_csi_cfg(
  68         csi_cfg_t* const                                                lhs,
  69         const csi_cfg_t* const                                  rhs,
  70         input_system_config_flags_t* const              flags);
  71
  72 static input_system_error_t set_source_type(
  73         input_system_source_t* const                    lhs,
  74         const input_system_source_t                             rhs,
  75         input_system_config_flags_t* const              flags);
  76
  77 static input_system_error_t input_system_multiplexer_cfg(
  78         input_system_multiplex_t* const                 lhs,
  79         const input_system_multiplex_t                  rhs,
  80         input_system_config_flags_t* const              flags);
  81
  82
  83
  84 STORAGE_CLASS_INLINE void capture_unit_get_state(
  85         const input_system_ID_t                 ID,
  86         const sub_system_ID_t                   sub_id,
  87         capture_unit_state_t                    *state);
  88
  89 STORAGE_CLASS_INLINE void acquisition_unit_get_state(
  90         const input_system_ID_t                 ID,
  91         const sub_system_ID_t                   sub_id,
  92         acquisition_unit_state_t                *state);
  93
  94 STORAGE_CLASS_INLINE void ctrl_unit_get_state(
  95         const input_system_ID_t                 ID,
  96         const sub_system_ID_t                   sub_id,
  97         ctrl_unit_state_t                               *state);
  98
  99 STORAGE_CLASS_INLINE void mipi_port_get_state(
 100         const rx_ID_t                                   ID,
 101         const mipi_port_ID_t                    port_ID,
 102         mipi_port_state_t                               *state);
 103
 104 STORAGE_CLASS_INLINE void rx_channel_get_state(
 105         const rx_ID_t                                   ID,
 106         const unsigned int                              ch_id,
 107         rx_channel_state_t                              *state);
 108
 109 static void gp_device_rst(const gp_device_ID_t          ID);
 110
 111 static void input_selector_cfg_for_sensor(const gp_device_ID_t  ID);
 112
 113 static void input_switch_rst(const gp_device_ID_t       ID);
 114
 115 static void input_switch_cfg(
 116         const gp_device_ID_t                            ID,
 117         const input_switch_cfg_t * const        cfg
 118 );
 119
 120 void input_system_get_state(
 121         const input_system_ID_t                 ID,
 122         input_system_state_t                    *state)
 123 {
 124         sub_system_ID_t sub_id;
 125
 126         assert(ID < N_INPUT_SYSTEM_ID);
 127         assert(state != NULL);
 128
 129         state->str_multicastA_sel = input_system_sub_system_reg_load(ID,
 130                 GPREGS_UNIT0_ID,
 131                 HIVE_ISYS_GPREG_MULTICAST_A_IDX);
 132         state->str_multicastB_sel = input_system_sub_system_reg_load(ID,
 133                 GPREGS_UNIT0_ID,
 134                 HIVE_ISYS_GPREG_MULTICAST_B_IDX);
 135         state->str_multicastC_sel = input_system_sub_system_reg_load(ID,
 136                 GPREGS_UNIT0_ID,
 137                 HIVE_ISYS_GPREG_MULTICAST_C_IDX);
 138         state->str_mux_sel = input_system_sub_system_reg_load(ID,
 139                 GPREGS_UNIT0_ID,
 140                 HIVE_ISYS_GPREG_MUX_IDX);
 141         state->str_mon_status = input_system_sub_system_reg_load(ID,
 142                 GPREGS_UNIT0_ID,
 143                 HIVE_ISYS_GPREG_STRMON_STAT_IDX);
 144         state->str_mon_irq_cond = input_system_sub_system_reg_load(ID,
 145                 GPREGS_UNIT0_ID,
 146                 HIVE_ISYS_GPREG_STRMON_COND_IDX);
 147         state->str_mon_irq_en = input_system_sub_system_reg_load(ID,
 148                 GPREGS_UNIT0_ID,
 149                 HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX);
 150         state->isys_srst = input_system_sub_system_reg_load(ID,
 151                 GPREGS_UNIT0_ID,
 152                 HIVE_ISYS_GPREG_SRST_IDX);
 153         state->isys_slv_reg_srst = input_system_sub_system_reg_load(ID,
 154                 GPREGS_UNIT0_ID,
 155                 HIVE_ISYS_GPREG_SLV_REG_SRST_IDX);
 156         state->str_deint_portA_cnt = input_system_sub_system_reg_load(ID,
 157                 GPREGS_UNIT0_ID,
 158                 HIVE_ISYS_GPREG_REG_PORT_A_IDX);
 159         state->str_deint_portB_cnt = input_system_sub_system_reg_load(ID,
 160                 GPREGS_UNIT0_ID,
 161                 HIVE_ISYS_GPREG_REG_PORT_B_IDX);
 162
 163         for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) {
 164                 capture_unit_get_state(ID, sub_id,
 165                         &(state->capture_unit[sub_id - CAPTURE_UNIT0_ID]));
 166         }
 167         for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) {
 168                 acquisition_unit_get_state(ID, sub_id,
 169                         &(state->acquisition_unit[sub_id - ACQUISITION_UNIT0_ID]));
 170         }
 171         for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) {
 172                 ctrl_unit_get_state(ID, sub_id,
 173                         &(state->ctrl_unit_state[sub_id - CTRL_UNIT0_ID]));
 174         }
 175
 176 return;
 177 }
 178
 179 void receiver_get_state(
 180         const rx_ID_t                           ID,
 181         receiver_state_t                        *state)
 182 {
 183         mipi_port_ID_t  port_id;
 184         unsigned int    ch_id;
 185
 186         assert(ID < N_RX_ID);
 187         assert(state != NULL);
 188
 189         state->fs_to_ls_delay = (uint8_t)receiver_reg_load(ID,
 190                 _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX);
 191         state->ls_to_data_delay = (uint8_t)receiver_reg_load(ID,
 192                 _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX);
 193         state->data_to_le_delay = (uint8_t)receiver_reg_load(ID,
 194                 _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX);
 195         state->le_to_fe_delay = (uint8_t)receiver_reg_load(ID,
 196                 _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX);
 197         state->fe_to_fs_delay = (uint8_t)receiver_reg_load(ID,
 198                 _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX);
 199         state->le_to_fs_delay = (uint8_t)receiver_reg_load(ID,
 200                 _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX);
 201         state->is_two_ppc = (bool)receiver_reg_load(ID,
 202                 _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX);
 203         state->backend_rst = receiver_reg_load(ID,
 204                 _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX);
 205         state->raw18 = (uint16_t)receiver_reg_load(ID,
 206                 _HRT_CSS_RECEIVER_RAW18_REG_IDX);
 207         state->force_raw8 = (bool)receiver_reg_load(ID,
 208                 _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX);
 209         state->raw16 = (uint16_t)receiver_reg_load(ID,
 210                 _HRT_CSS_RECEIVER_RAW16_REG_IDX);
 211
 212         for (port_id = (mipi_port_ID_t)0; port_id < N_MIPI_PORT_ID; port_id++) {
 213                 mipi_port_get_state(ID, port_id,
 214                         &(state->mipi_port_state[port_id]));
 215         }
 216         for (ch_id = (unsigned int)0; ch_id < N_RX_CHANNEL_ID; ch_id++) {
 217                 rx_channel_get_state(ID, ch_id,
 218                         &(state->rx_channel_state[ch_id]));
 219         }
 220
 221         state->be_gsp_acc_ovl = receiver_reg_load(ID,
 222                 _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX);
 223         state->be_srst = receiver_reg_load(ID,
 224                 _HRT_CSS_RECEIVER_BE_SRST_REG_IDX);
 225         state->be_is_two_ppc = receiver_reg_load(ID,
 226                 _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX);
 227         state->be_comp_format0 = receiver_reg_load(ID,
 228                 _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX);
 229         state->be_comp_format1 = receiver_reg_load(ID,
 230                 _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX);
 231         state->be_comp_format2 = receiver_reg_load(ID,
 232                 _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX);
 233         state->be_comp_format3 = receiver_reg_load(ID,
 234                 _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX);
 235         state->be_sel = receiver_reg_load(ID,
 236                 _HRT_CSS_RECEIVER_BE_SEL_REG_IDX);
 237         state->be_raw16_config = receiver_reg_load(ID,
 238                 _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX);
 239         state->be_raw18_config = receiver_reg_load(ID,
 240                 _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX);
 241         state->be_force_raw8 = receiver_reg_load(ID,
 242                 _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX);
 243         state->be_irq_status = receiver_reg_load(ID,
 244                 _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX);
 245         state->be_irq_clear = receiver_reg_load(ID,
 246                 _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX);
 247
 248 return;
 249 }
 250
 251 bool is_mipi_format_yuv420(
 252         const mipi_format_t                     mipi_format)
 253 {
 254         bool    is_yuv420 = (
 255                 (mipi_format == MIPI_FORMAT_YUV420_8) ||
 256                 (mipi_format == MIPI_FORMAT_YUV420_10) ||
 257                 (mipi_format == MIPI_FORMAT_YUV420_8_SHIFT) ||
 258                 (mipi_format == MIPI_FORMAT_YUV420_10_SHIFT));
 259 /* MIPI_FORMAT_YUV420_8_LEGACY is not YUV420 */
 260
 261 return is_yuv420;
 262 }
 263
 264 void receiver_set_compression(
 265         const rx_ID_t                   ID,
 266         const unsigned int              cfg_ID,
 267         const mipi_compressor_t         comp,
 268         const mipi_predictor_t          pred)
 269 {
 270         const unsigned int              field_id = cfg_ID % N_MIPI_FORMAT_CUSTOM;
 271         const unsigned int              ch_id = cfg_ID / N_MIPI_FORMAT_CUSTOM;
 272         hrt_data                        val;
 273         hrt_address                     addr = 0;
 274         hrt_data                        reg;
 275
 276         assert(ID < N_RX_ID);
 277         assert(cfg_ID < N_MIPI_COMPRESSOR_CONTEXT);
 278         assert(field_id < N_MIPI_FORMAT_CUSTOM);
 279         assert(ch_id < N_RX_CHANNEL_ID);
 280         assert(comp < N_MIPI_COMPRESSOR_METHODS);
 281         assert(pred < N_MIPI_PREDICTOR_TYPES);
 282
 283         val = (((uint8_t)pred) << 3) | comp;
 284
 285         switch (ch_id) {
 286         case 0: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX);
 287                 break;
 288         case 1: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX);
 289                 break;
 290         case 2: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX);
 291                 break;
 292         case 3: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX);
 293                 break;
 294         default:
 295                 /* should not happen */
 296                 assert(false);
 297                 return;
 298         }
 299
 300         reg = ((field_id < 6)?(val << (field_id * 5)):(val << ((field_id - 6) * 5)));
 301         receiver_reg_store(ID, addr, reg);
 302
 303 return;
 304 }
 305
 306 void receiver_port_enable(
 307         const rx_ID_t                   ID,
 308         const mipi_port_ID_t            port_ID,
 309         const bool                      cnd)
 310 {
 311         hrt_data        reg = receiver_port_reg_load(ID, port_ID,
 312                 _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
 313
 314         if (cnd) {
 315                 reg |= 0x01;
 316         } else {
 317                 reg &= ~0x01;
 318         }
 319
 320         receiver_port_reg_store(ID, port_ID,
 321                 _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, reg);
 322 return;
 323 }
 324
 325 bool is_receiver_port_enabled(
 326         const rx_ID_t                   ID,
 327         const mipi_port_ID_t            port_ID)
 328 {
 329         hrt_data        reg = receiver_port_reg_load(ID, port_ID,
 330                 _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
 331 return ((reg & 0x01) != 0);
 332 }
 333
 334 void receiver_irq_enable(
 335         const rx_ID_t                   ID,
 336         const mipi_port_ID_t            port_ID,
 337         const rx_irq_info_t             irq_info)
 338 {
 339         receiver_port_reg_store(ID,
 340                 port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, irq_info);
 341 return;
 342 }
 343
 344 rx_irq_info_t receiver_get_irq_info(
 345         const rx_ID_t                   ID,
 346         const mipi_port_ID_t            port_ID)
 347 {
 348 return receiver_port_reg_load(ID,
 349         port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
 350 }
 351
 352 void receiver_irq_clear(
 353         const rx_ID_t                   ID,
 354         const mipi_port_ID_t            port_ID,
 355         const rx_irq_info_t             irq_info)
 356 {
 357         receiver_port_reg_store(ID,
 358                 port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX, irq_info);
 359 return;
 360 }
 361
 362 STORAGE_CLASS_INLINE void capture_unit_get_state(
 363         const input_system_ID_t                 ID,
 364         const sub_system_ID_t                   sub_id,
 365         capture_unit_state_t                    *state)
 366 {
 367         assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID));
 368         assert(state != NULL);
 369
 370         state->StartMode = input_system_sub_system_reg_load(ID,
 371                 sub_id,
 372                 CAPT_START_MODE_REG_ID);
 373         state->Start_Addr = input_system_sub_system_reg_load(ID,
 374                 sub_id,
 375                 CAPT_START_ADDR_REG_ID);
 376         state->Mem_Region_Size = input_system_sub_system_reg_load(ID,
 377                 sub_id,
 378                 CAPT_MEM_REGION_SIZE_REG_ID);
 379         state->Num_Mem_Regions = input_system_sub_system_reg_load(ID,
 380                 sub_id,
 381                 CAPT_NUM_MEM_REGIONS_REG_ID);
 382 //      AM: Illegal read from following registers.
 383 /*      state->Init = input_system_sub_system_reg_load(ID,
 384                 sub_id,
 385                 CAPT_INIT_REG_ID);
 386         state->Start = input_system_sub_system_reg_load(ID,
 387                 sub_id,
 388                 CAPT_START_REG_ID);
 389         state->Stop = input_system_sub_system_reg_load(ID,
 390                 sub_id,
 391                 CAPT_STOP_REG_ID);
 392 */
 393         state->Packet_Length = input_system_sub_system_reg_load(ID,
 394                 sub_id,
 395                 CAPT_PACKET_LENGTH_REG_ID);
 396         state->Received_Length = input_system_sub_system_reg_load(ID,
 397                 sub_id,
 398                 CAPT_RECEIVED_LENGTH_REG_ID);
 399         state->Received_Short_Packets = input_system_sub_system_reg_load(ID,
 400                 sub_id,
 401                 CAPT_RECEIVED_SHORT_PACKETS_REG_ID);
 402         state->Received_Long_Packets = input_system_sub_system_reg_load(ID,
 403                 sub_id,
 404                 CAPT_RECEIVED_LONG_PACKETS_REG_ID);
 405         state->Last_Command = input_system_sub_system_reg_load(ID,
 406                 sub_id,
 407                 CAPT_LAST_COMMAND_REG_ID);
 408         state->Next_Command = input_system_sub_system_reg_load(ID,
 409                 sub_id,
 410                 CAPT_NEXT_COMMAND_REG_ID);
 411         state->Last_Acknowledge = input_system_sub_system_reg_load(ID,
 412                 sub_id,
 413                 CAPT_LAST_ACKNOWLEDGE_REG_ID);
 414         state->Next_Acknowledge = input_system_sub_system_reg_load(ID,
 415                 sub_id,
 416                 CAPT_NEXT_ACKNOWLEDGE_REG_ID);
 417         state->FSM_State_Info = input_system_sub_system_reg_load(ID,
 418                 sub_id,
 419                 CAPT_FSM_STATE_INFO_REG_ID);
 420
 421 return;
 422 }
 423
 424 STORAGE_CLASS_INLINE void acquisition_unit_get_state(
 425         const input_system_ID_t                 ID,
 426         const sub_system_ID_t                   sub_id,
 427         acquisition_unit_state_t                *state)
 428 {
 429         assert(sub_id == ACQUISITION_UNIT0_ID);
 430         assert(state != NULL);
 431
 432         state->Start_Addr = input_system_sub_system_reg_load(ID,
 433                 sub_id,
 434                 ACQ_START_ADDR_REG_ID);
 435         state->Mem_Region_Size = input_system_sub_system_reg_load(ID,
 436                 sub_id,
 437                 ACQ_MEM_REGION_SIZE_REG_ID);
 438         state->Num_Mem_Regions = input_system_sub_system_reg_load(ID,
 439                 sub_id,
 440                 ACQ_NUM_MEM_REGIONS_REG_ID);
 441 //      AM: Illegal read from following registers.
 442 /*      state->Init = input_system_sub_system_reg_load(ID,
 443                 sub_id,
 444                 ACQ_INIT_REG_ID);
 445 */
 446         state->Received_Short_Packets = input_system_sub_system_reg_load(ID,
 447                 sub_id,
 448                 ACQ_RECEIVED_SHORT_PACKETS_REG_ID);
 449         state->Received_Long_Packets = input_system_sub_system_reg_load(ID,
 450                 sub_id,
 451                 ACQ_RECEIVED_LONG_PACKETS_REG_ID);
 452         state->Last_Command = input_system_sub_system_reg_load(ID,
 453                 sub_id,
 454                 ACQ_LAST_COMMAND_REG_ID);
 455         state->Next_Command = input_system_sub_system_reg_load(ID,
 456                 sub_id,
 457                 ACQ_NEXT_COMMAND_REG_ID);
 458         state->Last_Acknowledge = input_system_sub_system_reg_load(ID,
 459                 sub_id,
 460                 ACQ_LAST_ACKNOWLEDGE_REG_ID);
 461         state->Next_Acknowledge = input_system_sub_system_reg_load(ID,
 462                 sub_id,
 463                 ACQ_NEXT_ACKNOWLEDGE_REG_ID);
 464         state->FSM_State_Info = input_system_sub_system_reg_load(ID,
 465                 sub_id,
 466                 ACQ_FSM_STATE_INFO_REG_ID);
 467         state->Int_Cntr_Info = input_system_sub_system_reg_load(ID,
 468                 sub_id,
 469                 ACQ_INT_CNTR_INFO_REG_ID);
 470
 471 return;
 472 }
 473
 474 STORAGE_CLASS_INLINE void ctrl_unit_get_state(
 475         const input_system_ID_t                 ID,
 476         const sub_system_ID_t                   sub_id,
 477         ctrl_unit_state_t                       *state)
 478 {
 479         assert(sub_id == CTRL_UNIT0_ID);
 480         assert(state != NULL);
 481
 482         state->captA_start_addr = input_system_sub_system_reg_load(ID,
 483                 sub_id,
 484                 ISYS_CTRL_CAPT_START_ADDR_A_REG_ID);
 485         state->captB_start_addr = input_system_sub_system_reg_load(ID,
 486                 sub_id,
 487                 ISYS_CTRL_CAPT_START_ADDR_B_REG_ID);
 488         state->captC_start_addr = input_system_sub_system_reg_load(ID,
 489                 sub_id,
 490                 ISYS_CTRL_CAPT_START_ADDR_C_REG_ID);
 491         state->captA_mem_region_size = input_system_sub_system_reg_load(ID,
 492                 sub_id,
 493                 ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID);
 494         state->captB_mem_region_size = input_system_sub_system_reg_load(ID,
 495                 sub_id,
 496                 ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID);
 497         state->captC_mem_region_size = input_system_sub_system_reg_load(ID,
 498                 sub_id,
 499                 ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID);
 500         state->captA_num_mem_regions = input_system_sub_system_reg_load(ID,
 501                 sub_id,
 502                 ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID);
 503         state->captB_num_mem_regions = input_system_sub_system_reg_load(ID,
 504                 sub_id,
 505                 ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID);
 506         state->captC_num_mem_regions = input_system_sub_system_reg_load(ID,
 507                 sub_id,
 508                 ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID);
 509         state->acq_start_addr = input_system_sub_system_reg_load(ID,
 510                 sub_id,
 511                 ISYS_CTRL_ACQ_START_ADDR_REG_ID);
 512         state->acq_mem_region_size = input_system_sub_system_reg_load(ID,
 513                 sub_id,
 514                 ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID);
 515         state->acq_num_mem_regions = input_system_sub_system_reg_load(ID,
 516                 sub_id,
 517                 ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID);
 518 //      AM: Illegal read from following registers.
 519 /*      state->ctrl_init = input_system_sub_system_reg_load(ID,
 520                 sub_id,
 521                 ISYS_CTRL_INIT_REG_ID);
 522 */
 523         state->last_cmd = input_system_sub_system_reg_load(ID,
 524                 sub_id,
 525                 ISYS_CTRL_LAST_COMMAND_REG_ID);
 526         state->next_cmd = input_system_sub_system_reg_load(ID,
 527                 sub_id,
 528                 ISYS_CTRL_NEXT_COMMAND_REG_ID);
 529         state->last_ack = input_system_sub_system_reg_load(ID,
 530                 sub_id,
 531                 ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID);
 532         state->next_ack = input_system_sub_system_reg_load(ID,
 533                 sub_id,
 534                 ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID);
 535         state->top_fsm_state = input_system_sub_system_reg_load(ID,
 536                 sub_id,
 537                 ISYS_CTRL_FSM_STATE_INFO_REG_ID);
 538         state->captA_fsm_state = input_system_sub_system_reg_load(ID,
 539                 sub_id,
 540                 ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID);
 541         state->captB_fsm_state = input_system_sub_system_reg_load(ID,
 542                 sub_id,
 543                 ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID);
 544         state->captC_fsm_state = input_system_sub_system_reg_load(ID,
 545                 sub_id,
 546                 ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID);
 547         state->acq_fsm_state = input_system_sub_system_reg_load(ID,
 548                 sub_id,
 549                 ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID);
 550         state->capt_reserve_one_mem_region = input_system_sub_system_reg_load(ID,
 551                 sub_id,
 552                 ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID);
 553
 554 return;
 555 }
 556
 557 STORAGE_CLASS_INLINE void mipi_port_get_state(
 558         const rx_ID_t                           ID,
 559         const mipi_port_ID_t                    port_ID,
 560         mipi_port_state_t                       *state)
 561 {
 562         int     i;
 563
 564         assert(ID < N_RX_ID);
 565         assert(port_ID < N_MIPI_PORT_ID);
 566         assert(state != NULL);
 567
 568         state->device_ready = receiver_port_reg_load(ID,
 569                 port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
 570         state->irq_status = receiver_port_reg_load(ID,
 571                 port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
 572         state->irq_enable = receiver_port_reg_load(ID,
 573                 port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
 574         state->timeout_count = receiver_port_reg_load(ID,
 575                 port_ID, _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX);
 576         state->init_count = (uint16_t)receiver_port_reg_load(ID,
 577                 port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX);
 578         state->raw16_18 = (uint16_t)receiver_port_reg_load(ID,
 579                 port_ID, _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX);
 580         state->sync_count = receiver_port_reg_load(ID,
 581                 port_ID, _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX);
 582         state->rx_count = receiver_port_reg_load(ID,
 583                 port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX);
 584
 585         for (i = 0; i < MIPI_4LANE_CFG ; i++) {
 586                 state->lane_sync_count[i] = (uint8_t)((state->sync_count)>>(i*8));
 587                 state->lane_rx_count[i] = (uint8_t)((state->rx_count)>>(i*8));
 588         }
 589
 590 return;
 591 }
 592
 593 STORAGE_CLASS_INLINE void rx_channel_get_state(
 594         const rx_ID_t                                   ID,
 595         const unsigned int                              ch_id,
 596         rx_channel_state_t                              *state)
 597 {
 598         int     i;
 599
 600         assert(ID < N_RX_ID);
 601         assert(ch_id < N_RX_CHANNEL_ID);
 602         assert(state != NULL);
 603
 604         switch (ch_id) {
 605                 case 0:
 606                         state->comp_scheme0 = receiver_reg_load(ID,
 607                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX);
 608                         state->comp_scheme1 = receiver_reg_load(ID,
 609                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX);
 610         break;
 611                 case 1:
 612                         state->comp_scheme0 = receiver_reg_load(ID,
 613                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX);
 614                         state->comp_scheme1 = receiver_reg_load(ID,
 615                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX);
 616         break;
 617                 case 2:
 618                         state->comp_scheme0 = receiver_reg_load(ID,
 619                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX);
 620                         state->comp_scheme1 = receiver_reg_load(ID,
 621                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX);
 622         break;
 623                 case 3:
 624                         state->comp_scheme0 = receiver_reg_load(ID,
 625                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX);
 626                         state->comp_scheme1 = receiver_reg_load(ID,
 627                                 _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX);
 628         break;
 629         }
 630
 631 /* See Table 7.1.17,..., 7.1.24 */
 632         for (i = 0; i < 6; i++) {
 633                 uint8_t val = (uint8_t)((state->comp_scheme0)>>(i*5)) & 0x1f;
 634                 state->comp[i] = (mipi_compressor_t)(val & 0x07);
 635                 state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
 636         }
 637         for (i = 6; i < N_MIPI_FORMAT_CUSTOM; i++) {
 638                 uint8_t val = (uint8_t)((state->comp_scheme0)>>((i-6)*5)) & 0x1f;
 639                 state->comp[i] = (mipi_compressor_t)(val & 0x07);
 640                 state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
 641         }
 642
 643 return;
 644 }
 645
 646 // MW: "2400" in the name is not good, but this is to avoid a naming conflict
 647 input_system_cfg2400_t config;
 648
 649 static void receiver_rst(
 650         const rx_ID_t                           ID)
 651 {
 652         mipi_port_ID_t          port_id;
 653
 654         assert(ID < N_RX_ID);
 655
 656 // Disable all ports.
 657         for (port_id = MIPI_PORT0_ID; port_id < N_MIPI_PORT_ID; port_id++) {
 658                 receiver_port_enable(ID, port_id, false);
 659         }
 660
 661         // AM: Additional actions for stopping receiver?
 662
 663         return;
 664 }
 665
 666 //Single function to reset all the devices mapped via GP_DEVICE.
 667 static void gp_device_rst(const gp_device_ID_t          ID)
 668 {
 669         assert(ID < N_GP_DEVICE_ID);
 670
 671         gp_device_reg_store(ID, _REG_GP_SYNCGEN_ENABLE_ADDR, ZERO);
 672         // gp_device_reg_store(ID, _REG_GP_SYNCGEN_FREE_RUNNING_ADDR, ZERO);
 673         // gp_device_reg_store(ID, _REG_GP_SYNCGEN_PAUSE_ADDR, ONE);
 674         // gp_device_reg_store(ID, _REG_GP_NR_FRAMES_ADDR, ZERO);
 675         // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO);
 676         // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO);
 677         // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_LINES_ADDR, ZERO);
 678         // gp_device_reg_store(ID, _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR, ZERO);
 679         // gp_device_reg_store(ID, _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR, ZERO);
 680 // AM: Following calls cause strange warnings. Probably they should not be initialized.
 681 //      gp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ZERO);
 682 //      gp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ZERO);
 683 //      gp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ZERO);
 684 //      gp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ZERO);
 685         gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_ADDR, ZERO);
 686         gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_B_ADDR, ZERO);
 687         gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR, ZERO);
 688         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_ADDR, ZERO);
 689         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_B_ADDR, ZERO);
 690         gp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_MASK_ADDR, ZERO);
 691         gp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_MASK_ADDR, ZERO);
 692         gp_device_reg_store(ID, _REG_GP_ISEL_XY_CNT_MASK_ADDR, ZERO);
 693         gp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_DELTA_ADDR, ZERO);
 694         gp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_DELTA_ADDR, ZERO);
 695         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_MODE_ADDR, ZERO);
 696         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED1_ADDR, ZERO);
 697         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN1_ADDR, ZERO);
 698         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE1_ADDR, ZERO);
 699         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED2_ADDR, ZERO);
 700         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN2_ADDR, ZERO);
 701         gp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE2_ADDR, ZERO);
 702         //gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO);
 703         //gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO);
 704         gp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO);
 705         gp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO);
 706         gp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO);
 707         //      gp_device_reg_store(ID, _REG_GP_SYNCGEN_HOR_CNT_ADDR, ZERO);
 708         //      gp_device_reg_store(ID, _REG_GP_SYNCGEN_VER_CNT_ADDR, ZERO);
 709         //      gp_device_reg_store(ID, _REG_GP_SYNCGEN_FRAME_CNT_ADDR, ZERO);
 710         gp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR, ZERO); // AM: Maybe this soft reset is not safe.
 711
 712         return;
 713 }
 714
 715 static void input_selector_cfg_for_sensor(const gp_device_ID_t ID)
 716 {
 717         assert(ID < N_GP_DEVICE_ID);
 718
 719         gp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ONE);
 720         gp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ONE);
 721         gp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ONE);
 722         gp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ONE);
 723         gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO);
 724         gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO);
 725         gp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO);
 726         gp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO);
 727         gp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO);
 728         gp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR, ZERO);
 729
 730         return;
 731 }
 732
 733 static void input_switch_rst(const gp_device_ID_t ID)
 734 {
 735         int addr;
 736
 737         assert(ID < N_GP_DEVICE_ID);
 738
 739         // Initialize the data&hsync LUT.
 740         for (addr = _REG_GP_IFMT_input_switch_lut_reg0;
 741                          addr <= _REG_GP_IFMT_input_switch_lut_reg7; addr += SIZEOF_HRT_REG) {
 742
 743                 gp_device_reg_store(ID, addr, ZERO);
 744         }
 745
 746         // Initialize the vsync LUT.
 747         gp_device_reg_store(ID,
 748                 _REG_GP_IFMT_input_switch_fsync_lut,
 749                 ZERO);
 750
 751         return;
 752 }
 753
 754 static void input_switch_cfg(
 755         const gp_device_ID_t                    ID,
 756         const input_switch_cfg_t * const        cfg)
 757 {
 758         int addr_offset;
 759
 760         assert(ID < N_GP_DEVICE_ID);
 761         assert(cfg != NULL);
 762
 763         // Initialize the data&hsync LUT.
 764         for (addr_offset = 0; addr_offset < N_RX_CHANNEL_ID * 2; addr_offset++) {
 765                 assert(addr_offset * SIZEOF_HRT_REG + _REG_GP_IFMT_input_switch_lut_reg0 <= _REG_GP_IFMT_input_switch_lut_reg7);
 766                 gp_device_reg_store(ID,
 767                         _REG_GP_IFMT_input_switch_lut_reg0 + addr_offset * SIZEOF_HRT_REG,
 768                         cfg->hsync_data_reg[addr_offset]);
 769         }
 770
 771         // Initialize the vsync LUT.
 772         gp_device_reg_store(ID,
 773                 _REG_GP_IFMT_input_switch_fsync_lut,
 774                 cfg->vsync_data_reg);
 775
 776         return;
 777 }
 778
 779
 780 static void input_system_network_rst(const input_system_ID_t ID)
 781 {
 782         unsigned int sub_id;
 783
 784         // Reset all 3 multicasts.
 785         input_system_sub_system_reg_store(ID,
 786                 GPREGS_UNIT0_ID,
 787                 HIVE_ISYS_GPREG_MULTICAST_A_IDX,
 788                 INPUT_SYSTEM_DISCARD_ALL);
 789         input_system_sub_system_reg_store(ID,
 790                 GPREGS_UNIT0_ID,
 791                 HIVE_ISYS_GPREG_MULTICAST_B_IDX,
 792                 INPUT_SYSTEM_DISCARD_ALL);
 793         input_system_sub_system_reg_store(ID,
 794                 GPREGS_UNIT0_ID,
 795                 HIVE_ISYS_GPREG_MULTICAST_C_IDX,
 796                 INPUT_SYSTEM_DISCARD_ALL);
 797
 798         // Reset stream mux.
 799         input_system_sub_system_reg_store(ID,
 800                 GPREGS_UNIT0_ID,
 801                 HIVE_ISYS_GPREG_MUX_IDX,
 802                 N_INPUT_SYSTEM_MULTIPLEX);
 803
 804         // Reset 3 capture units.
 805         for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) {
 806                 input_system_sub_system_reg_store(ID,
 807                         sub_id,
 808                         CAPT_INIT_REG_ID,
 809                         1U << CAPT_INIT_RST_REG_BIT);
 810         }
 811
 812         // Reset acquisition unit.
 813         for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) {
 814                 input_system_sub_system_reg_store(ID,
 815                         sub_id,
 816                         ACQ_INIT_REG_ID,
 817                         1U << ACQ_INIT_RST_REG_BIT);
 818         }
 819
 820         // DMA unit reset is not needed.
 821
 822         // Reset controller units.
 823         // NB: In future we need to keep part of ctrl_state for split capture and
 824         for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) {
 825                 input_system_sub_system_reg_store(ID,
 826                         sub_id,
 827                         ISYS_CTRL_INIT_REG_ID,
 828                         1U); //AM: Is there any named constant?
 829         }
 830
 831         return;
 832 }
 833
 834 // Function that resets current configuration.
 835 input_system_error_t input_system_configuration_reset(void)
 836 {
 837         unsigned int i;
 838
 839         receiver_rst(RX0_ID);
 840
 841         input_system_network_rst(INPUT_SYSTEM0_ID);
 842
 843         gp_device_rst(INPUT_SYSTEM0_ID);
 844
 845         input_switch_rst(INPUT_SYSTEM0_ID);
 846
 847         //target_rst();
 848
 849         // Reset IRQ_CTRLs.
 850
 851         // Reset configuration data structures.
 852         for (i = 0; i < N_CHANNELS; i++ ) {
 853                 config.ch_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
 854                 config.target_isp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
 855                 config.target_sp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
 856                 config.target_strm2mem_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
 857         }
 858
 859         for (i = 0; i < N_CSI_PORTS; i++ ) {
 860                 config.csi_buffer_flags[i]       = INPUT_SYSTEM_CFG_FLAG_RESET;
 861                 config.multicast[i]              = INPUT_SYSTEM_CFG_FLAG_RESET;
 862         }
 863
 864         config.source_type_flags                                 = INPUT_SYSTEM_CFG_FLAG_RESET;
 865         config.acquisition_buffer_unique_flags   = INPUT_SYSTEM_CFG_FLAG_RESET;
 866         config.unallocated_ib_mem_words                  = IB_CAPACITY_IN_WORDS;
 867         //config.acq_allocated_ib_mem_words              = 0;
 868
 869         // Set the start of the session cofiguration.
 870         config.session_flags = INPUT_SYSTEM_CFG_FLAG_REQUIRED;
 871
 872         return INPUT_SYSTEM_ERR_NO_ERROR;
 873 }
 874
 875 // MW: Comments are good, but doxygen is required, place it at the declaration
 876 // Function that appends the channel to current configuration.
 877 static input_system_error_t input_system_configure_channel(
 878         const channel_cfg_t             channel)
 879 {
 880         input_system_error_t error = INPUT_SYSTEM_ERR_NO_ERROR;
 881         // Check if channel is not already configured.
 882         if (config.ch_flags[channel.ch_id] & INPUT_SYSTEM_CFG_FLAG_SET){
 883                 return INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET;
 884         } else {
 885                 switch (channel.source_type){
 886                         case INPUT_SYSTEM_SOURCE_SENSOR :
 887                                 error = input_system_configure_channel_sensor(channel);
 888                                 break;
 889                         case INPUT_SYSTEM_SOURCE_TPG :
 890                                 return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
 891                                 break;
 892                         case INPUT_SYSTEM_SOURCE_PRBS :
 893                                 return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
 894                                 break;
 895                         case INPUT_SYSTEM_SOURCE_FIFO :
 896                                 return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
 897                                 break;
 898                         default :
 899                                 return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
 900                                 break;
 901                 }
 902
 903                 if (error != INPUT_SYSTEM_ERR_NO_ERROR) return error;
 904                 // Input switch channel configurations must be combined in united config.
 905                 config.input_switch_cfg.hsync_data_reg[channel.source_cfg.csi_cfg.csi_port * 2] =
 906                                 channel.target_cfg.input_switch_channel_cfg.hsync_data_reg[0];
 907                 config.input_switch_cfg.hsync_data_reg[channel.source_cfg.csi_cfg.csi_port * 2 + 1] =
 908                                 channel.target_cfg.input_switch_channel_cfg.hsync_data_reg[1];
 909                 config.input_switch_cfg.vsync_data_reg |=
 910                                  (channel.target_cfg.input_switch_channel_cfg.vsync_data_reg & 0x7) << (channel.source_cfg.csi_cfg.csi_port * 3);
 911
 912                 // Other targets are just copied and marked as set.
 913                 config.target_isp[channel.source_cfg.csi_cfg.csi_port] = channel.target_cfg.target_isp_cfg;
 914                 config.target_sp[channel.source_cfg.csi_cfg.csi_port] = channel.target_cfg.target_sp_cfg;
 915                 config.target_strm2mem[channel.source_cfg.csi_cfg.csi_port] = channel.target_cfg.target_strm2mem_cfg;
 916                 config.target_isp_flags[channel.source_cfg.csi_cfg.csi_port] |= INPUT_SYSTEM_CFG_FLAG_SET;
 917                 config.target_sp_flags[channel.source_cfg.csi_cfg.csi_port] |= INPUT_SYSTEM_CFG_FLAG_SET;
 918                 config.target_strm2mem_flags[channel.source_cfg.csi_cfg.csi_port] |= INPUT_SYSTEM_CFG_FLAG_SET;
 919
 920                 config.ch_flags[channel.ch_id] = INPUT_SYSTEM_CFG_FLAG_SET;
 921         }
 922         return INPUT_SYSTEM_ERR_NO_ERROR;
 923 }
 924
 925 // Function that partitions input buffer space with determining addresses.
 926 static input_system_error_t input_buffer_configuration(void)
 927 {
 928         uint32_t current_address    = 0;
 929         uint32_t unallocated_memory = IB_CAPACITY_IN_WORDS;
 930
 931         ib_buffer_t     candidate_buffer_acq  = IB_BUFFER_NULL;
 932         uint32_t size_requested;
 933         input_system_config_flags_t     acq_already_specified = INPUT_SYSTEM_CFG_FLAG_RESET;
 934         input_system_csi_port_t port;
 935         for (port = INPUT_SYSTEM_PORT_A; port < N_INPUT_SYSTEM_PORTS; port++) {
 936
 937                 csi_cfg_t source = config.csi_value[port];//.csi_cfg;
 938
 939                 if ( config.csi_flags[port] & INPUT_SYSTEM_CFG_FLAG_SET) {
 940
 941                         // Check and set csi buffer in input buffer.
 942                         switch (source.buffering_mode) {
 943                                 case INPUT_SYSTEM_FIFO_CAPTURE :
 944                                 case INPUT_SYSTEM_XMEM_ACQUIRE :
 945                                         config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_BLOCKED; // Well, not used.
 946                                         break;
 947
 948                                 case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING :
 949                                 case INPUT_SYSTEM_SRAM_BUFFERING :
 950                                 case INPUT_SYSTEM_XMEM_BUFFERING :
 951                                 case INPUT_SYSTEM_XMEM_CAPTURE :
 952                                         size_requested = source.csi_buffer.mem_reg_size * source.csi_buffer.nof_mem_regs;
 953                                         if (source.csi_buffer.mem_reg_size > 0
 954                                                 && source.csi_buffer.nof_mem_regs >0
 955                                                 && size_requested <= unallocated_memory
 956                                                 ) {
 957                                                         config.csi_buffer[port].mem_reg_addr = current_address;
 958                                                         config.csi_buffer[port].mem_reg_size = source.csi_buffer.mem_reg_size;
 959                                                         config.csi_buffer[port].nof_mem_regs = source.csi_buffer.nof_mem_regs;
 960                                                         current_address         += size_requested;
 961                                                         unallocated_memory      -= size_requested;
 962                                                         config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_SET;
 963                                         } else {
 964                                                         config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
 965                                                         return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
 966                                         }
 967                                         break;
 968
 969                                 default :
 970                                         config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
 971                                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
 972                                         break;
 973                         }
 974
 975                         // Check acquisition buffer specified but set it later since it has to be unique.
 976                         switch (source.buffering_mode) {
 977                                 case INPUT_SYSTEM_FIFO_CAPTURE :
 978                                 case INPUT_SYSTEM_SRAM_BUFFERING :
 979                                 case INPUT_SYSTEM_XMEM_CAPTURE :
 980                                         // Nothing to do.
 981                                         break;
 982
 983                                 case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING :
 984                                 case INPUT_SYSTEM_XMEM_BUFFERING :
 985                                 case INPUT_SYSTEM_XMEM_ACQUIRE :
 986                                         if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_RESET) {
 987                                                 size_requested = source.acquisition_buffer.mem_reg_size
 988                                                                                                         * source.acquisition_buffer.nof_mem_regs;
 989                                                 if (source.acquisition_buffer.mem_reg_size > 0
 990                                                         && source.acquisition_buffer.nof_mem_regs >0
 991                                                         && size_requested <= unallocated_memory
 992                                                         ) {
 993                                                                 candidate_buffer_acq = source.acquisition_buffer;
 994                                                                 acq_already_specified = INPUT_SYSTEM_CFG_FLAG_SET;
 995                                                 }
 996                                         } else {
 997                                                 // Check if specified acquisition buffer is the same as specified before.
 998                                                 if (source.acquisition_buffer.mem_reg_size != candidate_buffer_acq.mem_reg_size
 999                                                         || source.acquisition_buffer.nof_mem_regs !=  candidate_buffer_acq.nof_mem_regs
1000                                                    ) {
1001                                                         config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1002                                                         return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1003                                                 }
1004                                         }
1005                                         break;
1006
1007                                 default :
1008                                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1009                                         break;
1010                         }
1011                 } else {
1012                         config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1013                 }
1014         } // end of for ( port )
1015
1016         // Set the acquisition buffer at the end.
1017         size_requested = candidate_buffer_acq.mem_reg_size * candidate_buffer_acq.nof_mem_regs;
1018         if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_SET
1019                 && size_requested <= unallocated_memory) {
1020                 config.acquisition_buffer_unique.mem_reg_addr = current_address;
1021                 config.acquisition_buffer_unique.mem_reg_size = candidate_buffer_acq.mem_reg_size;
1022                 config.acquisition_buffer_unique.nof_mem_regs = candidate_buffer_acq.nof_mem_regs;
1023                 current_address         += size_requested;
1024                 unallocated_memory      -= size_requested;
1025                 config.acquisition_buffer_unique_flags = INPUT_SYSTEM_CFG_FLAG_SET;
1026
1027                 assert(current_address <= IB_CAPACITY_IN_WORDS);
1028         }
1029
1030         return INPUT_SYSTEM_ERR_NO_ERROR;
1031 }
1032
1033 static void capture_unit_configure(
1034         const input_system_ID_t                 ID,
1035         const sub_system_ID_t                   sub_id,
1036         const ib_buffer_t* const                cfg)
1037 {
1038         assert(ID < N_INPUT_SYSTEM_ID);
1039         assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID)); // Commented part is always true.
1040         assert(cfg != NULL);
1041
1042         input_system_sub_system_reg_store(ID,
1043                 sub_id,
1044                 CAPT_START_ADDR_REG_ID,
1045                 cfg->mem_reg_addr);
1046         input_system_sub_system_reg_store(ID,
1047                 sub_id,
1048                 CAPT_MEM_REGION_SIZE_REG_ID,
1049                 cfg->mem_reg_size);
1050         input_system_sub_system_reg_store(ID,
1051                 sub_id,
1052                 CAPT_NUM_MEM_REGIONS_REG_ID,
1053                 cfg->nof_mem_regs);
1054
1055         return;
1056 }
1057
1058
1059 static void acquisition_unit_configure(
1060         const input_system_ID_t                 ID,
1061         const sub_system_ID_t                   sub_id,
1062         const ib_buffer_t* const                cfg)
1063 {
1064         assert(ID < N_INPUT_SYSTEM_ID);
1065         assert(sub_id == ACQUISITION_UNIT0_ID);
1066         assert(cfg != NULL);
1067
1068         input_system_sub_system_reg_store(ID,
1069                 sub_id,
1070                 ACQ_START_ADDR_REG_ID,
1071                 cfg->mem_reg_addr);
1072         input_system_sub_system_reg_store(ID,
1073                 sub_id,
1074                 ACQ_NUM_MEM_REGIONS_REG_ID,
1075                 cfg->nof_mem_regs);
1076         input_system_sub_system_reg_store(ID,
1077                 sub_id,
1078                 ACQ_MEM_REGION_SIZE_REG_ID,
1079                 cfg->mem_reg_size);
1080
1081         return;
1082 }
1083
1084
1085 static void ctrl_unit_configure(
1086         const input_system_ID_t                 ID,
1087         const sub_system_ID_t                   sub_id,
1088         const ctrl_unit_cfg_t* const            cfg)
1089 {
1090         assert(ID < N_INPUT_SYSTEM_ID);
1091         assert(sub_id == CTRL_UNIT0_ID);
1092         assert(cfg != NULL);
1093
1094         input_system_sub_system_reg_store(ID,
1095                 sub_id,
1096                 ISYS_CTRL_CAPT_START_ADDR_A_REG_ID,
1097                 cfg->buffer_mipi[CAPTURE_UNIT0_ID].mem_reg_addr);
1098         input_system_sub_system_reg_store(ID,
1099                 sub_id,
1100                 ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID,
1101                 cfg->buffer_mipi[CAPTURE_UNIT0_ID].mem_reg_size);
1102         input_system_sub_system_reg_store(ID,
1103                 sub_id,
1104                 ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID,
1105                 cfg->buffer_mipi[CAPTURE_UNIT0_ID].nof_mem_regs);
1106
1107         input_system_sub_system_reg_store(ID,
1108                 sub_id,
1109                 ISYS_CTRL_CAPT_START_ADDR_B_REG_ID,
1110                 cfg->buffer_mipi[CAPTURE_UNIT1_ID].mem_reg_addr);
1111         input_system_sub_system_reg_store(ID,
1112                 sub_id,
1113                 ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID,
1114                 cfg->buffer_mipi[CAPTURE_UNIT1_ID].mem_reg_size);
1115         input_system_sub_system_reg_store(ID,
1116                 sub_id,
1117                 ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID,
1118                 cfg->buffer_mipi[CAPTURE_UNIT1_ID].nof_mem_regs);
1119
1120         input_system_sub_system_reg_store(ID,
1121                 sub_id,
1122                 ISYS_CTRL_CAPT_START_ADDR_C_REG_ID,
1123                 cfg->buffer_mipi[CAPTURE_UNIT2_ID].mem_reg_addr);
1124         input_system_sub_system_reg_store(ID,
1125                 sub_id,
1126                 ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID,
1127                 cfg->buffer_mipi[CAPTURE_UNIT2_ID].mem_reg_size);
1128         input_system_sub_system_reg_store(ID,
1129                 sub_id,
1130                 ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID,
1131                 cfg->buffer_mipi[CAPTURE_UNIT2_ID].nof_mem_regs);
1132
1133         input_system_sub_system_reg_store(ID,
1134                 sub_id,
1135                 ISYS_CTRL_ACQ_START_ADDR_REG_ID,
1136                 cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].mem_reg_addr);
1137         input_system_sub_system_reg_store(ID,
1138                 sub_id,
1139                 ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID,
1140                 cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].mem_reg_size);
1141         input_system_sub_system_reg_store(ID,
1142                 sub_id,
1143                 ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID,
1144                 cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].nof_mem_regs);
1145         input_system_sub_system_reg_store(ID,
1146                 sub_id,
1147                 ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID,
1148                 0);
1149         return;
1150 }
1151
1152 static void input_system_network_configure(
1153         const input_system_ID_t                         ID,
1154         const input_system_network_cfg_t * const        cfg)
1155 {
1156         uint32_t sub_id;
1157
1158         assert(ID < N_INPUT_SYSTEM_ID);
1159         assert(cfg != NULL);
1160
1161         // Set all 3 multicasts.
1162         input_system_sub_system_reg_store(ID,
1163                 GPREGS_UNIT0_ID,
1164                 HIVE_ISYS_GPREG_MULTICAST_A_IDX,
1165                 cfg->multicast_cfg[CAPTURE_UNIT0_ID]);
1166         input_system_sub_system_reg_store(ID,
1167                 GPREGS_UNIT0_ID,
1168                 HIVE_ISYS_GPREG_MULTICAST_B_IDX,
1169                 cfg->multicast_cfg[CAPTURE_UNIT1_ID]);
1170         input_system_sub_system_reg_store(ID,
1171                 GPREGS_UNIT0_ID,
1172                 HIVE_ISYS_GPREG_MULTICAST_C_IDX,
1173                 cfg->multicast_cfg[CAPTURE_UNIT2_ID]);
1174
1175         // Set stream mux.
1176         input_system_sub_system_reg_store(ID,
1177                 GPREGS_UNIT0_ID,
1178                 HIVE_ISYS_GPREG_MUX_IDX,
1179                 cfg->mux_cfg);
1180
1181         // Set capture units.
1182         for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) {
1183                 capture_unit_configure(ID,
1184                         sub_id,
1185                         &(cfg->ctrl_unit_cfg[ID].buffer_mipi[sub_id - CAPTURE_UNIT0_ID]));
1186         }
1187
1188         // Set acquisition units.
1189         for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) {
1190                 acquisition_unit_configure(ID,
1191                         sub_id,
1192                         &(cfg->ctrl_unit_cfg[sub_id - ACQUISITION_UNIT0_ID].buffer_acquire[sub_id - ACQUISITION_UNIT0_ID]));
1193         }
1194
1195         // No DMA configuration needed. Ctrl_unit will fully control it.
1196
1197         // Set controller units.
1198         for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) {
1199                 ctrl_unit_configure(ID,
1200                         sub_id,
1201                         &(cfg->ctrl_unit_cfg[sub_id - CTRL_UNIT0_ID]));
1202         }
1203
1204         return;
1205 }
1206
1207 static input_system_error_t configuration_to_registers(void)
1208 {
1209         input_system_network_cfg_t input_system_network_cfg;
1210         int i;
1211
1212         assert(config.source_type_flags & INPUT_SYSTEM_CFG_FLAG_SET);
1213
1214         switch (config.source_type) {
1215                 case INPUT_SYSTEM_SOURCE_SENSOR :
1216
1217                         // Determine stream multicasts setting based on the mode of csi_cfg_t.
1218                         // AM: This should be moved towards earlier function call, e.g. in
1219                         // the commit function.
1220                         for (i = MIPI_PORT0_ID; i < N_MIPI_PORT_ID; i++) {
1221                                 if (config.csi_flags[i] & INPUT_SYSTEM_CFG_FLAG_SET) {
1222
1223                                         switch (config.csi_value[i].buffering_mode) {
1224
1225                                                 case INPUT_SYSTEM_FIFO_CAPTURE:
1226                                                         config.multicast[i] = INPUT_SYSTEM_CSI_BACKEND;
1227                                                         break;
1228
1229                                                 case INPUT_SYSTEM_XMEM_CAPTURE:
1230                                                 case INPUT_SYSTEM_SRAM_BUFFERING:
1231                                                 case INPUT_SYSTEM_XMEM_BUFFERING:
1232                                                         config.multicast[i] = INPUT_SYSTEM_INPUT_BUFFER;
1233                                                         break;
1234
1235                                                 case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING:
1236                                                         config.multicast[i] = INPUT_SYSTEM_MULTICAST;
1237                                                         break;
1238
1239                                                 case INPUT_SYSTEM_XMEM_ACQUIRE:
1240                                                         config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL;
1241                                                         break;
1242
1243                                                 default:
1244                                                         config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL;
1245                                                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1246                                                         //break;
1247                                         }
1248                                 } else {
1249                                         config.multicast[i]= INPUT_SYSTEM_DISCARD_ALL;
1250                                 }
1251
1252                                 input_system_network_cfg.multicast_cfg[i] = config.multicast[i];
1253
1254                         } // for
1255
1256                         input_system_network_cfg.mux_cfg = config.multiplexer;
1257
1258                         input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT0_ID] = config.csi_buffer[MIPI_PORT0_ID];
1259                         input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT1_ID] = config.csi_buffer[MIPI_PORT1_ID];
1260                         input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT2_ID] = config.csi_buffer[MIPI_PORT2_ID];
1261                         input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID] =
1262                                         config.acquisition_buffer_unique;
1263
1264                         // First set input network around CSI receiver.
1265                         input_system_network_configure(INPUT_SYSTEM0_ID, &input_system_network_cfg);
1266
1267                         // Set the CSI receiver.
1268                         //...
1269                         break;
1270
1271                 case INPUT_SYSTEM_SOURCE_TPG :
1272
1273                         break;
1274
1275                 case INPUT_SYSTEM_SOURCE_PRBS :
1276
1277                         break;
1278
1279                 case INPUT_SYSTEM_SOURCE_FIFO :
1280                         break;
1281
1282                 default :
1283                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1284                         break;
1285
1286         } // end of switch (source_type)
1287
1288         // Set input selector.
1289         input_selector_cfg_for_sensor(INPUT_SYSTEM0_ID);
1290
1291         // Set input switch.
1292         input_switch_cfg(INPUT_SYSTEM0_ID, &config.input_switch_cfg);
1293
1294         // Set input formatters.
1295         // AM: IF are set dynamically.
1296         return INPUT_SYSTEM_ERR_NO_ERROR;
1297 }
1298
1299
1300 // Function that applies the whole configuration.
1301 input_system_error_t input_system_configuration_commit(void)
1302 {
1303         // The last configuration step is to configure the input buffer.
1304         input_system_error_t error = input_buffer_configuration();
1305         if (error != INPUT_SYSTEM_ERR_NO_ERROR) {
1306                 return error;
1307         }
1308
1309         // Translate the whole configuration into registers.
1310         error = configuration_to_registers();
1311         if (error != INPUT_SYSTEM_ERR_NO_ERROR) {
1312                 return error;
1313         }
1314
1315         // Translate the whole configuration into ctrl commands etc.
1316
1317         return INPUT_SYSTEM_ERR_NO_ERROR;
1318 }
1319
1320
1321
1322 // FIFO
1323
1324 input_system_error_t    input_system_csi_fifo_channel_cfg(
1325                 uint32_t                ch_id,
1326                 input_system_csi_port_t port,
1327                 backend_channel_cfg_t   backend_ch,
1328                 target_cfg2400_t        target
1329 )
1330 {
1331         channel_cfg_t channel;
1332
1333         channel.ch_id   = ch_id;
1334         channel.backend_ch      = backend_ch;
1335         channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
1336         //channel.source
1337         channel.source_cfg.csi_cfg.csi_port                     = port;
1338         channel.source_cfg.csi_cfg.buffering_mode       = INPUT_SYSTEM_FIFO_CAPTURE;
1339         channel.source_cfg.csi_cfg.csi_buffer                   = IB_BUFFER_NULL;
1340         channel.source_cfg.csi_cfg.acquisition_buffer   = IB_BUFFER_NULL;
1341         channel.source_cfg.csi_cfg.nof_xmem_buffers     = 0;
1342
1343         channel.target_cfg      = target;
1344         return input_system_configure_channel(channel);
1345 }
1346
1347
1348 input_system_error_t    input_system_csi_fifo_channel_with_counting_cfg(
1349                 uint32_t                                ch_id,
1350                 uint32_t                                nof_frames,
1351                 input_system_csi_port_t                 port,
1352                 backend_channel_cfg_t                   backend_ch,
1353                 uint32_t                                csi_mem_reg_size,
1354                 uint32_t                                csi_nof_mem_regs,
1355                 target_cfg2400_t                        target
1356 )
1357 {
1358         channel_cfg_t channel;
1359
1360         channel.ch_id   = ch_id;
1361         channel.backend_ch      = backend_ch;
1362         channel.source_type             = INPUT_SYSTEM_SOURCE_SENSOR;
1363         //channel.source
1364         channel.source_cfg.csi_cfg.csi_port                     = port;
1365         channel.source_cfg.csi_cfg.buffering_mode       = INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING;
1366         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size              = csi_mem_reg_size;
1367         channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs              = csi_nof_mem_regs;
1368         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr              = 0;
1369         channel.source_cfg.csi_cfg.acquisition_buffer                   = IB_BUFFER_NULL;
1370         channel.source_cfg.csi_cfg.nof_xmem_buffers     = nof_frames;
1371
1372         channel.target_cfg      = target;
1373         return input_system_configure_channel(channel);
1374 }
1375
1376
1377 // SRAM
1378
1379 input_system_error_t    input_system_csi_sram_channel_cfg(
1380                 uint32_t                                ch_id,
1381                 input_system_csi_port_t                 port,
1382                 backend_channel_cfg_t                   backend_ch,
1383                 uint32_t                                csi_mem_reg_size,
1384                 uint32_t                                csi_nof_mem_regs,
1385         //      uint32_t                                acq_mem_reg_size,
1386         //      uint32_t                                acq_nof_mem_regs,
1387                 target_cfg2400_t                        target
1388 )
1389 {
1390         channel_cfg_t channel;
1391
1392         channel.ch_id   = ch_id;
1393         channel.backend_ch      = backend_ch;
1394         channel.source_type             = INPUT_SYSTEM_SOURCE_SENSOR;
1395         //channel.source
1396         channel.source_cfg.csi_cfg.csi_port                     = port;
1397         channel.source_cfg.csi_cfg.buffering_mode       = INPUT_SYSTEM_SRAM_BUFFERING;
1398         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size              = csi_mem_reg_size;
1399         channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs              = csi_nof_mem_regs;
1400         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr              = 0;
1401         channel.source_cfg.csi_cfg.acquisition_buffer                   = IB_BUFFER_NULL;
1402         channel.source_cfg.csi_cfg.nof_xmem_buffers     = 0;
1403
1404         channel.target_cfg      = target;
1405         return input_system_configure_channel(channel);
1406 }
1407
1408
1409 //XMEM
1410
1411 // Collects all parameters and puts them in channel_cfg_t.
1412 input_system_error_t    input_system_csi_xmem_channel_cfg(
1413                 uint32_t                                ch_id,
1414                 input_system_csi_port_t                 port,
1415                 backend_channel_cfg_t                   backend_ch,
1416                 uint32_t                                csi_mem_reg_size,
1417                 uint32_t                                csi_nof_mem_regs,
1418                 uint32_t                                acq_mem_reg_size,
1419                 uint32_t                                acq_nof_mem_regs,
1420                 target_cfg2400_t                        target,
1421                 uint32_t                                nof_xmem_buffers
1422 )
1423 {
1424         channel_cfg_t channel;
1425
1426         channel.ch_id   = ch_id;
1427         channel.backend_ch      = backend_ch;
1428         channel.source_type             = INPUT_SYSTEM_SOURCE_SENSOR;
1429         //channel.source
1430         channel.source_cfg.csi_cfg.csi_port                     = port;
1431         channel.source_cfg.csi_cfg.buffering_mode       = INPUT_SYSTEM_XMEM_BUFFERING;
1432         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size              = csi_mem_reg_size;
1433         channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs              = csi_nof_mem_regs;
1434         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr              = 0;
1435         channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size      = acq_mem_reg_size;
1436         channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs      = acq_nof_mem_regs;
1437         channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr      = 0;
1438         channel.source_cfg.csi_cfg.nof_xmem_buffers     = nof_xmem_buffers;
1439
1440         channel.target_cfg      = target;
1441         return input_system_configure_channel(channel);
1442 }
1443
1444
1445
1446
1447 input_system_error_t    input_system_csi_xmem_acquire_only_channel_cfg(
1448                 uint32_t                                ch_id,
1449                 uint32_t                                nof_frames,
1450                 input_system_csi_port_t                 port,
1451                 backend_channel_cfg_t                   backend_ch,
1452                 uint32_t                                acq_mem_reg_size,
1453                 uint32_t                                acq_nof_mem_regs,
1454                 target_cfg2400_t                        target)
1455 {
1456         channel_cfg_t channel;
1457
1458         channel.ch_id   = ch_id;
1459         channel.backend_ch      = backend_ch;
1460         channel.source_type             = INPUT_SYSTEM_SOURCE_SENSOR;
1461         //channel.source
1462         channel.source_cfg.csi_cfg.csi_port                     = port;
1463         channel.source_cfg.csi_cfg.buffering_mode       = INPUT_SYSTEM_XMEM_ACQUIRE;
1464         channel.source_cfg.csi_cfg.csi_buffer           = IB_BUFFER_NULL;
1465         channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size      = acq_mem_reg_size;
1466         channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs      = acq_nof_mem_regs;
1467         channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr      = 0;
1468         channel.source_cfg.csi_cfg.nof_xmem_buffers     = nof_frames;
1469
1470         channel.target_cfg      = target;
1471         return input_system_configure_channel(channel);
1472 }
1473
1474
1475 input_system_error_t    input_system_csi_xmem_capture_only_channel_cfg(
1476                 uint32_t                                ch_id,
1477                 uint32_t                                nof_frames,
1478                 input_system_csi_port_t                 port,
1479                 uint32_t                                csi_mem_reg_size,
1480                 uint32_t                                csi_nof_mem_regs,
1481                 uint32_t                                acq_mem_reg_size,
1482                 uint32_t                                acq_nof_mem_regs,
1483                 target_cfg2400_t                        target)
1484 {
1485         channel_cfg_t channel;
1486
1487         channel.ch_id   = ch_id;
1488         //channel.backend_ch    = backend_ch;
1489         channel.source_type             = INPUT_SYSTEM_SOURCE_SENSOR;
1490         //channel.source
1491         channel.source_cfg.csi_cfg.csi_port                     = port;
1492         //channel.source_cfg.csi_cfg.backend_ch                 = backend_ch;
1493         channel.source_cfg.csi_cfg.buffering_mode       = INPUT_SYSTEM_XMEM_CAPTURE;
1494         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size              = csi_mem_reg_size;
1495         channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs              = csi_nof_mem_regs;
1496         channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr              = 0;
1497         channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size      = acq_mem_reg_size;
1498         channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs      = acq_nof_mem_regs;
1499         channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr      = 0;
1500         channel.source_cfg.csi_cfg.nof_xmem_buffers     = nof_frames;
1501
1502         channel.target_cfg      = target;
1503         return input_system_configure_channel(channel);
1504 }
1505
1506
1507
1508 // Non - CSI
1509
1510 input_system_error_t    input_system_prbs_channel_cfg(
1511                 uint32_t                ch_id,
1512                 uint32_t                nof_frames,//not used yet
1513                 uint32_t                seed,
1514                 uint32_t                sync_gen_width,
1515                 uint32_t                sync_gen_height,
1516                 uint32_t                sync_gen_hblank_cycles,
1517                 uint32_t                sync_gen_vblank_cycles,
1518                 target_cfg2400_t        target
1519 )
1520 {
1521         channel_cfg_t channel;
1522
1523         (void)nof_frames;
1524
1525         channel.ch_id   = ch_id;
1526         channel.source_type= INPUT_SYSTEM_SOURCE_PRBS;
1527
1528         channel.source_cfg.prbs_cfg.seed = seed;
1529         channel.source_cfg.prbs_cfg.sync_gen_cfg.width          = sync_gen_width;
1530         channel.source_cfg.prbs_cfg.sync_gen_cfg.height         = sync_gen_height;
1531         channel.source_cfg.prbs_cfg.sync_gen_cfg.hblank_cycles  = sync_gen_hblank_cycles;
1532         channel.source_cfg.prbs_cfg.sync_gen_cfg.vblank_cycles  = sync_gen_vblank_cycles;
1533
1534         channel.target_cfg      = target;
1535
1536         return input_system_configure_channel(channel);
1537 }
1538
1539
1540
1541 input_system_error_t    input_system_tpg_channel_cfg(
1542                 uint32_t                ch_id,
1543                 uint32_t                nof_frames,//not used yet
1544                 uint32_t                x_mask,
1545                 uint32_t                y_mask,
1546                 uint32_t                x_delta,
1547                 uint32_t                y_delta,
1548                 uint32_t                xy_mask,
1549                 uint32_t                sync_gen_width,
1550                 uint32_t                sync_gen_height,
1551                 uint32_t                sync_gen_hblank_cycles,
1552                 uint32_t                sync_gen_vblank_cycles,
1553                 target_cfg2400_t        target
1554 )
1555 {
1556         channel_cfg_t channel;
1557
1558         (void)nof_frames;
1559
1560         channel.ch_id   = ch_id;
1561         channel.source_type             = INPUT_SYSTEM_SOURCE_TPG;
1562
1563         channel.source_cfg.tpg_cfg.x_mask       = x_mask;
1564         channel.source_cfg.tpg_cfg.y_mask       = y_mask;
1565         channel.source_cfg.tpg_cfg.x_delta      = x_delta;
1566         channel.source_cfg.tpg_cfg.y_delta      = y_delta;
1567         channel.source_cfg.tpg_cfg.xy_mask      = xy_mask;
1568         channel.source_cfg.tpg_cfg.sync_gen_cfg.width           = sync_gen_width;
1569         channel.source_cfg.tpg_cfg.sync_gen_cfg.height          = sync_gen_height;
1570         channel.source_cfg.tpg_cfg.sync_gen_cfg.hblank_cycles   = sync_gen_hblank_cycles;
1571         channel.source_cfg.tpg_cfg.sync_gen_cfg.vblank_cycles   = sync_gen_vblank_cycles;
1572
1573         channel.target_cfg      = target;
1574         return input_system_configure_channel(channel);
1575 }
1576
1577 // MW: Don't use system specific names, (even in system specific files) "cfg2400" -> cfg
1578 input_system_error_t    input_system_gpfifo_channel_cfg(
1579                 uint32_t                ch_id,
1580                 uint32_t                nof_frames, //not used yet
1581                 target_cfg2400_t        target)
1582 {
1583         channel_cfg_t channel;
1584
1585         (void)nof_frames;
1586
1587         channel.ch_id   = ch_id;
1588         channel.source_type     = INPUT_SYSTEM_SOURCE_FIFO;
1589
1590         channel.target_cfg      = target;
1591         return input_system_configure_channel(channel);
1592 }
1593
1594 ///////////////////////////////////////////////////////////////////////////
1595 //
1596 // Private specialized functions for channel setting.
1597 //
1598 ///////////////////////////////////////////////////////////////////////////
1599
1600 // Fills the parameters to config.csi_value[port]
1601 static input_system_error_t input_system_configure_channel_sensor(
1602         const channel_cfg_t channel)
1603 {
1604         const uint32_t port = channel.source_cfg.csi_cfg.csi_port;
1605         input_system_error_t status = INPUT_SYSTEM_ERR_NO_ERROR;
1606
1607         input_system_multiplex_t mux;
1608
1609         if (port >= N_INPUT_SYSTEM_PORTS)
1610                 return INPUT_SYSTEM_ERR_GENERIC;
1611
1612         //check if port > N_INPUT_SYSTEM_MULTIPLEX
1613
1614         status = set_source_type(&(config.source_type), channel.source_type, &config.source_type_flags);
1615         if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
1616
1617         // Check for conflicts on source (implicitly on multicast, capture unit and input buffer).
1618
1619         status = set_csi_cfg(&(config.csi_value[port]), &channel.source_cfg.csi_cfg, &(config.csi_flags[port]));
1620         if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
1621
1622
1623         switch (channel.source_cfg.csi_cfg.buffering_mode){
1624                 case INPUT_SYSTEM_FIFO_CAPTURE:
1625
1626                         // Check for conflicts on mux.
1627                         mux = INPUT_SYSTEM_MIPI_PORT0 + port;
1628                         status = input_system_multiplexer_cfg(&config.multiplexer, mux, &config.multiplexer_flags);
1629                         if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
1630                         config.multicast[port] = INPUT_SYSTEM_CSI_BACKEND;
1631
1632                         // Shared resource, so it should be blocked.
1633                         //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1634                         //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1635                         //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1636
1637                         break;
1638                 case INPUT_SYSTEM_SRAM_BUFFERING :
1639
1640                         // Check for conflicts on mux.
1641                         mux = INPUT_SYSTEM_ACQUISITION_UNIT;
1642                         status = input_system_multiplexer_cfg(&config.multiplexer, mux, &config.multiplexer_flags);
1643                         if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
1644                         config.multicast[port] = INPUT_SYSTEM_INPUT_BUFFER;
1645
1646                         // Shared resource, so it should be blocked.
1647                         //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1648                         //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1649                         //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1650
1651                         break;
1652                 case INPUT_SYSTEM_XMEM_BUFFERING :
1653
1654                         // Check for conflicts on mux.
1655                         mux = INPUT_SYSTEM_ACQUISITION_UNIT;
1656                         status = input_system_multiplexer_cfg(&config.multiplexer, mux, &config.multiplexer_flags);
1657                         if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
1658                         config.multicast[port] = INPUT_SYSTEM_INPUT_BUFFER;
1659
1660                         // Shared resource, so it should be blocked.
1661                         //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1662                         //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1663                         //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
1664
1665                         break;
1666                 case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING :
1667                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1668                         break;
1669                 case INPUT_SYSTEM_XMEM_CAPTURE :
1670                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1671                         break;
1672                 case INPUT_SYSTEM_XMEM_ACQUIRE :
1673                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1674                         break;
1675                 default :
1676                         return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1677                         break;
1678         }
1679         return INPUT_SYSTEM_ERR_NO_ERROR;
1680 }
1681
1682 // Test flags and set structure.
1683 static input_system_error_t set_source_type(
1684                 input_system_source_t * const                   lhs,
1685                 const input_system_source_t                     rhs,
1686                 input_system_config_flags_t * const             flags)
1687 {
1688         // MW: Not enough asserts
1689         assert(lhs != NULL);
1690         assert(flags != NULL);
1691
1692         if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) {
1693                 *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1694                 return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1695         }
1696
1697         if ((*flags) & INPUT_SYSTEM_CFG_FLAG_SET) {
1698                 // Check for consistency with already set value.
1699                 if ((*lhs) == (rhs)) {
1700                         return INPUT_SYSTEM_ERR_NO_ERROR;
1701                 }
1702                 else {
1703                         *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1704                         return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1705                 }
1706         }
1707         // Check the value (individually).
1708         if (rhs >= N_INPUT_SYSTEM_SOURCE) {
1709                 *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1710                 return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1711         }
1712         // Set the value.
1713         *lhs = rhs;
1714
1715         *flags |= INPUT_SYSTEM_CFG_FLAG_SET;
1716         return INPUT_SYSTEM_ERR_NO_ERROR;
1717 }
1718
1719
1720 // Test flags and set structure.
1721 static input_system_error_t set_csi_cfg(
1722                 csi_cfg_t* const                        lhs,
1723                 const csi_cfg_t* const                  rhs,
1724                 input_system_config_flags_t * const     flags)
1725 {
1726         uint32_t memory_required;
1727         uint32_t acq_memory_required;
1728
1729         assert(lhs != NULL);
1730         assert(flags != NULL);
1731
1732         if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) {
1733                 *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1734                 return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1735         }
1736
1737         if (*flags & INPUT_SYSTEM_CFG_FLAG_SET) {
1738                 // check for consistency with already set value.
1739                 if (/*lhs->backend_ch == rhs.backend_ch
1740                         &&*/ lhs->buffering_mode == rhs->buffering_mode
1741                         && lhs->csi_buffer.mem_reg_size == rhs->csi_buffer.mem_reg_size
1742                         && lhs->csi_buffer.nof_mem_regs  == rhs->csi_buffer.nof_mem_regs
1743                         && lhs->acquisition_buffer.mem_reg_size == rhs->acquisition_buffer.mem_reg_size
1744                         && lhs->acquisition_buffer.nof_mem_regs  == rhs->acquisition_buffer.nof_mem_regs
1745                         && lhs->nof_xmem_buffers  == rhs->nof_xmem_buffers
1746                         ) {
1747                         return INPUT_SYSTEM_ERR_NO_ERROR;
1748                 }
1749                 else {
1750                         *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1751                         return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1752                 }
1753         }
1754         // Check the value (individually).
1755         // no check for backend_ch
1756         // no check for nof_xmem_buffers
1757         memory_required = rhs->csi_buffer.mem_reg_size * rhs->csi_buffer.nof_mem_regs;
1758         acq_memory_required = rhs->acquisition_buffer.mem_reg_size * rhs->acquisition_buffer.nof_mem_regs;
1759         if (rhs->buffering_mode >= N_INPUT_SYSTEM_BUFFERING_MODE
1760                 ||
1761         // Check if required memory is available in input buffer (SRAM).
1762                 (memory_required + acq_memory_required )> config.unallocated_ib_mem_words
1763
1764                 ) {
1765                 *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1766                 return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1767         }
1768         // Set the value.
1769         //lhs[port]->backend_ch                 = rhs.backend_ch;
1770         lhs->buffering_mode     = rhs->buffering_mode;
1771         lhs->nof_xmem_buffers = rhs->nof_xmem_buffers;
1772
1773         lhs->csi_buffer.mem_reg_size = rhs->csi_buffer.mem_reg_size;
1774         lhs->csi_buffer.nof_mem_regs  = rhs->csi_buffer.nof_mem_regs;
1775         lhs->acquisition_buffer.mem_reg_size = rhs->acquisition_buffer.mem_reg_size;
1776         lhs->acquisition_buffer.nof_mem_regs  = rhs->acquisition_buffer.nof_mem_regs;
1777     // ALX: NB: Here we just set buffer parameters, but still not allocate it
1778         // (no addresses determined). That will be done during commit.
1779
1780         //  FIXIT:      acq_memory_required is not deducted, since it can be allocated multiple times.
1781         config.unallocated_ib_mem_words -= memory_required;
1782 //assert(config.unallocated_ib_mem_words >=0);
1783         *flags |= INPUT_SYSTEM_CFG_FLAG_SET;
1784         return INPUT_SYSTEM_ERR_NO_ERROR;
1785 }
1786
1787
1788 // Test flags and set structure.
1789 static input_system_error_t input_system_multiplexer_cfg(
1790         input_system_multiplex_t* const         lhs,
1791         const input_system_multiplex_t          rhs,
1792         input_system_config_flags_t* const      flags)
1793 {
1794         assert(lhs != NULL);
1795         assert(flags != NULL);
1796
1797         if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) {
1798                 *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1799                 return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1800         }
1801
1802         if ((*flags) & INPUT_SYSTEM_CFG_FLAG_SET) {
1803                 // Check for consistency with already set value.
1804                 if ((*lhs) == (rhs)) {
1805                         return INPUT_SYSTEM_ERR_NO_ERROR;
1806                 }
1807                 else {
1808                         *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1809                         return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
1810                 }
1811         }
1812         // Check the value (individually).
1813         if (rhs >= N_INPUT_SYSTEM_MULTIPLEX) {
1814                 *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
1815                 return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
1816         }
1817         // Set the value.
1818         *lhs = rhs;
1819
1820         *flags |= INPUT_SYSTEM_CFG_FLAG_SET;
1821         return INPUT_SYSTEM_ERR_NO_ERROR;
1822 }
1823 #endif