drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_local.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2010-2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef __DMA_LOCAL_H_INCLUDED__
  16 #define __DMA_LOCAL_H_INCLUDED__
  17
  18 #include <type_support.h>
  19 #include "dma_global.h"
  20
  21 #include <hrt/defs.h>                           /* HRTCAT() */
  22 #include <hrt/bits.h>                           /* _hrt_get_bits() */
  23 #include <hive_isp_css_defs.h>          /* HIVE_DMA_NUM_CHANNELS */
  24 #include <dma_v2_defs.h>
  25
  26 #define _DMA_FSM_GROUP_CMD_IDX                                          _DMA_V2_FSM_GROUP_CMD_IDX
  27 #define _DMA_FSM_GROUP_ADDR_A_IDX                                       _DMA_V2_FSM_GROUP_ADDR_SRC_IDX
  28 #define _DMA_FSM_GROUP_ADDR_B_IDX                                       _DMA_V2_FSM_GROUP_ADDR_DEST_IDX
  29
  30 #define _DMA_FSM_GROUP_CMD_CTRL_IDX                                     _DMA_V2_FSM_GROUP_CMD_CTRL_IDX
  31
  32 #define _DMA_FSM_GROUP_FSM_CTRL_IDX                                     _DMA_V2_FSM_GROUP_FSM_CTRL_IDX
  33 #define _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX                       _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX
  34 #define _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX                     _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX
  35 #define _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX            _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX
  36 #define _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX          _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX
  37 #define _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX                      _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX
  38 #define _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX                      _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX
  39 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX        _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX
  40 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX         _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX
  41 #define _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX                     _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX
  42 #define _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX           _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX
  43 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX         _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX
  44 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX          _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX
  45 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX          _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX
  46 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX       _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX
  47 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX        _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX
  48 #define _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX            _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX
  49
  50 #define _DMA_FSM_GROUP_FSM_PACK_IDX                                     _DMA_V2_FSM_GROUP_FSM_PACK_IDX
  51 #define _DMA_FSM_GROUP_FSM_PACK_STATE_IDX                       _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX
  52 #define _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX                      _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX
  53 #define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX          _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX
  54 #define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX           _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX
  55
  56 #define _DMA_FSM_GROUP_FSM_REQ_IDX                                      _DMA_V2_FSM_GROUP_FSM_REQ_IDX
  57 #define _DMA_FSM_GROUP_FSM_REQ_STATE_IDX                        _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX
  58 #define _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX                       _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX
  59 #define _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX                       _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX
  60
  61 #define _DMA_FSM_GROUP_FSM_WR_IDX                                       _DMA_V2_FSM_GROUP_FSM_WR_IDX
  62 #define _DMA_FSM_GROUP_FSM_WR_STATE_IDX                         _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX
  63 #define _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX                        _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX
  64 #define _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX                        _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX
  65
  66 #define _DMA_DEV_INTERF_MAX_BURST_IDX                   _DMA_V2_DEV_INTERF_MAX_BURST_IDX
  67
  68 /*
  69  * Macro's to compute the DMA parameter register indices
  70  */
  71 #define DMA_SEL_COMP(comp)     (((comp)  & _hrt_ones(_DMA_V2_ADDR_SEL_COMP_BITS))            << _DMA_V2_ADDR_SEL_COMP_IDX)
  72 #define DMA_SEL_CH(ch)         (((ch)    & _hrt_ones(_DMA_V2_ADDR_SEL_CH_REG_BITS))          << _DMA_V2_ADDR_SEL_CH_REG_IDX)
  73 #define DMA_SEL_PARAM(param)   (((param) & _hrt_ones(_DMA_V2_ADDR_SEL_PARAM_BITS))           << _DMA_V2_ADDR_SEL_PARAM_IDX)
  74 /* CG = Connection Group */
  75 #define DMA_SEL_CG_INFO(info)  (((info)  & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX)
  76 #define DMA_SEL_CG_COMP(comp)  (((comp)  & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_BITS))      << _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
  77 #define DMA_SEL_DEV_INFO(info) (((info)  & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX)
  78 #define DMA_SEL_DEV_ID(dev)    (((dev)   & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS))  << _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX)
  79
  80 #define DMA_COMMAND_FSM_REG_IDX                                 (DMA_SEL_COMP(_DMA_V2_SEL_FSM_CMD) >> 2)
  81 #define DMA_CHANNEL_PARAM_REG_IDX(ch, param)    ((DMA_SEL_COMP(_DMA_V2_SEL_CH_REG) | DMA_SEL_CH(ch) | DMA_SEL_PARAM(param)) >> 2)
  82 #define DMA_CG_INFO_REG_IDX(info_id, comp_id)   ((DMA_SEL_COMP(_DMA_V2_SEL_CONN_GROUP) | DMA_SEL_CG_INFO(info_id) | DMA_SEL_CG_COMP(comp_id)) >> 2)
  83 #define DMA_DEV_INFO_REG_IDX(info_id, dev_id)   ((DMA_SEL_COMP(_DMA_V2_SEL_DEV_INTERF) | DMA_SEL_DEV_INFO(info_id) | DMA_SEL_DEV_ID(dev_id)) >> 2)
  84 #define DMA_RST_REG_IDX                                                 (DMA_SEL_COMP(_DMA_V2_SEL_RESET) >> 2)
  85
  86 #define DMA_GET_CONNECTION(val)    _hrt_get_bits(val, _DMA_V2_CONNECTION_IDX,    _DMA_V2_CONNECTION_BITS)
  87 #define DMA_GET_EXTENSION(val)     _hrt_get_bits(val, _DMA_V2_EXTENSION_IDX,     _DMA_V2_EXTENSION_BITS)
  88 #define DMA_GET_ELEMENTS(val)      _hrt_get_bits(val, _DMA_V2_ELEMENTS_IDX,      _DMA_V2_ELEMENTS_BITS)
  89 #define DMA_GET_CROPPING(val)      _hrt_get_bits(val, _DMA_V2_LEFT_CROPPING_IDX, _DMA_V2_LEFT_CROPPING_BITS)
  90
  91 typedef enum {
  92         DMA_CTRL_STATE_IDLE,
  93         DMA_CTRL_STATE_REQ_RCV,
  94         DMA_CTRL_STATE_RCV,
  95         DMA_CTRL_STATE_RCV_REQ,
  96         DMA_CTRL_STATE_INIT,
  97         N_DMA_CTRL_STATES
  98 } dma_ctrl_states_t;
  99
 100 typedef enum {
 101         DMA_COMMAND_READ,
 102         DMA_COMMAND_WRITE,
 103         DMA_COMMAND_SET_CHANNEL,
 104         DMA_COMMAND_SET_PARAM,
 105         DMA_COMMAND_READ_SPECIFIC,
 106         DMA_COMMAND_WRITE_SPECIFIC,
 107         DMA_COMMAND_INIT,
 108         DMA_COMMAND_INIT_SPECIFIC,
 109         DMA_COMMAND_RST,
 110         N_DMA_COMMANDS
 111 } dma_commands_t;
 112
 113 typedef enum {
 114         DMA_RW_STATE_IDLE,
 115         DMA_RW_STATE_REQ,
 116         DMA_RW_STATE_NEXT_LINE,
 117         DMA_RW_STATE_UNLOCK_CHANNEL,
 118         N_DMA_RW_STATES
 119 } dma_rw_states_t;
 120
 121 typedef enum {
 122         DMA_FIFO_STATE_WILL_BE_FULL,
 123         DMA_FIFO_STATE_FULL,
 124         DMA_FIFO_STATE_EMPTY,
 125         N_DMA_FIFO_STATES
 126 } dma_fifo_states_t;
 127
 128 /* typedef struct dma_state_s                   dma_state_t; */
 129 typedef struct dma_channel_state_s      dma_channel_state_t;
 130 typedef struct dma_port_state_s         dma_port_state_t;
 131
 132 struct dma_port_state_s {
 133         bool                       req_cs;
 134         bool                       req_we_n;
 135         bool                       req_run;
 136         bool                       req_ack;
 137         bool                       send_cs;
 138         bool                       send_we_n;
 139         bool                       send_run;
 140         bool                       send_ack;
 141         dma_fifo_states_t          fifo_state;
 142         int                        fifo_counter;
 143 };
 144
 145 struct dma_channel_state_s {
 146         int                        connection;
 147         bool                       sign_extend;
 148         int                        height;
 149         int                        stride_a;
 150         int                        elems_a;
 151         int                        cropping_a;
 152         int                        width_a;
 153         int                        stride_b;
 154         int                        elems_b;
 155         int                        cropping_b;
 156         int                        width_b;
 157 };
 158
 159 struct dma_state_s {
 160         bool                       fsm_command_idle;
 161         bool                       fsm_command_run;
 162         bool                       fsm_command_stalling;
 163         bool                       fsm_command_error;
 164         dma_commands_t             last_command;
 165         int                        last_command_channel;
 166         int                        last_command_param;
 167         dma_commands_t             current_command;
 168         int                        current_addr_a;
 169         int                        current_addr_b;
 170         bool                       fsm_ctrl_idle;
 171         bool                       fsm_ctrl_run;
 172         bool                       fsm_ctrl_stalling;
 173         bool                       fsm_ctrl_error;
 174         dma_ctrl_states_t          fsm_ctrl_state;
 175         int                        fsm_ctrl_source_dev;
 176         int                        fsm_ctrl_source_addr;
 177         int                        fsm_ctrl_source_stride;
 178         int                        fsm_ctrl_source_width;
 179         int                        fsm_ctrl_source_height;
 180         int                        fsm_ctrl_pack_source_dev;
 181         int                        fsm_ctrl_pack_dest_dev;
 182         int                        fsm_ctrl_dest_addr;
 183         int                        fsm_ctrl_dest_stride;
 184         int                        fsm_ctrl_pack_source_width;
 185         int                        fsm_ctrl_pack_dest_height;
 186         int                        fsm_ctrl_pack_dest_width;
 187         int                        fsm_ctrl_pack_source_elems;
 188         int                        fsm_ctrl_pack_dest_elems;
 189         int                        fsm_ctrl_pack_extension;
 190         int                                                pack_idle;
 191         int                            pack_run;
 192         int                                pack_stalling;
 193         int                                pack_error;
 194         int                        pack_cnt_height;
 195         int                        pack_src_cnt_width;
 196         int                        pack_dest_cnt_width;
 197         dma_rw_states_t            read_state;
 198         int                        read_cnt_height;
 199         int                        read_cnt_width;
 200         dma_rw_states_t            write_state;
 201         int                        write_height;
 202         int                        write_width;
 203         dma_port_state_t           port_states[HIVE_ISP_NUM_DMA_CONNS];
 204         dma_channel_state_t        channel_states[HIVE_DMA_NUM_CHANNELS];
 205 };
 206
 207 #endif /* __DMA_LOCAL_H_INCLUDED__ */