2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #ifndef _hrt_dummy_use_blob_sp
20 #define _hrt_dummy_use_blob_sp()
23 #define _hrt_cell_load_program_sp(proc) _hrt_cell_load_program_embedded(proc, sp)
26 /* function input_system_acquisition_stop: ADE */
28 /* function input_system_acquisition_stop: AD8 */
32 /* function longjmp: 684E */
34 /* function longjmp: 69C1 */
37 #ifndef HIVE_MULTIPLE_PROGRAMS
38 #ifndef HIVE_MEM_HIVE_IF_SRST_MASK
39 #define HIVE_MEM_HIVE_IF_SRST_MASK scalar_processor_2400_dmem
40 #define HIVE_ADDR_HIVE_IF_SRST_MASK 0x1C8
41 #define HIVE_SIZE_HIVE_IF_SRST_MASK 16
45 #define HIVE_MEM_sp_HIVE_IF_SRST_MASK scalar_processor_2400_dmem
46 #define HIVE_ADDR_sp_HIVE_IF_SRST_MASK 0x1C8
47 #define HIVE_SIZE_sp_HIVE_IF_SRST_MASK 16
50 /* function tmpmem_init_dmem: 6599 */
52 /* function tmpmem_init_dmem: 66D4 */
56 /* function ia_css_isys_sp_token_map_receive_ack: 5EDD */
58 /* function ia_css_isys_sp_token_map_receive_ack: 6018 */
62 /* function ia_css_dmaproxy_sp_set_addr_B: 3345 */
64 /* function ia_css_dmaproxy_sp_set_addr_B: 3539 */
66 /* function ia_css_pipe_data_init_tagger_resources: A4F */
69 /* function debug_buffer_set_ddr_addr: DD */
72 /* function receiver_port_reg_load: AC2 */
74 /* function receiver_port_reg_load: ABC */
77 #ifndef HIVE_MULTIPLE_PROGRAMS
78 #ifndef HIVE_MEM_vbuf_mipi
79 #define HIVE_MEM_vbuf_mipi scalar_processor_2400_dmem
81 #define HIVE_ADDR_vbuf_mipi 0x631C
83 #define HIVE_ADDR_vbuf_mipi 0x6378
85 #define HIVE_SIZE_vbuf_mipi 12
89 #define HIVE_MEM_sp_vbuf_mipi scalar_processor_2400_dmem
91 #define HIVE_ADDR_sp_vbuf_mipi 0x631C
93 #define HIVE_ADDR_sp_vbuf_mipi 0x6378
95 #define HIVE_SIZE_sp_vbuf_mipi 12
98 /* function ia_css_event_sp_decode: 3536 */
100 /* function ia_css_event_sp_decode: 372A */
104 /* function ia_css_queue_get_size: 48BE */
106 /* function ia_css_queue_get_size: 4B46 */
110 /* function ia_css_queue_load: 4EFF */
112 /* function ia_css_queue_load: 515D */
116 /* function setjmp: 6857 */
118 /* function setjmp: 69CA */
121 #ifndef HIVE_MULTIPLE_PROGRAMS
122 #ifndef HIVE_MEM_sem_for_sp2host_isys_event_queue
123 #define HIVE_MEM_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem
125 #define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x4684
127 #define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x46CC
129 #define HIVE_SIZE_sem_for_sp2host_isys_event_queue 20
133 #define HIVE_MEM_sp_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem
135 #define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x4684
137 #define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x46CC
139 #define HIVE_SIZE_sp_sem_for_sp2host_isys_event_queue 20
142 /* function ia_css_dmaproxy_sp_wait_for_ack: 6E07 */
144 /* function ia_css_dmaproxy_sp_wait_for_ack: 6F4B */
148 /* function ia_css_sp_rawcopy_func: 5124 */
150 /* function ia_css_sp_rawcopy_func: 5382 */
154 /* function ia_css_tagger_buf_sp_pop_marked: 2A10 */
156 /* function ia_css_tagger_buf_sp_pop_marked: 2BB2 */
159 #ifndef HIVE_MULTIPLE_PROGRAMS
160 #ifndef HIVE_MEM_isp_stage
161 #define HIVE_MEM_isp_stage scalar_processor_2400_dmem
163 #define HIVE_ADDR_isp_stage 0x5C00
165 #define HIVE_ADDR_isp_stage 0x5C60
167 #define HIVE_SIZE_isp_stage 832
171 #define HIVE_MEM_sp_isp_stage scalar_processor_2400_dmem
173 #define HIVE_ADDR_sp_isp_stage 0x5C00
175 #define HIVE_ADDR_sp_isp_stage 0x5C60
177 #define HIVE_SIZE_sp_isp_stage 832
179 #ifndef HIVE_MULTIPLE_PROGRAMS
180 #ifndef HIVE_MEM_vbuf_raw
181 #define HIVE_MEM_vbuf_raw scalar_processor_2400_dmem
183 #define HIVE_ADDR_vbuf_raw 0x2F4
185 #define HIVE_ADDR_vbuf_raw 0x30C
187 #define HIVE_SIZE_vbuf_raw 4
191 #define HIVE_MEM_sp_vbuf_raw scalar_processor_2400_dmem
193 #define HIVE_ADDR_sp_vbuf_raw 0x2F4
195 #define HIVE_ADDR_sp_vbuf_raw 0x30C
197 #define HIVE_SIZE_sp_vbuf_raw 4
200 /* function ia_css_sp_bin_copy_func: 504B */
202 /* function ia_css_sp_bin_copy_func: 52A9 */
206 /* function ia_css_queue_item_store: 4C4D */
208 /* function ia_css_queue_item_store: 4EAB */
211 #ifndef HIVE_MULTIPLE_PROGRAMS
212 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs
213 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem
215 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AA0
217 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AFC
219 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_metadata_bufs 20
223 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem
225 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AA0
227 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AFC
229 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 20
231 #ifndef HIVE_MULTIPLE_PROGRAMS
232 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs
233 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem
235 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4AB4
237 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4B10
239 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_buffer_bufs 160
243 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem
245 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4AB4
247 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4B10
249 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 160
251 /* function sp_start_isp: 45D */
253 #ifndef HIVE_MULTIPLE_PROGRAMS
254 #ifndef HIVE_MEM_sp_binary_group
255 #define HIVE_MEM_sp_binary_group scalar_processor_2400_dmem
257 #define HIVE_ADDR_sp_binary_group 0x5FF0
259 #define HIVE_ADDR_sp_binary_group 0x6050
261 #define HIVE_SIZE_sp_binary_group 32
265 #define HIVE_MEM_sp_sp_binary_group scalar_processor_2400_dmem
267 #define HIVE_ADDR_sp_sp_binary_group 0x5FF0
269 #define HIVE_ADDR_sp_sp_binary_group 0x6050
271 #define HIVE_SIZE_sp_sp_binary_group 32
273 #ifndef HIVE_MULTIPLE_PROGRAMS
274 #ifndef HIVE_MEM_sp_sw_state
275 #define HIVE_MEM_sp_sw_state scalar_processor_2400_dmem
277 #define HIVE_ADDR_sp_sw_state 0x62AC
279 #define HIVE_ADDR_sp_sw_state 0x6308
281 #define HIVE_SIZE_sp_sw_state 4
285 #define HIVE_MEM_sp_sp_sw_state scalar_processor_2400_dmem
287 #define HIVE_ADDR_sp_sp_sw_state 0x62AC
289 #define HIVE_ADDR_sp_sp_sw_state 0x6308
291 #define HIVE_SIZE_sp_sp_sw_state 4
294 /* function ia_css_thread_sp_main: D5B */
296 /* function ia_css_thread_sp_main: D50 */
300 /* function ia_css_ispctrl_sp_init_internal_buffers: 373C */
302 /* function ia_css_ispctrl_sp_init_internal_buffers: 396B */
305 #ifndef HIVE_MULTIPLE_PROGRAMS
306 #ifndef HIVE_MEM_sp2host_psys_event_queue_handle
307 #define HIVE_MEM_sp2host_psys_event_queue_handle scalar_processor_2400_dmem
309 #define HIVE_ADDR_sp2host_psys_event_queue_handle 0x4B54
311 #define HIVE_ADDR_sp2host_psys_event_queue_handle 0x4BB0
313 #define HIVE_SIZE_sp2host_psys_event_queue_handle 12
317 #define HIVE_MEM_sp_sp2host_psys_event_queue_handle scalar_processor_2400_dmem
319 #define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x4B54
321 #define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x4BB0
323 #define HIVE_SIZE_sp_sp2host_psys_event_queue_handle 12
325 #ifndef HIVE_MULTIPLE_PROGRAMS
326 #ifndef HIVE_MEM_sem_for_sp2host_psys_event_queue
327 #define HIVE_MEM_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem
329 #define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x4698
331 #define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x46E0
333 #define HIVE_SIZE_sem_for_sp2host_psys_event_queue 20
337 #define HIVE_MEM_sp_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem
339 #define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x4698
341 #define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x46E0
343 #define HIVE_SIZE_sp_sem_for_sp2host_psys_event_queue 20
346 /* function ia_css_tagger_sp_propagate_frame: 2429 */
348 #ifndef HIVE_MULTIPLE_PROGRAMS
349 #ifndef HIVE_MEM_sp_stop_copy_preview
350 #define HIVE_MEM_sp_stop_copy_preview scalar_processor_2400_dmem
351 #define HIVE_ADDR_sp_stop_copy_preview 0x6290
352 #define HIVE_SIZE_sp_stop_copy_preview 4
356 #define HIVE_MEM_sp_sp_stop_copy_preview scalar_processor_2400_dmem
357 #define HIVE_ADDR_sp_sp_stop_copy_preview 0x6290
358 #define HIVE_SIZE_sp_sp_stop_copy_preview 4
360 /* function ia_css_tagger_sp_propagate_frame: 2479 */
364 /* function input_system_reg_load: B17 */
366 /* function input_system_reg_load: B11 */
369 #ifndef HIVE_MULTIPLE_PROGRAMS
370 #ifndef HIVE_MEM_vbuf_handles
371 #define HIVE_MEM_vbuf_handles scalar_processor_2400_dmem
373 #define HIVE_ADDR_vbuf_handles 0x6328
375 #define HIVE_ADDR_vbuf_handles 0x6384
377 #define HIVE_SIZE_vbuf_handles 960
381 #define HIVE_MEM_sp_vbuf_handles scalar_processor_2400_dmem
383 #define HIVE_ADDR_sp_vbuf_handles 0x6328
385 #define HIVE_ADDR_sp_vbuf_handles 0x6384
387 #define HIVE_SIZE_sp_vbuf_handles 960
390 /* function ia_css_queue_store: 4DB3 */
392 /* function ia_css_sp_flash_register: 2C45 */
394 /* function ia_css_queue_store: 5011 */
398 /* function ia_css_sp_rawcopy_dummy_function: 566B */
400 /* function ia_css_sp_flash_register: 2DE7 */
404 /* function ia_css_isys_sp_backend_create: 5B50 */
406 /* function ia_css_isys_sp_backend_create: 5C8B */
410 /* function ia_css_pipeline_sp_init: 184C */
412 /* function ia_css_pipeline_sp_init: 1886 */
416 /* function ia_css_tagger_sp_configure: 2319 */
418 /* function ia_css_tagger_sp_configure: 2369 */
422 /* function ia_css_ispctrl_sp_end_binary: 357F */
424 /* function ia_css_ispctrl_sp_end_binary: 3773 */
427 #ifndef HIVE_MULTIPLE_PROGRAMS
428 #ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs
429 #define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem
431 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4B60
433 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4BBC
435 #define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20
439 #define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem
441 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4B60
443 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4BBC
445 #define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20
448 /* function receiver_port_reg_store: AC9 */
450 /* function receiver_port_reg_store: AC3 */
453 #ifndef HIVE_MULTIPLE_PROGRAMS
454 #ifndef HIVE_MEM_event_is_pending_mask
455 #define HIVE_MEM_event_is_pending_mask scalar_processor_2400_dmem
456 #define HIVE_ADDR_event_is_pending_mask 0x5C
457 #define HIVE_SIZE_event_is_pending_mask 44
461 #define HIVE_MEM_sp_event_is_pending_mask scalar_processor_2400_dmem
462 #define HIVE_ADDR_sp_event_is_pending_mask 0x5C
463 #define HIVE_SIZE_sp_event_is_pending_mask 44
465 #ifndef HIVE_MULTIPLE_PROGRAMS
466 #ifndef HIVE_MEM_sp_all_cb_elems_frame
467 #define HIVE_MEM_sp_all_cb_elems_frame scalar_processor_2400_dmem
469 #define HIVE_ADDR_sp_all_cb_elems_frame 0x46AC
471 #define HIVE_ADDR_sp_all_cb_elems_frame 0x46F4
473 #define HIVE_SIZE_sp_all_cb_elems_frame 16
477 #define HIVE_MEM_sp_sp_all_cb_elems_frame scalar_processor_2400_dmem
479 #define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x46AC
481 #define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x46F4
483 #define HIVE_SIZE_sp_sp_all_cb_elems_frame 16
485 #ifndef HIVE_MULTIPLE_PROGRAMS
486 #ifndef HIVE_MEM_sp2host_isys_event_queue_handle
487 #define HIVE_MEM_sp2host_isys_event_queue_handle scalar_processor_2400_dmem
489 #define HIVE_ADDR_sp2host_isys_event_queue_handle 0x4B74
491 #define HIVE_ADDR_sp2host_isys_event_queue_handle 0x4BD0
493 #define HIVE_SIZE_sp2host_isys_event_queue_handle 12
497 #define HIVE_MEM_sp_sp2host_isys_event_queue_handle scalar_processor_2400_dmem
499 #define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x4B74
501 #define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x4BD0
503 #define HIVE_SIZE_sp_sp2host_isys_event_queue_handle 12
505 #ifndef HIVE_MULTIPLE_PROGRAMS
506 #ifndef HIVE_MEM_host_sp_com
507 #define HIVE_MEM_host_sp_com scalar_processor_2400_dmem
509 #define HIVE_ADDR_host_sp_com 0x4114
511 #define HIVE_ADDR_host_sp_com 0x4134
513 #define HIVE_SIZE_host_sp_com 220
517 #define HIVE_MEM_sp_host_sp_com scalar_processor_2400_dmem
519 #define HIVE_ADDR_sp_host_sp_com 0x4114
521 #define HIVE_ADDR_sp_host_sp_com 0x4134
523 #define HIVE_SIZE_sp_host_sp_com 220
526 /* function ia_css_queue_get_free_space: 4A12 */
528 /* function ia_css_queue_get_free_space: 4C70 */
532 /* function exec_image_pipe: 6C4 */
534 /* function exec_image_pipe: 658 */
537 #ifndef HIVE_MULTIPLE_PROGRAMS
538 #ifndef HIVE_MEM_sp_init_dmem_data
539 #define HIVE_MEM_sp_init_dmem_data scalar_processor_2400_dmem
541 #define HIVE_ADDR_sp_init_dmem_data 0x62B0
543 #define HIVE_ADDR_sp_init_dmem_data 0x630C
545 #define HIVE_SIZE_sp_init_dmem_data 24
549 #define HIVE_MEM_sp_sp_init_dmem_data scalar_processor_2400_dmem
551 #define HIVE_ADDR_sp_sp_init_dmem_data 0x62B0
553 #define HIVE_ADDR_sp_sp_init_dmem_data 0x630C
555 #define HIVE_SIZE_sp_sp_init_dmem_data 24
558 /* function ia_css_sp_metadata_start: 592D */
560 /* function ia_css_sp_metadata_start: 5A68 */
564 /* function ia_css_bufq_sp_init_buffer_queues: 2CB4 */
566 /* function ia_css_bufq_sp_init_buffer_queues: 2E56 */
570 /* function ia_css_pipeline_sp_stop: 182F */
572 /* function ia_css_pipeline_sp_stop: 1869 */
576 /* function ia_css_tagger_sp_connect_pipes: 2803 */
578 /* function ia_css_tagger_sp_connect_pipes: 2853 */
582 /* function sp_isys_copy_wait: 70D */
584 /* function sp_isys_copy_wait: 6A1 */
587 /* function is_isp_debug_buffer_full: 337 */
590 /* function ia_css_dmaproxy_sp_configure_channel_from_info: 32C8 */
592 /* function ia_css_dmaproxy_sp_configure_channel_from_info: 34A9 */
596 /* function encode_and_post_timer_event: A30 */
598 /* function encode_and_post_timer_event: 9C4 */
601 #ifndef HIVE_MULTIPLE_PROGRAMS
602 #ifndef HIVE_MEM_sp_per_frame_data
603 #define HIVE_MEM_sp_per_frame_data scalar_processor_2400_dmem
605 #define HIVE_ADDR_sp_per_frame_data 0x41F0
607 #define HIVE_ADDR_sp_per_frame_data 0x4210
609 #define HIVE_SIZE_sp_per_frame_data 4
613 #define HIVE_MEM_sp_sp_per_frame_data scalar_processor_2400_dmem
615 #define HIVE_ADDR_sp_sp_per_frame_data 0x41F0
617 #define HIVE_ADDR_sp_sp_per_frame_data 0x4210
619 #define HIVE_SIZE_sp_sp_per_frame_data 4
622 /* function ia_css_rmgr_sp_vbuf_dequeue: 62ED */
624 /* function ia_css_rmgr_sp_vbuf_dequeue: 6428 */
627 #ifndef HIVE_MULTIPLE_PROGRAMS
628 #ifndef HIVE_MEM_host2sp_psys_event_queue_handle
629 #define HIVE_MEM_host2sp_psys_event_queue_handle scalar_processor_2400_dmem
631 #define HIVE_ADDR_host2sp_psys_event_queue_handle 0x4B80
633 #define HIVE_ADDR_host2sp_psys_event_queue_handle 0x4BDC
635 #define HIVE_SIZE_host2sp_psys_event_queue_handle 12
639 #define HIVE_MEM_sp_host2sp_psys_event_queue_handle scalar_processor_2400_dmem
641 #define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x4B80
643 #define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x4BDC
645 #define HIVE_SIZE_sp_host2sp_psys_event_queue_handle 12
647 #ifndef HIVE_MULTIPLE_PROGRAMS
648 #ifndef HIVE_MEM_xmem_bin_addr
649 #define HIVE_MEM_xmem_bin_addr scalar_processor_2400_dmem
651 #define HIVE_ADDR_xmem_bin_addr 0x41F4
653 #define HIVE_ADDR_xmem_bin_addr 0x4214
655 #define HIVE_SIZE_xmem_bin_addr 4
659 #define HIVE_MEM_sp_xmem_bin_addr scalar_processor_2400_dmem
661 #define HIVE_ADDR_sp_xmem_bin_addr 0x41F4
663 #define HIVE_ADDR_sp_xmem_bin_addr 0x4214
665 #define HIVE_SIZE_sp_xmem_bin_addr 4
668 /* function tmr_clock_init: 13FB */
670 /* function tmr_clock_init: 141C */
674 /* function ia_css_pipeline_sp_run: 141C */
676 /* function ia_css_pipeline_sp_run: 143D */
680 /* function memcpy: 68F7 */
682 /* function memcpy: 6A6A */
685 #ifndef HIVE_MULTIPLE_PROGRAMS
686 #ifndef HIVE_MEM_GP_DEVICE_BASE
687 #define HIVE_MEM_GP_DEVICE_BASE scalar_processor_2400_dmem
689 #define HIVE_ADDR_GP_DEVICE_BASE 0x2FC
691 #define HIVE_ADDR_GP_DEVICE_BASE 0x314
693 #define HIVE_SIZE_GP_DEVICE_BASE 4
697 #define HIVE_MEM_sp_GP_DEVICE_BASE scalar_processor_2400_dmem
699 #define HIVE_ADDR_sp_GP_DEVICE_BASE 0x2FC
701 #define HIVE_ADDR_sp_GP_DEVICE_BASE 0x314
703 #define HIVE_SIZE_sp_GP_DEVICE_BASE 4
705 #ifndef HIVE_MULTIPLE_PROGRAMS
706 #ifndef HIVE_MEM_ia_css_thread_sp_ready_queue
707 #define HIVE_MEM_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem
709 #define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x1E0
711 #define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x1E4
713 #define HIVE_SIZE_ia_css_thread_sp_ready_queue 12
717 #define HIVE_MEM_sp_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem
719 #define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x1E0
721 #define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x1E4
723 #define HIVE_SIZE_sp_ia_css_thread_sp_ready_queue 12
726 /* function input_system_reg_store: B1E */
728 /* function input_system_reg_store: B18 */
732 /* function ia_css_isys_sp_frontend_start: 5D66 */
734 /* function ia_css_isys_sp_frontend_start: 5EA1 */
738 /* function ia_css_uds_sp_scale_params: 6600 */
740 /* function ia_css_uds_sp_scale_params: 6773 */
744 /* function ia_css_circbuf_increase_size: E40 */
746 /* function ia_css_circbuf_increase_size: E35 */
750 /* function __divu: 6875 */
752 /* function __divu: 69E8 */
756 /* function ia_css_thread_sp_get_state: C83 */
758 /* function ia_css_thread_sp_get_state: C78 */
761 #ifndef HIVE_MULTIPLE_PROGRAMS
762 #ifndef HIVE_MEM_sem_for_cont_capt_stop
763 #define HIVE_MEM_sem_for_cont_capt_stop scalar_processor_2400_dmem
765 #define HIVE_ADDR_sem_for_cont_capt_stop 0x46BC
767 #define HIVE_ADDR_sem_for_cont_capt_stop 0x4704
769 #define HIVE_SIZE_sem_for_cont_capt_stop 20
773 #define HIVE_MEM_sp_sem_for_cont_capt_stop scalar_processor_2400_dmem
775 #define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x46BC
777 #define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x4704
779 #define HIVE_SIZE_sp_sem_for_cont_capt_stop 20
782 /* function thread_fiber_sp_main: E39 */
784 /* function thread_fiber_sp_main: E2E */
787 #ifndef HIVE_MULTIPLE_PROGRAMS
788 #ifndef HIVE_MEM_sp_isp_pipe_thread
789 #define HIVE_MEM_sp_isp_pipe_thread scalar_processor_2400_dmem
791 #define HIVE_ADDR_sp_isp_pipe_thread 0x4800
792 #define HIVE_SIZE_sp_isp_pipe_thread 340
794 #define HIVE_ADDR_sp_isp_pipe_thread 0x4848
795 #define HIVE_SIZE_sp_isp_pipe_thread 360
800 #define HIVE_MEM_sp_sp_isp_pipe_thread scalar_processor_2400_dmem
802 #define HIVE_ADDR_sp_sp_isp_pipe_thread 0x4800
803 #define HIVE_SIZE_sp_sp_isp_pipe_thread 340
805 #define HIVE_ADDR_sp_sp_isp_pipe_thread 0x4848
806 #define HIVE_SIZE_sp_sp_isp_pipe_thread 360
810 /* function ia_css_parambuf_sp_handle_parameter_sets: 128A */
812 /* function ia_css_parambuf_sp_handle_parameter_sets: 127F */
816 /* function ia_css_spctrl_sp_set_state: 595C */
818 /* function ia_css_spctrl_sp_set_state: 5A97 */
822 /* function ia_css_thread_sem_sp_signal: 6AF7 */
824 /* function ia_css_thread_sem_sp_signal: 6C6C */
827 #ifndef HIVE_MULTIPLE_PROGRAMS
828 #ifndef HIVE_MEM_IRQ_BASE
829 #define HIVE_MEM_IRQ_BASE scalar_processor_2400_dmem
830 #define HIVE_ADDR_IRQ_BASE 0x2C
831 #define HIVE_SIZE_IRQ_BASE 16
835 #define HIVE_MEM_sp_IRQ_BASE scalar_processor_2400_dmem
836 #define HIVE_ADDR_sp_IRQ_BASE 0x2C
837 #define HIVE_SIZE_sp_IRQ_BASE 16
839 #ifndef HIVE_MULTIPLE_PROGRAMS
840 #ifndef HIVE_MEM_TIMED_CTRL_BASE
841 #define HIVE_MEM_TIMED_CTRL_BASE scalar_processor_2400_dmem
842 #define HIVE_ADDR_TIMED_CTRL_BASE 0x40
843 #define HIVE_SIZE_TIMED_CTRL_BASE 4
847 #define HIVE_MEM_sp_TIMED_CTRL_BASE scalar_processor_2400_dmem
848 #define HIVE_ADDR_sp_TIMED_CTRL_BASE 0x40
849 #define HIVE_SIZE_sp_TIMED_CTRL_BASE 4
852 /* function ia_css_isys_sp_isr: 6FDC */
854 /* function ia_css_isys_sp_generate_exp_id: 60FE */
856 /* function ia_css_isys_sp_isr: 7139 */
860 /* function ia_css_rmgr_sp_init: 61E8 */
862 /* function ia_css_isys_sp_generate_exp_id: 6239 */
866 /* function ia_css_thread_sem_sp_init: 6BC8 */
868 /* function ia_css_rmgr_sp_init: 6323 */
872 #ifndef HIVE_MULTIPLE_PROGRAMS
873 #ifndef HIVE_MEM_is_isp_requested
874 #define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem
875 #define HIVE_ADDR_is_isp_requested 0x308
876 #define HIVE_SIZE_is_isp_requested 4
880 #define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem
881 #define HIVE_ADDR_sp_is_isp_requested 0x308
882 #define HIVE_SIZE_sp_is_isp_requested 4
884 /* function ia_css_thread_sem_sp_init: 6D3B */
887 #ifndef HIVE_MULTIPLE_PROGRAMS
888 #ifndef HIVE_MEM_sem_for_reading_cb_frame
889 #define HIVE_MEM_sem_for_reading_cb_frame scalar_processor_2400_dmem
891 #define HIVE_ADDR_sem_for_reading_cb_frame 0x46D0
893 #define HIVE_ADDR_sem_for_reading_cb_frame 0x4718
895 #define HIVE_SIZE_sem_for_reading_cb_frame 40
899 #define HIVE_MEM_sp_sem_for_reading_cb_frame scalar_processor_2400_dmem
901 #define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x46D0
903 #define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x4718
905 #define HIVE_SIZE_sp_sem_for_reading_cb_frame 40
908 /* function ia_css_dmaproxy_sp_execute: 3230 */
910 #ifndef HIVE_MULTIPLE_PROGRAMS
911 #ifndef HIVE_MEM_is_isp_requested
912 #define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem
913 #define HIVE_ADDR_is_isp_requested 0x320
914 #define HIVE_SIZE_is_isp_requested 4
918 #define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem
919 #define HIVE_ADDR_sp_is_isp_requested 0x320
920 #define HIVE_SIZE_sp_is_isp_requested 4
922 /* function ia_css_dmaproxy_sp_execute: 340F */
926 /* function ia_css_queue_is_empty: 48F9 */
928 /* function ia_css_queue_is_empty: 7098 */
932 /* function ia_css_pipeline_sp_has_stopped: 1825 */
934 /* function ia_css_pipeline_sp_has_stopped: 185F */
938 /* function ia_css_circbuf_extract: F44 */
940 /* function ia_css_circbuf_extract: F39 */
944 /* function ia_css_tagger_buf_sp_is_locked_from_start: 2B26 */
946 /* function ia_css_tagger_buf_sp_is_locked_from_start: 2CC8 */
949 #ifndef HIVE_MULTIPLE_PROGRAMS
950 #ifndef HIVE_MEM_current_sp_thread
951 #define HIVE_MEM_current_sp_thread scalar_processor_2400_dmem
952 #define HIVE_ADDR_current_sp_thread 0x1DC
953 #define HIVE_SIZE_current_sp_thread 4
957 #define HIVE_MEM_sp_current_sp_thread scalar_processor_2400_dmem
958 #define HIVE_ADDR_sp_current_sp_thread 0x1DC
959 #define HIVE_SIZE_sp_current_sp_thread 4
962 /* function ia_css_spctrl_sp_get_spid: 5963 */
964 /* function ia_css_spctrl_sp_get_spid: 5A9E */
968 /* function ia_css_bufq_sp_reset_buffers: 2D3B */
970 /* function ia_css_bufq_sp_reset_buffers: 2EDD */
974 /* function ia_css_dmaproxy_sp_read_byte_addr: 6E35 */
976 /* function ia_css_dmaproxy_sp_read_byte_addr: 6F79 */
980 /* function ia_css_rmgr_sp_uninit: 61E1 */
982 /* function ia_css_rmgr_sp_uninit: 631C */
985 #ifndef HIVE_MULTIPLE_PROGRAMS
986 #ifndef HIVE_MEM_sp_threads_stack
987 #define HIVE_MEM_sp_threads_stack scalar_processor_2400_dmem
988 #define HIVE_ADDR_sp_threads_stack 0x164
989 #define HIVE_SIZE_sp_threads_stack 28
993 #define HIVE_MEM_sp_sp_threads_stack scalar_processor_2400_dmem
994 #define HIVE_ADDR_sp_sp_threads_stack 0x164
995 #define HIVE_SIZE_sp_sp_threads_stack 28
998 /* function ia_css_circbuf_peek: F26 */
1000 /* function ia_css_circbuf_peek: F1B */
1004 /* function ia_css_parambuf_sp_wait_for_in_param: 1053 */
1006 /* function ia_css_parambuf_sp_wait_for_in_param: 1048 */
1010 /* function ia_css_isys_sp_token_map_get_exp_id: 5FC6 */
1012 /* function ia_css_isys_sp_token_map_get_exp_id: 6101 */
1015 #ifndef HIVE_MULTIPLE_PROGRAMS
1016 #ifndef HIVE_MEM_sp_all_cb_elems_param
1017 #define HIVE_MEM_sp_all_cb_elems_param scalar_processor_2400_dmem
1019 #define HIVE_ADDR_sp_all_cb_elems_param 0x46F8
1021 #define HIVE_ADDR_sp_all_cb_elems_param 0x4740
1023 #define HIVE_SIZE_sp_all_cb_elems_param 16
1027 #define HIVE_MEM_sp_sp_all_cb_elems_param scalar_processor_2400_dmem
1029 #define HIVE_ADDR_sp_sp_all_cb_elems_param 0x46F8
1031 #define HIVE_ADDR_sp_sp_all_cb_elems_param 0x4740
1033 #define HIVE_SIZE_sp_sp_all_cb_elems_param 16
1035 #ifndef HIVE_MULTIPLE_PROGRAMS
1036 #ifndef HIVE_MEM_pipeline_sp_curr_binary_id
1037 #define HIVE_MEM_pipeline_sp_curr_binary_id scalar_processor_2400_dmem
1039 #define HIVE_ADDR_pipeline_sp_curr_binary_id 0x1EC
1041 #define HIVE_ADDR_pipeline_sp_curr_binary_id 0x1F0
1043 #define HIVE_SIZE_pipeline_sp_curr_binary_id 4
1047 #define HIVE_MEM_sp_pipeline_sp_curr_binary_id scalar_processor_2400_dmem
1049 #define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x1EC
1051 #define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x1F0
1053 #define HIVE_SIZE_sp_pipeline_sp_curr_binary_id 4
1055 #ifndef HIVE_MULTIPLE_PROGRAMS
1056 #ifndef HIVE_MEM_sp_all_cbs_frame_desc
1057 #define HIVE_MEM_sp_all_cbs_frame_desc scalar_processor_2400_dmem
1059 #define HIVE_ADDR_sp_all_cbs_frame_desc 0x4708
1061 #define HIVE_ADDR_sp_all_cbs_frame_desc 0x4750
1063 #define HIVE_SIZE_sp_all_cbs_frame_desc 8
1067 #define HIVE_MEM_sp_sp_all_cbs_frame_desc scalar_processor_2400_dmem
1069 #define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x4708
1071 #define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x4750
1073 #define HIVE_SIZE_sp_sp_all_cbs_frame_desc 8
1076 /* function sp_isys_copy_func_v2: 706 */
1078 /* function sp_isys_copy_func_v2: 69A */
1081 #ifndef HIVE_MULTIPLE_PROGRAMS
1082 #ifndef HIVE_MEM_sem_for_reading_cb_param
1083 #define HIVE_MEM_sem_for_reading_cb_param scalar_processor_2400_dmem
1085 #define HIVE_ADDR_sem_for_reading_cb_param 0x4710
1087 #define HIVE_ADDR_sem_for_reading_cb_param 0x4758
1089 #define HIVE_SIZE_sem_for_reading_cb_param 40
1093 #define HIVE_MEM_sp_sem_for_reading_cb_param scalar_processor_2400_dmem
1095 #define HIVE_ADDR_sp_sem_for_reading_cb_param 0x4710
1097 #define HIVE_ADDR_sp_sem_for_reading_cb_param 0x4758
1099 #define HIVE_SIZE_sp_sem_for_reading_cb_param 40
1102 /* function ia_css_queue_get_used_space: 49C6 */
1104 /* function ia_css_queue_get_used_space: 4C24 */
1107 #ifndef HIVE_MULTIPLE_PROGRAMS
1108 #ifndef HIVE_MEM_sem_for_cont_capt_start
1109 #define HIVE_MEM_sem_for_cont_capt_start scalar_processor_2400_dmem
1111 #define HIVE_ADDR_sem_for_cont_capt_start 0x4738
1113 #define HIVE_ADDR_sem_for_cont_capt_start 0x4780
1115 #define HIVE_SIZE_sem_for_cont_capt_start 20
1119 #define HIVE_MEM_sp_sem_for_cont_capt_start scalar_processor_2400_dmem
1121 #define HIVE_ADDR_sp_sem_for_cont_capt_start 0x4738
1123 #define HIVE_ADDR_sp_sem_for_cont_capt_start 0x4780
1125 #define HIVE_SIZE_sp_sem_for_cont_capt_start 20
1127 #ifndef HIVE_MULTIPLE_PROGRAMS
1128 #ifndef HIVE_MEM_tmp_heap
1129 #define HIVE_MEM_tmp_heap scalar_processor_2400_dmem
1131 #define HIVE_ADDR_tmp_heap 0x6010
1133 #define HIVE_ADDR_tmp_heap 0x6070
1135 #define HIVE_SIZE_tmp_heap 640
1139 #define HIVE_MEM_sp_tmp_heap scalar_processor_2400_dmem
1141 #define HIVE_ADDR_sp_tmp_heap 0x6010
1143 #define HIVE_ADDR_sp_tmp_heap 0x6070
1145 #define HIVE_SIZE_sp_tmp_heap 640
1148 /* function ia_css_rmgr_sp_get_num_vbuf: 64F1 */
1150 /* function ia_css_rmgr_sp_get_num_vbuf: 662C */
1154 /* function ia_css_ispctrl_sp_output_compute_dma_info: 3F62 */
1156 /* function ia_css_ispctrl_sp_output_compute_dma_info: 41A5 */
1160 /* function ia_css_tagger_sp_lock_exp_id: 20E6 */
1162 /* function ia_css_tagger_sp_lock_exp_id: 2136 */
1165 #ifndef HIVE_MULTIPLE_PROGRAMS
1166 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs
1167 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem
1169 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4B8C
1171 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4BE8
1173 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_s3a_bufs 60
1177 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem
1179 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4B8C
1181 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4BE8
1183 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 60
1186 /* function ia_css_queue_is_full: 4A5D */
1188 /* function ia_css_queue_is_full: 4CBB */
1191 /* function debug_buffer_init_isp: E4 */
1194 /* function ia_css_isys_sp_frontend_uninit: 5D20 */
1196 /* function ia_css_isys_sp_frontend_uninit: 5E5B */
1200 /* function ia_css_tagger_sp_exp_id_is_locked: 201C */
1202 /* function ia_css_tagger_sp_exp_id_is_locked: 206C */
1205 #ifndef HIVE_MULTIPLE_PROGRAMS
1206 #ifndef HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem
1207 #define HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem
1209 #define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x66E8
1211 #define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x6744
1213 #define HIVE_SIZE_ia_css_rmgr_sp_mipi_frame_sem 60
1217 #define HIVE_MEM_sp_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem
1219 #define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x66E8
1221 #define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x6744
1223 #define HIVE_SIZE_sp_ia_css_rmgr_sp_mipi_frame_sem 60
1226 /* function ia_css_rmgr_sp_refcount_dump: 62C8 */
1228 /* function ia_css_rmgr_sp_refcount_dump: 6403 */
1231 #ifndef HIVE_MULTIPLE_PROGRAMS
1232 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id
1233 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem
1235 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4BC8
1237 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4C24
1239 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_isp_parameters_id 20
1243 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem
1245 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4BC8
1247 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4C24
1249 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 20
1251 #ifndef HIVE_MULTIPLE_PROGRAMS
1252 #ifndef HIVE_MEM_sp_pipe_threads
1253 #define HIVE_MEM_sp_pipe_threads scalar_processor_2400_dmem
1254 #define HIVE_ADDR_sp_pipe_threads 0x150
1255 #define HIVE_SIZE_sp_pipe_threads 20
1259 #define HIVE_MEM_sp_sp_pipe_threads scalar_processor_2400_dmem
1260 #define HIVE_ADDR_sp_sp_pipe_threads 0x150
1261 #define HIVE_SIZE_sp_sp_pipe_threads 20
1264 /* function sp_event_proxy_func: 71B */
1266 /* function sp_event_proxy_func: 6AF */
1269 #ifndef HIVE_MULTIPLE_PROGRAMS
1270 #ifndef HIVE_MEM_host2sp_isys_event_queue_handle
1271 #define HIVE_MEM_host2sp_isys_event_queue_handle scalar_processor_2400_dmem
1273 #define HIVE_ADDR_host2sp_isys_event_queue_handle 0x4BDC
1275 #define HIVE_ADDR_host2sp_isys_event_queue_handle 0x4C38
1277 #define HIVE_SIZE_host2sp_isys_event_queue_handle 12
1281 #define HIVE_MEM_sp_host2sp_isys_event_queue_handle scalar_processor_2400_dmem
1283 #define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x4BDC
1285 #define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x4C38
1287 #define HIVE_SIZE_sp_host2sp_isys_event_queue_handle 12
1290 /* function ia_css_thread_sp_yield: 6A70 */
1292 /* function ia_css_thread_sp_yield: 6BEA */
1295 #ifndef HIVE_MULTIPLE_PROGRAMS
1296 #ifndef HIVE_MEM_sp_all_cbs_param_desc
1297 #define HIVE_MEM_sp_all_cbs_param_desc scalar_processor_2400_dmem
1299 #define HIVE_ADDR_sp_all_cbs_param_desc 0x474C
1301 #define HIVE_ADDR_sp_all_cbs_param_desc 0x4794
1303 #define HIVE_SIZE_sp_all_cbs_param_desc 8
1307 #define HIVE_MEM_sp_sp_all_cbs_param_desc scalar_processor_2400_dmem
1309 #define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x474C
1311 #define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x4794
1313 #define HIVE_SIZE_sp_sp_all_cbs_param_desc 8
1315 #ifndef HIVE_MULTIPLE_PROGRAMS
1316 #ifndef HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb
1317 #define HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem
1319 #define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x5BF4
1321 #define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x5C50
1323 #define HIVE_SIZE_ia_css_dmaproxy_sp_invalidate_tlb 4
1327 #define HIVE_MEM_sp_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem
1329 #define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x5BF4
1331 #define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x5C50
1333 #define HIVE_SIZE_sp_ia_css_dmaproxy_sp_invalidate_tlb 4
1336 /* function ia_css_thread_sp_fork: D10 */
1338 /* function ia_css_thread_sp_fork: D05 */
1342 /* function ia_css_tagger_sp_destroy: 280D */
1344 /* function ia_css_tagger_sp_destroy: 285D */
1348 /* function ia_css_dmaproxy_sp_vmem_read: 31D0 */
1350 /* function ia_css_dmaproxy_sp_vmem_read: 33AF */
1354 /* function ia_css_ifmtr_sp_init: 614F */
1356 /* function ia_css_ifmtr_sp_init: 628A */
1360 /* function initialize_sp_group: 6D4 */
1362 /* function initialize_sp_group: 668 */
1366 /* function ia_css_tagger_buf_sp_peek: 2932 */
1368 /* function ia_css_tagger_buf_sp_peek: 2AD4 */
1372 /* function ia_css_thread_sp_init: D3C */
1374 /* function ia_css_thread_sp_init: D31 */
1378 /* function ia_css_isys_sp_reset_exp_id: 60F6 */
1380 /* function ia_css_isys_sp_reset_exp_id: 6231 */
1384 /* function qos_scheduler_update_fps: 65F0 */
1386 /* function qos_scheduler_update_fps: 6763 */
1390 /* function ia_css_ispctrl_sp_set_stream_base_addr: 4637 */
1392 /* function ia_css_ispctrl_sp_set_stream_base_addr: 4892 */
1395 #ifndef HIVE_MULTIPLE_PROGRAMS
1396 #ifndef HIVE_MEM_ISP_DMEM_BASE
1397 #define HIVE_MEM_ISP_DMEM_BASE scalar_processor_2400_dmem
1398 #define HIVE_ADDR_ISP_DMEM_BASE 0x10
1399 #define HIVE_SIZE_ISP_DMEM_BASE 4
1403 #define HIVE_MEM_sp_ISP_DMEM_BASE scalar_processor_2400_dmem
1404 #define HIVE_ADDR_sp_ISP_DMEM_BASE 0x10
1405 #define HIVE_SIZE_sp_ISP_DMEM_BASE 4
1407 #ifndef HIVE_MULTIPLE_PROGRAMS
1408 #ifndef HIVE_MEM_SP_DMEM_BASE
1409 #define HIVE_MEM_SP_DMEM_BASE scalar_processor_2400_dmem
1410 #define HIVE_ADDR_SP_DMEM_BASE 0x4
1411 #define HIVE_SIZE_SP_DMEM_BASE 4
1415 #define HIVE_MEM_sp_SP_DMEM_BASE scalar_processor_2400_dmem
1416 #define HIVE_ADDR_sp_SP_DMEM_BASE 0x4
1417 #define HIVE_SIZE_sp_SP_DMEM_BASE 4
1420 /* function ia_css_dmaproxy_sp_read: 3246 */
1422 /* function __ia_css_queue_is_empty_text: 4B81 */
1424 /* function ia_css_dmaproxy_sp_read: 3425 */
1427 #ifndef HIVE_MULTIPLE_PROGRAMS
1428 #ifndef HIVE_MEM_raw_copy_line_count
1429 #define HIVE_MEM_raw_copy_line_count scalar_processor_2400_dmem
1431 #define HIVE_ADDR_raw_copy_line_count 0x2C8
1433 #define HIVE_ADDR_raw_copy_line_count 0x2E0
1435 #define HIVE_SIZE_raw_copy_line_count 4
1439 #define HIVE_MEM_sp_raw_copy_line_count scalar_processor_2400_dmem
1441 #define HIVE_ADDR_sp_raw_copy_line_count 0x2C8
1443 #define HIVE_ADDR_sp_raw_copy_line_count 0x2E0
1445 #define HIVE_SIZE_sp_raw_copy_line_count 4
1447 #ifndef HIVE_MULTIPLE_PROGRAMS
1448 #ifndef HIVE_MEM_host2sp_tag_cmd_queue_handle
1449 #define HIVE_MEM_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem
1451 #define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x4BE8
1453 #define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x4C44
1455 #define HIVE_SIZE_host2sp_tag_cmd_queue_handle 12
1459 #define HIVE_MEM_sp_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem
1461 #define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x4BE8
1463 #define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x4C44
1465 #define HIVE_SIZE_sp_host2sp_tag_cmd_queue_handle 12
1468 /* function ia_css_queue_peek: 493C */
1470 /* function ia_css_queue_peek: 4B9A */
1473 #ifndef HIVE_MULTIPLE_PROGRAMS
1474 #ifndef HIVE_MEM_ia_css_flash_sp_frame_cnt
1475 #define HIVE_MEM_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem
1477 #define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x4A94
1479 #define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x4AF0
1481 #define HIVE_SIZE_ia_css_flash_sp_frame_cnt 4
1485 #define HIVE_MEM_sp_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem
1487 #define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x4A94
1489 #define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x4AF0
1491 #define HIVE_SIZE_sp_ia_css_flash_sp_frame_cnt 4
1493 #ifndef HIVE_MULTIPLE_PROGRAMS
1494 #ifndef HIVE_MEM_event_can_send_token_mask
1495 #define HIVE_MEM_event_can_send_token_mask scalar_processor_2400_dmem
1496 #define HIVE_ADDR_event_can_send_token_mask 0x88
1497 #define HIVE_SIZE_event_can_send_token_mask 44
1501 #define HIVE_MEM_sp_event_can_send_token_mask scalar_processor_2400_dmem
1502 #define HIVE_ADDR_sp_event_can_send_token_mask 0x88
1503 #define HIVE_SIZE_sp_event_can_send_token_mask 44
1505 #ifndef HIVE_MULTIPLE_PROGRAMS
1506 #ifndef HIVE_MEM_isp_thread
1507 #define HIVE_MEM_isp_thread scalar_processor_2400_dmem
1509 #define HIVE_ADDR_isp_thread 0x5F40
1511 #define HIVE_ADDR_isp_thread 0x5FA0
1513 #define HIVE_SIZE_isp_thread 4
1517 #define HIVE_MEM_sp_isp_thread scalar_processor_2400_dmem
1519 #define HIVE_ADDR_sp_isp_thread 0x5F40
1521 #define HIVE_ADDR_sp_isp_thread 0x5FA0
1523 #define HIVE_SIZE_sp_isp_thread 4
1526 /* function encode_and_post_sp_event_non_blocking: A78 */
1528 /* function encode_and_post_sp_event_non_blocking: A0C */
1532 /* function ia_css_isys_sp_frontend_destroy: 5DF8 */
1534 /* function ia_css_isys_sp_frontend_destroy: 5F33 */
1537 /* function is_ddr_debug_buffer_full: 2CC */
1540 /* function ia_css_isys_sp_frontend_stop: 5D38 */
1542 /* function ia_css_isys_sp_frontend_stop: 5E73 */
1546 /* function ia_css_isys_sp_token_map_init: 6094 */
1548 /* function ia_css_isys_sp_token_map_init: 61CF */
1552 /* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 2982 */
1554 /* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 2B24 */
1557 #ifndef HIVE_MULTIPLE_PROGRAMS
1558 #ifndef HIVE_MEM_sp_threads_fiber
1559 #define HIVE_MEM_sp_threads_fiber scalar_processor_2400_dmem
1560 #define HIVE_ADDR_sp_threads_fiber 0x19C
1561 #define HIVE_SIZE_sp_threads_fiber 28
1565 #define HIVE_MEM_sp_sp_threads_fiber scalar_processor_2400_dmem
1566 #define HIVE_ADDR_sp_sp_threads_fiber 0x19C
1567 #define HIVE_SIZE_sp_sp_threads_fiber 28
1570 /* function encode_and_post_sp_event: A01 */
1572 /* function encode_and_post_sp_event: 995 */
1575 /* function debug_enqueue_ddr: EE */
1578 /* function ia_css_rmgr_sp_refcount_init_vbuf: 6283 */
1580 /* function ia_css_rmgr_sp_refcount_init_vbuf: 63BE */
1584 /* function dmaproxy_sp_read_write: 6EE4 */
1586 /* function dmaproxy_sp_read_write: 7017 */
1589 #ifndef HIVE_MULTIPLE_PROGRAMS
1590 #ifndef HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer
1591 #define HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem
1593 #define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5BF8
1595 #define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5C54
1597 #define HIVE_SIZE_ia_css_dmaproxy_isp_dma_cmd_buffer 4
1601 #define HIVE_MEM_sp_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem
1603 #define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5BF8
1605 #define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5C54
1607 #define HIVE_SIZE_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 4
1609 #ifndef HIVE_MULTIPLE_PROGRAMS
1610 #ifndef HIVE_MEM_host2sp_buffer_queue_handle
1611 #define HIVE_MEM_host2sp_buffer_queue_handle scalar_processor_2400_dmem
1613 #define HIVE_ADDR_host2sp_buffer_queue_handle 0x4BF4
1615 #define HIVE_ADDR_host2sp_buffer_queue_handle 0x4C50
1617 #define HIVE_SIZE_host2sp_buffer_queue_handle 480
1621 #define HIVE_MEM_sp_host2sp_buffer_queue_handle scalar_processor_2400_dmem
1623 #define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x4BF4
1625 #define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x4C50
1627 #define HIVE_SIZE_sp_host2sp_buffer_queue_handle 480
1629 #ifndef HIVE_MULTIPLE_PROGRAMS
1630 #ifndef HIVE_MEM_ia_css_flash_sp_in_service
1631 #define HIVE_MEM_ia_css_flash_sp_in_service scalar_processor_2400_dmem
1633 #define HIVE_ADDR_ia_css_flash_sp_in_service 0x3178
1635 #define HIVE_ADDR_ia_css_flash_sp_in_service 0x3198
1637 #define HIVE_SIZE_ia_css_flash_sp_in_service 4
1641 #define HIVE_MEM_sp_ia_css_flash_sp_in_service scalar_processor_2400_dmem
1643 #define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3178
1645 #define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3198
1647 #define HIVE_SIZE_sp_ia_css_flash_sp_in_service 4
1650 /* function ia_css_dmaproxy_sp_process: 6BF0 */
1652 /* function ia_css_dmaproxy_sp_process: 6D63 */
1656 /* function ia_css_tagger_buf_sp_mark_from_end: 2C0A */
1658 /* function ia_css_tagger_buf_sp_mark_from_end: 2DAC */
1662 /* function ia_css_isys_sp_backend_rcv_acquire_ack: 5A05 */
1664 /* function ia_css_isys_sp_backend_rcv_acquire_ack: 5B40 */
1668 /* function ia_css_isys_sp_backend_pre_acquire_request: 5A1B */
1670 /* function ia_css_isys_sp_backend_pre_acquire_request: 5B56 */
1674 /* function ia_css_ispctrl_sp_init_cs: 366C */
1676 /* function ia_css_ispctrl_sp_init_cs: 386E */
1680 /* function ia_css_spctrl_sp_init: 5971 */
1682 /* function ia_css_spctrl_sp_init: 5AAC */
1686 /* function sp_event_proxy_init: 730 */
1688 /* function sp_event_proxy_init: 6C4 */
1691 #ifndef HIVE_MULTIPLE_PROGRAMS
1692 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick
1693 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem
1695 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4DD4
1697 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4E30
1699 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_previous_clock_tick 40
1703 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem
1705 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4DD4
1707 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4E30
1709 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 40
1711 #ifndef HIVE_MULTIPLE_PROGRAMS
1712 #ifndef HIVE_MEM_sp_output
1713 #define HIVE_MEM_sp_output scalar_processor_2400_dmem
1715 #define HIVE_ADDR_sp_output 0x41F8
1717 #define HIVE_ADDR_sp_output 0x4218
1719 #define HIVE_SIZE_sp_output 16
1723 #define HIVE_MEM_sp_sp_output scalar_processor_2400_dmem
1725 #define HIVE_ADDR_sp_sp_output 0x41F8
1727 #define HIVE_ADDR_sp_sp_output 0x4218
1729 #define HIVE_SIZE_sp_sp_output 16
1731 #ifndef HIVE_MULTIPLE_PROGRAMS
1732 #ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues
1733 #define HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem
1735 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4DFC
1737 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4E58
1739 #define HIVE_SIZE_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800
1743 #define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem
1745 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4DFC
1747 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4E58
1749 #define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800
1751 #ifndef HIVE_MULTIPLE_PROGRAMS
1752 #ifndef HIVE_MEM_ISP_CTRL_BASE
1753 #define HIVE_MEM_ISP_CTRL_BASE scalar_processor_2400_dmem
1754 #define HIVE_ADDR_ISP_CTRL_BASE 0x8
1755 #define HIVE_SIZE_ISP_CTRL_BASE 4
1759 #define HIVE_MEM_sp_ISP_CTRL_BASE scalar_processor_2400_dmem
1760 #define HIVE_ADDR_sp_ISP_CTRL_BASE 0x8
1761 #define HIVE_SIZE_sp_ISP_CTRL_BASE 4
1763 #ifndef HIVE_MULTIPLE_PROGRAMS
1764 #ifndef HIVE_MEM_INPUT_FORMATTER_BASE
1765 #define HIVE_MEM_INPUT_FORMATTER_BASE scalar_processor_2400_dmem
1766 #define HIVE_ADDR_INPUT_FORMATTER_BASE 0x4C
1767 #define HIVE_SIZE_INPUT_FORMATTER_BASE 16
1771 #define HIVE_MEM_sp_INPUT_FORMATTER_BASE scalar_processor_2400_dmem
1772 #define HIVE_ADDR_sp_INPUT_FORMATTER_BASE 0x4C
1773 #define HIVE_SIZE_sp_INPUT_FORMATTER_BASE 16
1776 /* function sp_dma_proxy_reset_channels: 34A0 */
1778 /* function sp_dma_proxy_reset_channels: 3694 */
1782 /* function ia_css_isys_sp_backend_acquire: 5B26 */
1784 /* function ia_css_isys_sp_backend_acquire: 5C61 */
1788 /* function ia_css_tagger_sp_update_size: 2901 */
1790 /* function ia_css_tagger_sp_update_size: 2AA3 */
1793 #ifndef HIVE_MULTIPLE_PROGRAMS
1794 #ifndef HIVE_MEM_ia_css_bufq_host_sp_queue
1795 #define HIVE_MEM_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem
1797 #define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x511C
1799 #define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x5178
1801 #define HIVE_SIZE_ia_css_bufq_host_sp_queue 2008
1805 #define HIVE_MEM_sp_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem
1807 #define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x511C
1809 #define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x5178
1811 #define HIVE_SIZE_sp_ia_css_bufq_host_sp_queue 2008
1814 /* function thread_fiber_sp_create: DA8 */
1816 /* function thread_fiber_sp_create: D9D */
1820 /* function ia_css_dmaproxy_sp_set_increments: 3332 */
1822 /* function ia_css_dmaproxy_sp_set_increments: 3526 */
1825 #ifndef HIVE_MULTIPLE_PROGRAMS
1826 #ifndef HIVE_MEM_sem_for_writing_cb_frame
1827 #define HIVE_MEM_sem_for_writing_cb_frame scalar_processor_2400_dmem
1829 #define HIVE_ADDR_sem_for_writing_cb_frame 0x4754
1831 #define HIVE_ADDR_sem_for_writing_cb_frame 0x479C
1833 #define HIVE_SIZE_sem_for_writing_cb_frame 20
1837 #define HIVE_MEM_sp_sem_for_writing_cb_frame scalar_processor_2400_dmem
1839 #define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x4754
1841 #define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x479C
1843 #define HIVE_SIZE_sp_sem_for_writing_cb_frame 20
1846 /* function receiver_reg_store: AD7 */
1848 /* function receiver_reg_store: AD1 */
1851 #ifndef HIVE_MULTIPLE_PROGRAMS
1852 #ifndef HIVE_MEM_sem_for_writing_cb_param
1853 #define HIVE_MEM_sem_for_writing_cb_param scalar_processor_2400_dmem
1855 #define HIVE_ADDR_sem_for_writing_cb_param 0x4768
1857 #define HIVE_ADDR_sem_for_writing_cb_param 0x47B0
1859 #define HIVE_SIZE_sem_for_writing_cb_param 20
1863 #define HIVE_MEM_sp_sem_for_writing_cb_param scalar_processor_2400_dmem
1865 #define HIVE_ADDR_sp_sem_for_writing_cb_param 0x4768
1867 #define HIVE_ADDR_sp_sem_for_writing_cb_param 0x47B0
1869 #define HIVE_SIZE_sp_sem_for_writing_cb_param 20
1871 /* function sp_start_isp_entry: 453 */
1872 #ifndef HIVE_MULTIPLE_PROGRAMS
1873 #ifdef HIVE_ADDR_sp_start_isp_entry
1875 #define HIVE_ADDR_sp_start_isp_entry 0x453
1877 #define HIVE_ADDR_sp_sp_start_isp_entry 0x453
1880 /* function ia_css_tagger_buf_sp_unmark_all: 2B8E */
1882 /* function ia_css_tagger_buf_sp_unmark_all: 2D30 */
1886 /* function ia_css_tagger_buf_sp_unmark_from_start: 2BCF */
1888 /* function ia_css_tagger_buf_sp_unmark_from_start: 2D71 */
1892 /* function ia_css_dmaproxy_sp_channel_acquire: 34CC */
1894 /* function ia_css_dmaproxy_sp_channel_acquire: 36C0 */
1898 /* function ia_css_rmgr_sp_add_num_vbuf: 64CD */
1900 /* function ia_css_rmgr_sp_add_num_vbuf: 6608 */
1904 /* function ia_css_isys_sp_token_map_create: 60DD */
1906 /* function ia_css_isys_sp_token_map_create: 6218 */
1910 /* function __ia_css_dmaproxy_sp_wait_for_ack_text: 319C */
1912 /* function __ia_css_dmaproxy_sp_wait_for_ack_text: 337B */
1916 /* function ia_css_tagger_sp_acquire_buf_elem: 1FF4 */
1918 /* function ia_css_tagger_sp_acquire_buf_elem: 2044 */
1922 /* function ia_css_bufq_sp_is_dynamic_buffer: 3085 */
1924 /* function ia_css_bufq_sp_is_dynamic_buffer: 3227 */
1927 #ifndef HIVE_MULTIPLE_PROGRAMS
1928 #ifndef HIVE_MEM_sp_group
1929 #define HIVE_MEM_sp_group scalar_processor_2400_dmem
1931 #define HIVE_ADDR_sp_group 0x4208
1932 #define HIVE_SIZE_sp_group 1144
1934 #define HIVE_ADDR_sp_group 0x4228
1935 #define HIVE_SIZE_sp_group 1184
1940 #define HIVE_MEM_sp_sp_group scalar_processor_2400_dmem
1942 #define HIVE_ADDR_sp_sp_group 0x4208
1943 #define HIVE_SIZE_sp_sp_group 1144
1945 #define HIVE_ADDR_sp_sp_group 0x4228
1946 #define HIVE_SIZE_sp_sp_group 1184
1949 #ifndef HIVE_MULTIPLE_PROGRAMS
1950 #ifndef HIVE_MEM_sp_event_proxy_thread
1951 #define HIVE_MEM_sp_event_proxy_thread scalar_processor_2400_dmem
1953 #define HIVE_ADDR_sp_event_proxy_thread 0x4954
1954 #define HIVE_SIZE_sp_event_proxy_thread 68
1956 #define HIVE_ADDR_sp_event_proxy_thread 0x49B0
1957 #define HIVE_SIZE_sp_event_proxy_thread 72
1962 #define HIVE_MEM_sp_sp_event_proxy_thread scalar_processor_2400_dmem
1964 #define HIVE_ADDR_sp_sp_event_proxy_thread 0x4954
1965 #define HIVE_SIZE_sp_sp_event_proxy_thread 68
1967 #define HIVE_ADDR_sp_sp_event_proxy_thread 0x49B0
1968 #define HIVE_SIZE_sp_sp_event_proxy_thread 72
1972 /* function ia_css_thread_sp_kill: CD6 */
1974 /* function ia_css_thread_sp_kill: CCB */
1978 /* function ia_css_tagger_sp_create: 28BB */
1980 /* function ia_css_tagger_sp_create: 2A51 */
1984 /* function tmpmem_acquire_dmem: 657A */
1986 /* function tmpmem_acquire_dmem: 66B5 */
1989 #ifndef HIVE_MULTIPLE_PROGRAMS
1990 #ifndef HIVE_MEM_MMU_BASE
1991 #define HIVE_MEM_MMU_BASE scalar_processor_2400_dmem
1992 #define HIVE_ADDR_MMU_BASE 0x24
1993 #define HIVE_SIZE_MMU_BASE 8
1997 #define HIVE_MEM_sp_MMU_BASE scalar_processor_2400_dmem
1998 #define HIVE_ADDR_sp_MMU_BASE 0x24
1999 #define HIVE_SIZE_sp_MMU_BASE 8
2002 /* function ia_css_dmaproxy_sp_channel_release: 34B8 */
2004 /* function ia_css_dmaproxy_sp_channel_release: 36AC */
2008 /* function ia_css_dmaproxy_sp_is_idle: 3498 */
2010 /* function ia_css_dmaproxy_sp_is_idle: 368C */
2013 #ifndef HIVE_MULTIPLE_PROGRAMS
2014 #ifndef HIVE_MEM_sem_for_qos_start
2015 #define HIVE_MEM_sem_for_qos_start scalar_processor_2400_dmem
2017 #define HIVE_ADDR_sem_for_qos_start 0x477C
2019 #define HIVE_ADDR_sem_for_qos_start 0x47C4
2021 #define HIVE_SIZE_sem_for_qos_start 20
2025 #define HIVE_MEM_sp_sem_for_qos_start scalar_processor_2400_dmem
2027 #define HIVE_ADDR_sp_sem_for_qos_start 0x477C
2029 #define HIVE_ADDR_sp_sem_for_qos_start 0x47C4
2031 #define HIVE_SIZE_sp_sem_for_qos_start 20
2034 /* function isp_hmem_load: B55 */
2036 /* function isp_hmem_load: B4F */
2040 /* function ia_css_tagger_sp_release_buf_elem: 1FD0 */
2042 /* function ia_css_tagger_sp_release_buf_elem: 2020 */
2046 /* function ia_css_eventq_sp_send: 350E */
2048 /* function ia_css_eventq_sp_send: 3702 */
2051 #ifndef HIVE_MULTIPLE_PROGRAMS
2052 #ifndef HIVE_MEM_ia_css_isys_sp_error_cnt
2053 #define HIVE_MEM_ia_css_isys_sp_error_cnt scalar_processor_2400_dmem
2055 #define HIVE_ADDR_ia_css_isys_sp_error_cnt 0x62D4
2057 #define HIVE_ADDR_ia_css_isys_sp_error_cnt 0x6330
2059 #define HIVE_SIZE_ia_css_isys_sp_error_cnt 16
2063 #define HIVE_MEM_sp_ia_css_isys_sp_error_cnt scalar_processor_2400_dmem
2065 #define HIVE_ADDR_sp_ia_css_isys_sp_error_cnt 0x62D4
2067 #define HIVE_ADDR_sp_ia_css_isys_sp_error_cnt 0x6330
2069 #define HIVE_SIZE_sp_ia_css_isys_sp_error_cnt 16
2072 /* function ia_css_tagger_buf_sp_unlock_from_start: 2ABE */
2074 /* function ia_css_tagger_buf_sp_unlock_from_start: 2C60 */
2077 #ifndef HIVE_MULTIPLE_PROGRAMS
2078 #ifndef HIVE_MEM_debug_buffer_ddr_address
2079 #define HIVE_MEM_debug_buffer_ddr_address scalar_processor_2400_dmem
2080 #define HIVE_ADDR_debug_buffer_ddr_address 0xBC
2081 #define HIVE_SIZE_debug_buffer_ddr_address 4
2085 #define HIVE_MEM_sp_debug_buffer_ddr_address scalar_processor_2400_dmem
2086 #define HIVE_ADDR_sp_debug_buffer_ddr_address 0xBC
2087 #define HIVE_SIZE_sp_debug_buffer_ddr_address 4
2090 /* function sp_isys_copy_request: 714 */
2092 /* function sp_isys_copy_request: 6A8 */
2096 /* function ia_css_rmgr_sp_refcount_retain_vbuf: 635D */
2098 /* function ia_css_rmgr_sp_refcount_retain_vbuf: 6498 */
2102 /* function ia_css_thread_sp_set_priority: CCE */
2104 /* function ia_css_thread_sp_set_priority: CC3 */
2108 /* function sizeof_hmem: BFC */
2110 /* function sizeof_hmem: BF6 */
2114 /* function tmpmem_release_dmem: 6569 */
2116 /* function tmpmem_release_dmem: 66A4 */
2119 /* function cnd_input_system_cfg: 392 */
2122 /* function __ia_css_sp_rawcopy_func_critical: 6F65 */
2124 /* function __ia_css_sp_rawcopy_func_critical: 70C2 */
2128 /* function ia_css_dmaproxy_sp_set_width_exception: 331D */
2130 /* function __ia_css_dmaproxy_sp_process_text: 331F */
2134 /* function sp_event_assert: 8B1 */
2136 /* function ia_css_dmaproxy_sp_set_width_exception: 3511 */
2140 /* function ia_css_flash_sp_init_internal_params: 2CA9 */
2142 /* function sp_event_assert: 845 */
2146 /* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 29C4 */
2148 /* function ia_css_flash_sp_init_internal_params: 2E4B */
2152 /* function __modu: 68BB */
2154 /* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 2B66 */
2158 /* function ia_css_dmaproxy_sp_init_isp_vector: 31A2 */
2160 /* function __modu: 6A2E */
2162 /* function ia_css_dmaproxy_sp_init_isp_vector: 3381 */
2165 /* function isp_vamem_store: 0 */
2168 /* function ia_css_tagger_sp_set_copy_pipe: 2A48 */
2171 #ifndef HIVE_MULTIPLE_PROGRAMS
2172 #ifndef HIVE_MEM_GDC_BASE
2173 #define HIVE_MEM_GDC_BASE scalar_processor_2400_dmem
2174 #define HIVE_ADDR_GDC_BASE 0x44
2175 #define HIVE_SIZE_GDC_BASE 8
2179 #define HIVE_MEM_sp_GDC_BASE scalar_processor_2400_dmem
2180 #define HIVE_ADDR_sp_GDC_BASE 0x44
2181 #define HIVE_SIZE_sp_GDC_BASE 8
2184 /* function ia_css_queue_local_init: 4C27 */
2186 /* function ia_css_queue_local_init: 4E85 */
2190 /* function sp_event_proxy_callout_func: 6988 */
2192 /* function sp_event_proxy_callout_func: 6AFB */
2196 /* function qos_scheduler_schedule_stage: 65C1 */
2198 /* function qos_scheduler_schedule_stage: 670F */
2201 #ifndef HIVE_MULTIPLE_PROGRAMS
2202 #ifndef HIVE_MEM_ia_css_thread_sp_num_ready_threads
2203 #define HIVE_MEM_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem
2205 #define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x49E0
2207 #define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x4A40
2209 #define HIVE_SIZE_ia_css_thread_sp_num_ready_threads 4
2213 #define HIVE_MEM_sp_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem
2215 #define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x49E0
2217 #define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x4A40
2219 #define HIVE_SIZE_sp_ia_css_thread_sp_num_ready_threads 4
2221 #ifndef HIVE_MULTIPLE_PROGRAMS
2222 #ifndef HIVE_MEM_sp_threads_stack_size
2223 #define HIVE_MEM_sp_threads_stack_size scalar_processor_2400_dmem
2224 #define HIVE_ADDR_sp_threads_stack_size 0x180
2225 #define HIVE_SIZE_sp_threads_stack_size 28
2229 #define HIVE_MEM_sp_sp_threads_stack_size scalar_processor_2400_dmem
2230 #define HIVE_ADDR_sp_sp_threads_stack_size 0x180
2231 #define HIVE_SIZE_sp_sp_threads_stack_size 28
2234 /* function ia_css_ispctrl_sp_isp_done_row_striping: 3F48 */
2236 /* function ia_css_ispctrl_sp_isp_done_row_striping: 418B */
2240 /* function __ia_css_isys_sp_isr_text: 5E22 */
2242 /* function __ia_css_isys_sp_isr_text: 5F5D */
2246 /* function ia_css_queue_dequeue: 4AA5 */
2248 /* function ia_css_queue_dequeue: 4D03 */
2252 /* function ia_css_dmaproxy_sp_configure_channel: 6E4C */
2254 /* function is_qos_standalone_mode: 66EA */
2256 /* function ia_css_dmaproxy_sp_configure_channel: 6F90 */
2259 #ifndef HIVE_MULTIPLE_PROGRAMS
2260 #ifndef HIVE_MEM_current_thread_fiber_sp
2261 #define HIVE_MEM_current_thread_fiber_sp scalar_processor_2400_dmem
2263 #define HIVE_ADDR_current_thread_fiber_sp 0x49E8
2265 #define HIVE_ADDR_current_thread_fiber_sp 0x4A44
2267 #define HIVE_SIZE_current_thread_fiber_sp 4
2271 #define HIVE_MEM_sp_current_thread_fiber_sp scalar_processor_2400_dmem
2273 #define HIVE_ADDR_sp_current_thread_fiber_sp 0x49E8
2275 #define HIVE_ADDR_sp_current_thread_fiber_sp 0x4A44
2277 #define HIVE_SIZE_sp_current_thread_fiber_sp 4
2280 /* function ia_css_circbuf_pop: FD8 */
2282 /* function ia_css_circbuf_pop: FCD */
2286 /* function memset: 693A */
2288 /* function memset: 6AAD */
2291 /* function irq_raise_set_token: B6 */
2293 #ifndef HIVE_MULTIPLE_PROGRAMS
2294 #ifndef HIVE_MEM_GPIO_BASE
2295 #define HIVE_MEM_GPIO_BASE scalar_processor_2400_dmem
2296 #define HIVE_ADDR_GPIO_BASE 0x3C
2297 #define HIVE_SIZE_GPIO_BASE 4
2301 #define HIVE_MEM_sp_GPIO_BASE scalar_processor_2400_dmem
2302 #define HIVE_ADDR_sp_GPIO_BASE 0x3C
2303 #define HIVE_SIZE_sp_GPIO_BASE 4
2306 /* function ia_css_pipeline_acc_stage_enable: 17F0 */
2308 /* function ia_css_pipeline_acc_stage_enable: 1818 */
2312 /* function ia_css_tagger_sp_unlock_exp_id: 2041 */
2314 /* function ia_css_tagger_sp_unlock_exp_id: 2091 */
2317 #ifndef HIVE_MULTIPLE_PROGRAMS
2318 #ifndef HIVE_MEM_isp_ph
2319 #define HIVE_MEM_isp_ph scalar_processor_2400_dmem
2321 #define HIVE_ADDR_isp_ph 0x62E4
2323 #define HIVE_ADDR_isp_ph 0x6340
2325 #define HIVE_SIZE_isp_ph 28
2329 #define HIVE_MEM_sp_isp_ph scalar_processor_2400_dmem
2331 #define HIVE_ADDR_sp_isp_ph 0x62E4
2333 #define HIVE_ADDR_sp_isp_ph 0x6340
2335 #define HIVE_SIZE_sp_isp_ph 28
2338 /* function ia_css_isys_sp_token_map_flush: 6022 */
2340 /* function ia_css_isys_sp_token_map_flush: 615D */
2344 /* function ia_css_ispctrl_sp_init_ds: 37CB */
2346 /* function ia_css_ispctrl_sp_init_ds: 39FA */
2350 /* function get_xmem_base_addr_raw: 3B78 */
2352 /* function get_xmem_base_addr_raw: 3DB3 */
2355 #ifndef HIVE_MULTIPLE_PROGRAMS
2356 #ifndef HIVE_MEM_sp_all_cbs_param
2357 #define HIVE_MEM_sp_all_cbs_param scalar_processor_2400_dmem
2359 #define HIVE_ADDR_sp_all_cbs_param 0x4790
2361 #define HIVE_ADDR_sp_all_cbs_param 0x47D8
2363 #define HIVE_SIZE_sp_all_cbs_param 16
2367 #define HIVE_MEM_sp_sp_all_cbs_param scalar_processor_2400_dmem
2369 #define HIVE_ADDR_sp_sp_all_cbs_param 0x4790
2371 #define HIVE_ADDR_sp_sp_all_cbs_param 0x47D8
2373 #define HIVE_SIZE_sp_sp_all_cbs_param 16
2376 /* function ia_css_circbuf_create: 1026 */
2378 /* function ia_css_circbuf_create: 101B */
2381 #ifndef HIVE_MULTIPLE_PROGRAMS
2382 #ifndef HIVE_MEM_sem_for_sp_group
2383 #define HIVE_MEM_sem_for_sp_group scalar_processor_2400_dmem
2385 #define HIVE_ADDR_sem_for_sp_group 0x47A0
2387 #define HIVE_ADDR_sem_for_sp_group 0x47E8
2389 #define HIVE_SIZE_sem_for_sp_group 20
2393 #define HIVE_MEM_sp_sem_for_sp_group scalar_processor_2400_dmem
2395 #define HIVE_ADDR_sp_sem_for_sp_group 0x47A0
2397 #define HIVE_ADDR_sp_sem_for_sp_group 0x47E8
2399 #define HIVE_SIZE_sp_sem_for_sp_group 20
2402 /* function ia_css_framebuf_sp_wait_for_in_frame: 64F8 */
2404 /* function __ia_css_dmaproxy_sp_configure_channel_text: 34F0 */
2406 /* function ia_css_framebuf_sp_wait_for_in_frame: 6633 */
2410 /* function ia_css_sp_rawcopy_tag_frame: 5588 */
2412 /* function ia_css_sp_rawcopy_tag_frame: 57C9 */
2416 /* function isp_hmem_clear: B25 */
2418 /* function isp_hmem_clear: B1F */
2422 /* function ia_css_framebuf_sp_release_in_frame: 653B */
2424 /* function ia_css_framebuf_sp_release_in_frame: 6676 */
2428 /* function ia_css_isys_sp_backend_snd_acquire_request: 5A78 */
2430 /* function ia_css_isys_sp_backend_snd_acquire_request: 5BB3 */
2434 /* function ia_css_isys_sp_token_map_is_full: 5EA9 */
2436 /* function ia_css_isys_sp_token_map_is_full: 5FE4 */
2440 /* function input_system_acquisition_run: AF9 */
2442 /* function input_system_acquisition_run: AF3 */
2446 /* function ia_css_ispctrl_sp_start_binary: 364A */
2448 /* function ia_css_ispctrl_sp_start_binary: 384C */
2451 #ifndef HIVE_MULTIPLE_PROGRAMS
2452 #ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs
2453 #define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem
2455 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x58F4
2457 #define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x5950
2459 #define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20
2463 #define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem
2465 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x58F4
2467 #define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x5950
2469 #define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20
2472 /* function ia_css_eventq_sp_recv: 34E0 */
2474 /* function ia_css_eventq_sp_recv: 36D4 */
2477 #ifndef HIVE_MULTIPLE_PROGRAMS
2478 #ifndef HIVE_MEM_isp_pool
2479 #define HIVE_MEM_isp_pool scalar_processor_2400_dmem
2481 #define HIVE_ADDR_isp_pool 0x2E8
2483 #define HIVE_ADDR_isp_pool 0x300
2485 #define HIVE_SIZE_isp_pool 4
2489 #define HIVE_MEM_sp_isp_pool scalar_processor_2400_dmem
2491 #define HIVE_ADDR_sp_isp_pool 0x2E8
2493 #define HIVE_ADDR_sp_isp_pool 0x300
2495 #define HIVE_SIZE_sp_isp_pool 4
2498 /* function ia_css_rmgr_sp_rel_gen: 622A */
2500 /* function ia_css_rmgr_sp_rel_gen: 6365 */
2502 /* function ia_css_tagger_sp_unblock_clients: 2919 */
2506 /* function css_get_frame_processing_time_end: 1FC0 */
2508 /* function css_get_frame_processing_time_end: 2010 */
2511 #ifndef HIVE_MULTIPLE_PROGRAMS
2512 #ifndef HIVE_MEM_event_any_pending_mask
2513 #define HIVE_MEM_event_any_pending_mask scalar_processor_2400_dmem
2515 #define HIVE_ADDR_event_any_pending_mask 0x300
2517 #define HIVE_ADDR_event_any_pending_mask 0x318
2519 #define HIVE_SIZE_event_any_pending_mask 8
2523 #define HIVE_MEM_sp_event_any_pending_mask scalar_processor_2400_dmem
2525 #define HIVE_ADDR_sp_event_any_pending_mask 0x300
2527 #define HIVE_ADDR_sp_event_any_pending_mask 0x318
2529 #define HIVE_SIZE_sp_event_any_pending_mask 8
2532 /* function ia_css_isys_sp_backend_push: 5A2F */
2534 /* function ia_css_isys_sp_backend_push: 5B6A */
2537 /* function sh_css_decode_tag_descr: 352 */
2539 /* function debug_enqueue_isp: 27B */
2542 /* function qos_scheduler_update_stage_budget: 65AF */
2544 /* function qos_scheduler_update_stage_budget: 66F2 */
2548 /* function ia_css_spctrl_sp_uninit: 596A */
2550 /* function ia_css_spctrl_sp_uninit: 5AA5 */
2553 #ifndef HIVE_MULTIPLE_PROGRAMS
2554 #ifndef HIVE_MEM_HIVE_IF_SWITCH_CODE
2555 #define HIVE_MEM_HIVE_IF_SWITCH_CODE scalar_processor_2400_dmem
2556 #define HIVE_ADDR_HIVE_IF_SWITCH_CODE 0x1D8
2557 #define HIVE_SIZE_HIVE_IF_SWITCH_CODE 4
2561 #define HIVE_MEM_sp_HIVE_IF_SWITCH_CODE scalar_processor_2400_dmem
2562 #define HIVE_ADDR_sp_HIVE_IF_SWITCH_CODE 0x1D8
2563 #define HIVE_SIZE_sp_HIVE_IF_SWITCH_CODE 4
2565 #ifndef HIVE_MULTIPLE_PROGRAMS
2566 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs
2567 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem
2569 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x5908
2571 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x5964
2573 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_dis_bufs 140
2577 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem
2579 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x5908
2581 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x5964
2583 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_dis_bufs 140
2586 /* function ia_css_tagger_buf_sp_lock_from_start: 2AF2 */
2588 /* function ia_css_tagger_buf_sp_lock_from_start: 2C94 */
2591 #ifndef HIVE_MULTIPLE_PROGRAMS
2592 #ifndef HIVE_MEM_sem_for_isp_idle
2593 #define HIVE_MEM_sem_for_isp_idle scalar_processor_2400_dmem
2595 #define HIVE_ADDR_sem_for_isp_idle 0x47B4
2597 #define HIVE_ADDR_sem_for_isp_idle 0x47FC
2599 #define HIVE_SIZE_sem_for_isp_idle 20
2603 #define HIVE_MEM_sp_sem_for_isp_idle scalar_processor_2400_dmem
2605 #define HIVE_ADDR_sp_sem_for_isp_idle 0x47B4
2607 #define HIVE_ADDR_sp_sem_for_isp_idle 0x47FC
2609 #define HIVE_SIZE_sp_sem_for_isp_idle 20
2612 /* function ia_css_dmaproxy_sp_write_byte_addr: 31FF */
2614 /* function ia_css_dmaproxy_sp_write_byte_addr: 33DE */
2618 /* function ia_css_dmaproxy_sp_init: 3176 */
2620 /* function ia_css_dmaproxy_sp_init: 3355 */
2624 /* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 2D7B */
2626 /* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 2F1D */
2629 #ifndef HIVE_MULTIPLE_PROGRAMS
2630 #ifndef HIVE_MEM_ISP_VAMEM_BASE
2631 #define HIVE_MEM_ISP_VAMEM_BASE scalar_processor_2400_dmem
2632 #define HIVE_ADDR_ISP_VAMEM_BASE 0x14
2633 #define HIVE_SIZE_ISP_VAMEM_BASE 12
2637 #define HIVE_MEM_sp_ISP_VAMEM_BASE scalar_processor_2400_dmem
2638 #define HIVE_ADDR_sp_ISP_VAMEM_BASE 0x14
2639 #define HIVE_SIZE_sp_ISP_VAMEM_BASE 12
2641 #ifndef HIVE_MULTIPLE_PROGRAMS
2642 #ifndef HIVE_MEM_ia_css_rawcopy_sp_tagger
2643 #define HIVE_MEM_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem
2645 #define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x6294
2647 #define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x62F0
2649 #define HIVE_SIZE_ia_css_rawcopy_sp_tagger 24
2653 #define HIVE_MEM_sp_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem
2655 #define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x6294
2657 #define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x62F0
2659 #define HIVE_SIZE_sp_ia_css_rawcopy_sp_tagger 24
2661 #ifndef HIVE_MULTIPLE_PROGRAMS
2662 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids
2663 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem
2665 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x5994
2667 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x59F0
2669 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_exp_ids 70
2673 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem
2675 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x5994
2677 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x59F0
2679 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_exp_ids 70
2682 /* function ia_css_queue_item_load: 4D19 */
2684 /* function ia_css_queue_item_load: 4F77 */
2688 /* function ia_css_spctrl_sp_get_state: 5955 */
2690 /* function ia_css_spctrl_sp_get_state: 5A90 */
2694 /* function ia_css_isys_sp_token_map_uninit: 603F */
2696 /* function ia_css_isys_sp_token_map_uninit: 617A */
2699 #ifndef HIVE_MULTIPLE_PROGRAMS
2700 #ifndef HIVE_MEM_callout_sp_thread
2701 #define HIVE_MEM_callout_sp_thread scalar_processor_2400_dmem
2703 #define HIVE_ADDR_callout_sp_thread 0x49DC
2705 #define HIVE_ADDR_callout_sp_thread 0x1E0
2707 #define HIVE_SIZE_callout_sp_thread 4
2711 #define HIVE_MEM_sp_callout_sp_thread scalar_processor_2400_dmem
2713 #define HIVE_ADDR_sp_callout_sp_thread 0x49DC
2715 #define HIVE_ADDR_sp_callout_sp_thread 0x1E0
2717 #define HIVE_SIZE_sp_callout_sp_thread 4
2720 /* function thread_fiber_sp_init: E2F */
2722 /* function thread_fiber_sp_init: E24 */
2725 #ifndef HIVE_MULTIPLE_PROGRAMS
2726 #ifndef HIVE_MEM_SP_PMEM_BASE
2727 #define HIVE_MEM_SP_PMEM_BASE scalar_processor_2400_dmem
2728 #define HIVE_ADDR_SP_PMEM_BASE 0x0
2729 #define HIVE_SIZE_SP_PMEM_BASE 4
2733 #define HIVE_MEM_sp_SP_PMEM_BASE scalar_processor_2400_dmem
2734 #define HIVE_ADDR_sp_SP_PMEM_BASE 0x0
2735 #define HIVE_SIZE_sp_SP_PMEM_BASE 4
2738 /* function ia_css_isys_sp_token_map_snd_acquire_req: 5FAF */
2740 /* function ia_css_isys_sp_token_map_snd_acquire_req: 60EA */
2743 #ifndef HIVE_MULTIPLE_PROGRAMS
2744 #ifndef HIVE_MEM_sp_isp_input_stream_format
2745 #define HIVE_MEM_sp_isp_input_stream_format scalar_processor_2400_dmem
2747 #define HIVE_ADDR_sp_isp_input_stream_format 0x40F8
2749 #define HIVE_ADDR_sp_isp_input_stream_format 0x4118
2751 #define HIVE_SIZE_sp_isp_input_stream_format 20
2755 #define HIVE_MEM_sp_sp_isp_input_stream_format scalar_processor_2400_dmem
2757 #define HIVE_ADDR_sp_sp_isp_input_stream_format 0x40F8
2759 #define HIVE_ADDR_sp_sp_isp_input_stream_format 0x4118
2761 #define HIVE_SIZE_sp_sp_isp_input_stream_format 20
2764 /* function __mod: 68A7 */
2766 /* function __mod: 6A1A */
2770 /* function ia_css_dmaproxy_sp_init_dmem_channel: 3260 */
2772 /* function ia_css_dmaproxy_sp_init_dmem_channel: 343F */
2776 /* function ia_css_thread_sp_join: CFF */
2778 /* function ia_css_thread_sp_join: CF4 */
2782 /* function ia_css_dmaproxy_sp_add_command: 6F4F */
2784 /* function ia_css_dmaproxy_sp_add_command: 7082 */
2788 /* function ia_css_sp_metadata_thread_func: 5809 */
2790 /* function ia_css_sp_metadata_thread_func: 5968 */
2794 /* function __sp_event_proxy_func_critical: 6975 */
2796 /* function __sp_event_proxy_func_critical: 6AE8 */
2800 /* function ia_css_sp_metadata_wait: 591C */
2802 /* function ia_css_sp_metadata_wait: 5A57 */
2806 /* function ia_css_circbuf_peek_from_start: F08 */
2808 /* function ia_css_circbuf_peek_from_start: EFD */
2812 /* function ia_css_event_sp_encode: 356B */
2814 /* function ia_css_event_sp_encode: 375F */
2818 /* function ia_css_thread_sp_run: D72 */
2820 /* function ia_css_thread_sp_run: D67 */
2824 /* function sp_isys_copy_func: 6F6 */
2826 /* function sp_isys_copy_func: 68A */
2830 /* function ia_css_isys_sp_backend_flush: 5A98 */
2832 /* function ia_css_isys_sp_backend_flush: 5BD3 */
2836 /* function ia_css_isys_sp_backend_frame_exists: 59B4 */
2838 /* function ia_css_isys_sp_backend_frame_exists: 5AEF */
2842 /* function ia_css_sp_isp_param_init_isp_memories: 47A2 */
2844 /* function ia_css_sp_isp_param_init_isp_memories: 4A2A */
2848 /* function register_isr: 8A9 */
2850 /* function register_isr: 83D */
2853 /* function irq_raise: C8 */
2856 /* function ia_css_dmaproxy_sp_mmu_invalidate: 313D */
2858 /* function ia_css_dmaproxy_sp_mmu_invalidate: 32E5 */
2861 #ifndef HIVE_MULTIPLE_PROGRAMS
2862 #ifndef HIVE_MEM_HIVE_IF_SRST_ADDRESS
2863 #define HIVE_MEM_HIVE_IF_SRST_ADDRESS scalar_processor_2400_dmem
2864 #define HIVE_ADDR_HIVE_IF_SRST_ADDRESS 0x1B8
2865 #define HIVE_SIZE_HIVE_IF_SRST_ADDRESS 16
2869 #define HIVE_MEM_sp_HIVE_IF_SRST_ADDRESS scalar_processor_2400_dmem
2870 #define HIVE_ADDR_sp_HIVE_IF_SRST_ADDRESS 0x1B8
2871 #define HIVE_SIZE_sp_HIVE_IF_SRST_ADDRESS 16
2874 /* function pipeline_sp_initialize_stage: 1924 */
2876 /* function pipeline_sp_initialize_stage: 195E */
2879 #ifndef HIVE_MULTIPLE_PROGRAMS
2880 #ifndef HIVE_MEM_ia_css_isys_sp_frontend_states
2881 #define HIVE_MEM_ia_css_isys_sp_frontend_states scalar_processor_2400_dmem
2883 #define HIVE_ADDR_ia_css_isys_sp_frontend_states 0x62C8
2885 #define HIVE_ADDR_ia_css_isys_sp_frontend_states 0x6324
2887 #define HIVE_SIZE_ia_css_isys_sp_frontend_states 12
2891 #define HIVE_MEM_sp_ia_css_isys_sp_frontend_states scalar_processor_2400_dmem
2893 #define HIVE_ADDR_sp_ia_css_isys_sp_frontend_states 0x62C8
2895 #define HIVE_ADDR_sp_ia_css_isys_sp_frontend_states 0x6324
2897 #define HIVE_SIZE_sp_ia_css_isys_sp_frontend_states 12
2900 /* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6E1E */
2902 /* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6F62 */
2906 /* function ia_css_ispctrl_sp_done_ds: 37B2 */
2908 /* function ia_css_ispctrl_sp_done_ds: 39E1 */
2912 /* function ia_css_sp_isp_param_get_mem_inits: 477D */
2914 /* function ia_css_sp_isp_param_get_mem_inits: 4A05 */
2918 /* function ia_css_parambuf_sp_init_buffer_queues: 13D0 */
2920 /* function ia_css_parambuf_sp_init_buffer_queues: 13F1 */
2923 #ifndef HIVE_MULTIPLE_PROGRAMS
2924 #ifndef HIVE_MEM_vbuf_pfp_spref
2925 #define HIVE_MEM_vbuf_pfp_spref scalar_processor_2400_dmem
2927 #define HIVE_ADDR_vbuf_pfp_spref 0x2F0
2929 #define HIVE_ADDR_vbuf_pfp_spref 0x308
2931 #define HIVE_SIZE_vbuf_pfp_spref 4
2935 #define HIVE_MEM_sp_vbuf_pfp_spref scalar_processor_2400_dmem
2937 #define HIVE_ADDR_sp_vbuf_pfp_spref 0x2F0
2939 #define HIVE_ADDR_sp_vbuf_pfp_spref 0x308
2941 #define HIVE_SIZE_sp_vbuf_pfp_spref 4
2944 /* function input_system_cfg: ABB */
2946 /* function input_system_cfg: AB5 */
2949 #ifndef HIVE_MULTIPLE_PROGRAMS
2950 #ifndef HIVE_MEM_ISP_HMEM_BASE
2951 #define HIVE_MEM_ISP_HMEM_BASE scalar_processor_2400_dmem
2952 #define HIVE_ADDR_ISP_HMEM_BASE 0x20
2953 #define HIVE_SIZE_ISP_HMEM_BASE 4
2957 #define HIVE_MEM_sp_ISP_HMEM_BASE scalar_processor_2400_dmem
2958 #define HIVE_ADDR_sp_ISP_HMEM_BASE 0x20
2959 #define HIVE_SIZE_sp_ISP_HMEM_BASE 4
2961 #ifndef HIVE_MULTIPLE_PROGRAMS
2962 #ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_frames
2963 #define HIVE_MEM_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem
2965 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x59DC
2967 #define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x5A38
2969 #define HIVE_SIZE_ia_css_bufq_sp_pipe_private_frames 280
2973 #define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem
2975 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x59DC
2977 #define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x5A38
2979 #define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_frames 280
2982 /* function qos_scheduler_init_stage_budget: 65E8 */
2984 /* function qos_scheduler_init_stage_budget: 6750 */
2988 /* function ia_css_isys_sp_backend_release: 5B0D */
2990 /* function ia_css_isys_sp_backend_release: 5C48 */
2994 /* function ia_css_isys_sp_backend_destroy: 5B37 */
2996 /* function ia_css_isys_sp_backend_destroy: 5C72 */
2999 #ifndef HIVE_MULTIPLE_PROGRAMS
3000 #ifndef HIVE_MEM_sp2host_buffer_queue_handle
3001 #define HIVE_MEM_sp2host_buffer_queue_handle scalar_processor_2400_dmem
3003 #define HIVE_ADDR_sp2host_buffer_queue_handle 0x5AF4
3005 #define HIVE_ADDR_sp2host_buffer_queue_handle 0x5B50
3007 #define HIVE_SIZE_sp2host_buffer_queue_handle 96
3011 #define HIVE_MEM_sp_sp2host_buffer_queue_handle scalar_processor_2400_dmem
3013 #define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x5AF4
3015 #define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x5B50
3017 #define HIVE_SIZE_sp_sp2host_buffer_queue_handle 96
3020 /* function ia_css_isys_sp_token_map_check_mipi_frame_size: 5F73 */
3022 /* function ia_css_isys_sp_token_map_check_mipi_frame_size: 60AE */
3026 /* function ia_css_ispctrl_sp_init_isp_vars: 449C */
3028 /* function ia_css_ispctrl_sp_init_isp_vars: 46F7 */
3032 /* function ia_css_isys_sp_frontend_has_empty_mipi_buffer_cb: 5B89 */
3034 /* function ia_css_isys_sp_frontend_has_empty_mipi_buffer_cb: 5CC4 */
3038 /* function sp_warning: 8DC */
3040 /* function sp_warning: 870 */
3044 /* function ia_css_rmgr_sp_vbuf_enqueue: 631D */
3046 /* function ia_css_rmgr_sp_vbuf_enqueue: 6458 */
3050 /* function ia_css_tagger_sp_tag_exp_id: 215B */
3052 /* function ia_css_tagger_sp_tag_exp_id: 21AB */
3056 /* function ia_css_dmaproxy_sp_write: 3216 */
3058 /* function ia_css_dmaproxy_sp_write: 33F5 */
3062 /* function ia_css_parambuf_sp_release_in_param: 1250 */
3064 /* function ia_css_parambuf_sp_release_in_param: 1245 */
3067 #ifndef HIVE_MULTIPLE_PROGRAMS
3068 #ifndef HIVE_MEM_irq_sw_interrupt_token
3069 #define HIVE_MEM_irq_sw_interrupt_token scalar_processor_2400_dmem
3071 #define HIVE_ADDR_irq_sw_interrupt_token 0x40F4
3073 #define HIVE_ADDR_irq_sw_interrupt_token 0x4114
3075 #define HIVE_SIZE_irq_sw_interrupt_token 4
3079 #define HIVE_MEM_sp_irq_sw_interrupt_token scalar_processor_2400_dmem
3081 #define HIVE_ADDR_sp_irq_sw_interrupt_token 0x40F4
3083 #define HIVE_ADDR_sp_irq_sw_interrupt_token 0x4114
3085 #define HIVE_SIZE_sp_irq_sw_interrupt_token 4
3087 #ifndef HIVE_MULTIPLE_PROGRAMS
3088 #ifndef HIVE_MEM_sp_isp_addresses
3089 #define HIVE_MEM_sp_isp_addresses scalar_processor_2400_dmem
3091 #define HIVE_ADDR_sp_isp_addresses 0x5F44
3093 #define HIVE_ADDR_sp_isp_addresses 0x5FA4
3095 #define HIVE_SIZE_sp_isp_addresses 172
3099 #define HIVE_MEM_sp_sp_isp_addresses scalar_processor_2400_dmem
3101 #define HIVE_ADDR_sp_sp_isp_addresses 0x5F44
3103 #define HIVE_ADDR_sp_sp_isp_addresses 0x5FA4
3105 #define HIVE_SIZE_sp_sp_isp_addresses 172
3108 /* function ia_css_rmgr_sp_acq_gen: 6242 */
3110 /* function ia_css_rmgr_sp_acq_gen: 637D */
3114 /* function receiver_reg_load: AD0 */
3116 /* function receiver_reg_load: ACA */
3119 #ifndef HIVE_MULTIPLE_PROGRAMS
3120 #ifndef HIVE_MEM_isps
3121 #define HIVE_MEM_isps scalar_processor_2400_dmem
3123 #define HIVE_ADDR_isps 0x6300
3125 #define HIVE_ADDR_isps 0x635C
3127 #define HIVE_SIZE_isps 28
3131 #define HIVE_MEM_sp_isps scalar_processor_2400_dmem
3133 #define HIVE_ADDR_sp_isps 0x6300
3135 #define HIVE_ADDR_sp_isps 0x635C
3137 #define HIVE_SIZE_sp_isps 28
3139 #ifndef HIVE_MULTIPLE_PROGRAMS
3140 #ifndef HIVE_MEM_host_sp_queues_initialized
3141 #define HIVE_MEM_host_sp_queues_initialized scalar_processor_2400_dmem
3143 #define HIVE_ADDR_host_sp_queues_initialized 0x410C
3145 #define HIVE_ADDR_host_sp_queues_initialized 0x412C
3147 #define HIVE_SIZE_host_sp_queues_initialized 4
3151 #define HIVE_MEM_sp_host_sp_queues_initialized scalar_processor_2400_dmem
3153 #define HIVE_ADDR_sp_host_sp_queues_initialized 0x410C
3155 #define HIVE_ADDR_sp_host_sp_queues_initialized 0x412C
3157 #define HIVE_SIZE_sp_host_sp_queues_initialized 4
3160 /* function ia_css_queue_uninit: 4BE5 */
3162 /* function ia_css_queue_uninit: 4E43 */
3165 #ifndef HIVE_MULTIPLE_PROGRAMS
3166 #ifndef HIVE_MEM_ia_css_ispctrl_sp_isp_started
3167 #define HIVE_MEM_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem
3169 #define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x5BFC
3171 #define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x5C58
3173 #define HIVE_SIZE_ia_css_ispctrl_sp_isp_started 4
3177 #define HIVE_MEM_sp_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem
3179 #define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x5BFC
3181 #define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x5C58
3183 #define HIVE_SIZE_sp_ia_css_ispctrl_sp_isp_started 4
3186 /* function ia_css_bufq_sp_release_dynamic_buf: 2DE7 */
3188 /* function ia_css_bufq_sp_release_dynamic_buf: 2F89 */
3192 /* function ia_css_dmaproxy_sp_set_height_exception: 330E */
3194 /* function ia_css_dmaproxy_sp_set_height_exception: 3502 */
3198 /* function ia_css_dmaproxy_sp_init_vmem_channel: 3293 */
3200 /* function ia_css_dmaproxy_sp_init_vmem_channel: 3473 */
3204 #ifndef HIVE_MULTIPLE_PROGRAMS
3205 #ifndef HIVE_MEM_num_ready_threads
3206 #define HIVE_MEM_num_ready_threads scalar_processor_2400_dmem
3207 #define HIVE_ADDR_num_ready_threads 0x49E4
3208 #define HIVE_SIZE_num_ready_threads 4
3212 #define HIVE_MEM_sp_num_ready_threads scalar_processor_2400_dmem
3213 #define HIVE_ADDR_sp_num_ready_threads 0x49E4
3214 #define HIVE_SIZE_sp_num_ready_threads 4
3216 /* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 31E8 */
3218 /* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 33C7 */
3221 #ifndef HIVE_MULTIPLE_PROGRAMS
3222 #ifndef HIVE_MEM_vbuf_spref
3223 #define HIVE_MEM_vbuf_spref scalar_processor_2400_dmem
3225 #define HIVE_ADDR_vbuf_spref 0x2EC
3227 #define HIVE_ADDR_vbuf_spref 0x304
3229 #define HIVE_SIZE_vbuf_spref 4
3233 #define HIVE_MEM_sp_vbuf_spref scalar_processor_2400_dmem
3235 #define HIVE_ADDR_sp_vbuf_spref 0x2EC
3237 #define HIVE_ADDR_sp_vbuf_spref 0x304
3239 #define HIVE_SIZE_sp_vbuf_spref 4
3241 #ifndef HIVE_MULTIPLE_PROGRAMS
3242 #ifndef HIVE_MEM_sp_metadata_thread
3243 #define HIVE_MEM_sp_metadata_thread scalar_processor_2400_dmem
3245 #define HIVE_ADDR_sp_metadata_thread 0x4998
3246 #define HIVE_SIZE_sp_metadata_thread 68
3248 #define HIVE_ADDR_sp_metadata_thread 0x49F8
3249 #define HIVE_SIZE_sp_metadata_thread 72
3254 #define HIVE_MEM_sp_sp_metadata_thread scalar_processor_2400_dmem
3256 #define HIVE_ADDR_sp_sp_metadata_thread 0x4998
3257 #define HIVE_SIZE_sp_sp_metadata_thread 68
3259 #define HIVE_ADDR_sp_sp_metadata_thread 0x49F8
3260 #define HIVE_SIZE_sp_sp_metadata_thread 72
3264 /* function ia_css_queue_enqueue: 4B2F */
3266 /* function ia_css_queue_enqueue: 4D8D */
3269 #ifndef HIVE_MULTIPLE_PROGRAMS
3270 #ifndef HIVE_MEM_ia_css_flash_sp_request
3271 #define HIVE_MEM_ia_css_flash_sp_request scalar_processor_2400_dmem
3273 #define HIVE_ADDR_ia_css_flash_sp_request 0x4A98
3275 #define HIVE_ADDR_ia_css_flash_sp_request 0x4AF4
3277 #define HIVE_SIZE_ia_css_flash_sp_request 4
3281 #define HIVE_MEM_sp_ia_css_flash_sp_request scalar_processor_2400_dmem
3283 #define HIVE_ADDR_sp_ia_css_flash_sp_request 0x4A98
3285 #define HIVE_ADDR_sp_ia_css_flash_sp_request 0x4AF4
3287 #define HIVE_SIZE_sp_ia_css_flash_sp_request 4
3290 /* function ia_css_dmaproxy_sp_vmem_write: 31B9 */
3292 /* function ia_css_dmaproxy_sp_vmem_write: 3398 */
3295 #ifndef HIVE_MULTIPLE_PROGRAMS
3296 #ifndef HIVE_MEM_tagger_frames
3297 #define HIVE_MEM_tagger_frames scalar_processor_2400_dmem
3299 #define HIVE_ADDR_tagger_frames 0x49EC
3301 #define HIVE_ADDR_tagger_frames 0x4A48
3303 #define HIVE_SIZE_tagger_frames 168
3307 #define HIVE_MEM_sp_tagger_frames scalar_processor_2400_dmem
3309 #define HIVE_ADDR_sp_tagger_frames 0x49EC
3311 #define HIVE_ADDR_sp_tagger_frames 0x4A48
3313 #define HIVE_SIZE_sp_tagger_frames 168
3316 /* function ia_css_isys_sp_token_map_snd_capture_req: 5FD1 */
3318 /* function ia_css_isys_sp_token_map_snd_capture_req: 610C */
3321 #ifndef HIVE_MULTIPLE_PROGRAMS
3322 #ifndef HIVE_MEM_sem_for_reading_if
3323 #define HIVE_MEM_sem_for_reading_if scalar_processor_2400_dmem
3325 #define HIVE_ADDR_sem_for_reading_if 0x47C8
3327 #define HIVE_ADDR_sem_for_reading_if 0x4810
3329 #define HIVE_SIZE_sem_for_reading_if 20
3333 #define HIVE_MEM_sp_sem_for_reading_if scalar_processor_2400_dmem
3335 #define HIVE_ADDR_sp_sem_for_reading_if 0x47C8
3337 #define HIVE_ADDR_sp_sem_for_reading_if 0x4810
3339 #define HIVE_SIZE_sp_sem_for_reading_if 20
3342 /* function sp_generate_interrupts: 95B */
3344 /* function sp_generate_interrupts: 8EF */
3346 /* function ia_css_pipeline_sp_start: 1871 */
3350 /* function ia_css_pipeline_sp_start: 1837 */
3352 /* function ia_css_thread_default_callout: 6BE3 */
3356 /* function ia_css_sp_rawcopy_init: 510C */
3358 /* function ia_css_sp_rawcopy_init: 536A */
3362 /* function tmr_clock_read: 13F1 */
3364 /* function tmr_clock_read: 1412 */
3367 #ifndef HIVE_MULTIPLE_PROGRAMS
3368 #ifndef HIVE_MEM_ISP_BAMEM_BASE
3369 #define HIVE_MEM_ISP_BAMEM_BASE scalar_processor_2400_dmem
3371 #define HIVE_ADDR_ISP_BAMEM_BASE 0x2F8
3373 #define HIVE_ADDR_ISP_BAMEM_BASE 0x310
3375 #define HIVE_SIZE_ISP_BAMEM_BASE 4
3379 #define HIVE_MEM_sp_ISP_BAMEM_BASE scalar_processor_2400_dmem
3381 #define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x2F8
3383 #define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x310
3385 #define HIVE_SIZE_sp_ISP_BAMEM_BASE 4
3388 /* function ia_css_isys_sp_frontend_rcv_capture_ack: 5C38 */
3390 /* function ia_css_isys_sp_frontend_rcv_capture_ack: 5D73 */
3393 #ifndef HIVE_MULTIPLE_PROGRAMS
3394 #ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues
3395 #define HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem
3397 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5B54
3399 #define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5BB0
3401 #define HIVE_SIZE_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160
3405 #define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem
3407 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5B54
3409 #define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5BB0
3411 #define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160
3414 /* function css_get_frame_processing_time_start: 1FC8 */
3416 /* function css_get_frame_processing_time_start: 2018 */
3419 #ifndef HIVE_MULTIPLE_PROGRAMS
3420 #ifndef HIVE_MEM_sp_all_cbs_frame
3421 #define HIVE_MEM_sp_all_cbs_frame scalar_processor_2400_dmem
3423 #define HIVE_ADDR_sp_all_cbs_frame 0x47DC
3425 #define HIVE_ADDR_sp_all_cbs_frame 0x4824
3427 #define HIVE_SIZE_sp_all_cbs_frame 16
3431 #define HIVE_MEM_sp_sp_all_cbs_frame scalar_processor_2400_dmem
3433 #define HIVE_ADDR_sp_sp_all_cbs_frame 0x47DC
3435 #define HIVE_ADDR_sp_sp_all_cbs_frame 0x4824
3437 #define HIVE_SIZE_sp_sp_all_cbs_frame 16
3440 /* function thread_sp_queue_print: D8F */
3442 /* function thread_sp_queue_print: D84 */
3446 /* function sp_notify_eof: 907 */
3448 /* function sp_notify_eof: 89B */
3451 #ifndef HIVE_MULTIPLE_PROGRAMS
3452 #ifndef HIVE_MEM_sem_for_str2mem
3453 #define HIVE_MEM_sem_for_str2mem scalar_processor_2400_dmem
3455 #define HIVE_ADDR_sem_for_str2mem 0x47EC
3457 #define HIVE_ADDR_sem_for_str2mem 0x4834
3459 #define HIVE_SIZE_sem_for_str2mem 20
3463 #define HIVE_MEM_sp_sem_for_str2mem scalar_processor_2400_dmem
3465 #define HIVE_ADDR_sp_sem_for_str2mem 0x47EC
3467 #define HIVE_ADDR_sp_sem_for_str2mem 0x4834
3469 #define HIVE_SIZE_sp_sem_for_str2mem 20
3472 /* function ia_css_tagger_buf_sp_is_marked_from_start: 2B5A */
3474 /* function ia_css_tagger_buf_sp_is_marked_from_start: 2CFC */
3478 /* function ia_css_bufq_sp_acquire_dynamic_buf: 2F9F */
3480 /* function ia_css_bufq_sp_acquire_dynamic_buf: 3141 */
3484 /* function ia_css_circbuf_destroy: 101D */
3486 /* function ia_css_circbuf_destroy: 1012 */
3489 #ifndef HIVE_MULTIPLE_PROGRAMS
3490 #ifndef HIVE_MEM_ISP_PMEM_BASE
3491 #define HIVE_MEM_ISP_PMEM_BASE scalar_processor_2400_dmem
3492 #define HIVE_ADDR_ISP_PMEM_BASE 0xC
3493 #define HIVE_SIZE_ISP_PMEM_BASE 4
3497 #define HIVE_MEM_sp_ISP_PMEM_BASE scalar_processor_2400_dmem
3498 #define HIVE_ADDR_sp_ISP_PMEM_BASE 0xC
3499 #define HIVE_SIZE_sp_ISP_PMEM_BASE 4
3502 /* function ia_css_sp_isp_param_mem_load: 4710 */
3504 /* function ia_css_sp_isp_param_mem_load: 4998 */
3508 /* function ia_css_tagger_buf_sp_pop_from_start: 2946 */
3510 /* function ia_css_tagger_buf_sp_pop_from_start: 2AE8 */
3514 /* function __div: 685F */
3516 /* function __div: 69D2 */
3520 /* function ia_css_isys_sp_frontend_create: 5E09 */
3522 /* function ia_css_isys_sp_frontend_create: 5F44 */
3526 /* function ia_css_rmgr_sp_refcount_release_vbuf: 633C */
3528 /* function ia_css_rmgr_sp_refcount_release_vbuf: 6477 */
3531 #ifndef HIVE_MULTIPLE_PROGRAMS
3532 #ifndef HIVE_MEM_ia_css_flash_sp_in_use
3533 #define HIVE_MEM_ia_css_flash_sp_in_use scalar_processor_2400_dmem
3535 #define HIVE_ADDR_ia_css_flash_sp_in_use 0x4A9C
3537 #define HIVE_ADDR_ia_css_flash_sp_in_use 0x4AF8
3539 #define HIVE_SIZE_ia_css_flash_sp_in_use 4
3543 #define HIVE_MEM_sp_ia_css_flash_sp_in_use scalar_processor_2400_dmem
3545 #define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x4A9C
3547 #define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x4AF8
3549 #define HIVE_SIZE_sp_ia_css_flash_sp_in_use 4
3552 /* function ia_css_thread_sem_sp_wait: 6B42 */
3554 /* function ia_css_thread_sem_sp_wait: 6CB7 */
3557 #ifndef HIVE_MULTIPLE_PROGRAMS
3558 #ifndef HIVE_MEM_sp_sleep_mode
3559 #define HIVE_MEM_sp_sleep_mode scalar_processor_2400_dmem
3561 #define HIVE_ADDR_sp_sleep_mode 0x4110
3563 #define HIVE_ADDR_sp_sleep_mode 0x4130
3565 #define HIVE_SIZE_sp_sleep_mode 4
3569 #define HIVE_MEM_sp_sp_sleep_mode scalar_processor_2400_dmem
3571 #define HIVE_ADDR_sp_sp_sleep_mode 0x4110
3573 #define HIVE_ADDR_sp_sp_sleep_mode 0x4130
3575 #define HIVE_SIZE_sp_sp_sleep_mode 4
3578 /* function ia_css_tagger_buf_sp_push: 2A55 */
3580 /* function ia_css_tagger_buf_sp_push: 2BF7 */
3583 /* function mmu_invalidate_cache: D3 */
3585 #ifndef HIVE_MULTIPLE_PROGRAMS
3586 #ifndef HIVE_MEM_sp_max_cb_elems
3587 #define HIVE_MEM_sp_max_cb_elems scalar_processor_2400_dmem
3588 #define HIVE_ADDR_sp_max_cb_elems 0x148
3589 #define HIVE_SIZE_sp_max_cb_elems 8
3593 #define HIVE_MEM_sp_sp_max_cb_elems scalar_processor_2400_dmem
3594 #define HIVE_ADDR_sp_sp_max_cb_elems 0x148
3595 #define HIVE_SIZE_sp_sp_max_cb_elems 8
3598 /* function ia_css_queue_remote_init: 4C07 */
3600 /* function ia_css_queue_remote_init: 4E65 */
3603 #ifndef HIVE_MULTIPLE_PROGRAMS
3604 #ifndef HIVE_MEM_isp_stop_req
3605 #define HIVE_MEM_isp_stop_req scalar_processor_2400_dmem
3607 #define HIVE_ADDR_isp_stop_req 0x4680
3609 #define HIVE_ADDR_isp_stop_req 0x46C8
3611 #define HIVE_SIZE_isp_stop_req 4
3615 #define HIVE_MEM_sp_isp_stop_req scalar_processor_2400_dmem
3617 #define HIVE_ADDR_sp_isp_stop_req 0x4680
3619 #define HIVE_ADDR_sp_isp_stop_req 0x46C8
3621 #define HIVE_SIZE_sp_isp_stop_req 4
3624 #define HIVE_ICACHE_sp_critical_SEGMENT_START 0
3625 #define HIVE_ICACHE_sp_critical_NUM_SEGMENTS 1
3628 #endif /* _sp_map_h_ */
3630 extern void sh_css_dump_sp_dmem(void);
3631 void sh_css_dump_sp_dmem(void)