2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __CSI_RX_PRIVATE_H_INCLUDED__
16 #define __CSI_RX_PRIVATE_H_INCLUDED__
18 #include "rx_csi_defs.h"
19 #include "mipi_backend_defs.h"
20 #include "csi_rx_public.h"
22 #include "device_access.h" /* ia_css_device_load_uint32 */
24 #include "assert_support.h" /* assert */
25 #include "print_support.h" /* print */
28 /*****************************************************
30 * Native command interface (NCI).
32 *****************************************************/
34 * @brief Get the csi rx fe state.
35 * Refer to "csi_rx_public.h" for details.
37 STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_get_state(
38 const csi_rx_frontend_ID_t ID,
39 csi_rx_fe_ctrl_state_t *state)
44 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
45 state->nof_enable_lanes =
46 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX);
47 state->error_handling =
48 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX);
50 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX);
51 state->status_dlane_hs =
52 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX);
53 state->status_dlane_lp =
54 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX);
56 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX);
58 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX);
61 * Get the values of the register-set per
64 for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
65 csi_rx_fe_ctrl_get_dlane_state(
73 * @brief Get the state of the csi rx fe dlane process.
74 * Refer to "csi_rx_public.h" for details.
76 STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_get_dlane_state(
77 const csi_rx_frontend_ID_t ID,
79 csi_rx_fe_ctrl_lane_t *dlane_state)
83 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
85 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
89 * @brief dump the csi rx fe state.
90 * Refer to "csi_rx_public.h" for details.
92 STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_dump_state(
93 const csi_rx_frontend_ID_t ID,
94 csi_rx_fe_ctrl_state_t *state)
98 ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x \n", ID, state->enable);
99 ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x \n", ID, state->nof_enable_lanes);
100 ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x \n", ID, state->error_handling);
101 ia_css_print("CSI RX FE STATE Controller %d Status 0x%x \n", ID, state->status);
102 ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x \n", ID, state->status_dlane_hs);
103 ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x \n", ID, state->status_dlane_lp);
104 ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x \n", ID, state->clane.termen);
105 ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x \n", ID, state->clane.settle);
108 * Get the values of the register-set per
111 for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
112 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x \n", ID, i, state->dlane[i].termen);
113 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x \n", ID, i, state->dlane[i].settle);
118 * @brief Get the csi rx be state.
119 * Refer to "csi_rx_public.h" for details.
121 STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_get_state(
122 const csi_rx_backend_ID_t ID,
123 csi_rx_be_ctrl_state_t *state)
128 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
131 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
133 for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
134 state->comp_format_reg[i] =
135 csi_rx_be_ctrl_reg_load(ID,
136 _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX+i);
140 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX);
143 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX);
145 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX);
147 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX);
148 #if 0 /* device access error for these registers */
149 /* ToDo: rootcause this failure */
150 state->custom_mode_enable =
151 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX);
153 state->custom_mode_data_state =
154 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
155 for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
157 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
159 state->custom_mode_valid_eop_config =
160 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX);
162 state->global_lut_disregard_reg =
163 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX);
164 state->packet_status_stall =
165 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX);
167 * Get the values of the register-set per
170 for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
171 state->short_packet_lut_entry[i] =
172 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i);
174 for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
175 state->long_packet_lut_entry[i] =
176 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i);
181 * @brief Dump the csi rx be state.
182 * Refer to "csi_rx_public.h" for details.
184 STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_dump_state(
185 const csi_rx_backend_ID_t ID,
186 csi_rx_be_ctrl_state_t *state)
190 ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x \n", ID, state->enable);
191 ia_css_print("CSI RX BE STATE Controller %d Status 0x%x \n", ID, state->status);
193 for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
194 ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x \n", ID, i, state->status);
196 ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x \n", ID, state->raw16);
197 ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x \n", ID, state->raw18);
198 ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x \n", ID, state->force_raw8);
199 ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x \n", ID, state->irq_status);
200 #if 0 /* ToDo:Getting device access error for this register */
201 for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
202 ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x \n", ID, i, state->pec[i]);
205 ia_css_print("CSI RX BE STATE Controller %d Global LUT diregard reg 0x%x \n", ID, state->global_lut_disregard_reg);
206 ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x \n", ID, state->packet_status_stall);
208 * Get the values of the register-set per
211 for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
212 ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x \n", ID, i, state->short_packet_lut_entry[i]);
214 for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
215 ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x \n", ID, i, state->long_packet_lut_entry[i]);
219 /*****************************************************
221 * Device level interface (DLI).
223 *****************************************************/
225 * @brief Load the register value.
226 * Refer to "csi_rx_public.h" for details.
228 STORAGE_CLASS_CSI_RX_C hrt_data csi_rx_fe_ctrl_reg_load(
229 const csi_rx_frontend_ID_t ID,
230 const hrt_address reg)
232 assert(ID < N_CSI_RX_FRONTEND_ID);
233 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
234 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
239 * @brief Store a value to the register.
240 * Refer to "ibuf_ctrl_public.h" for details.
242 STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_reg_store(
243 const csi_rx_frontend_ID_t ID,
244 const hrt_address reg,
245 const hrt_data value)
247 assert(ID < N_CSI_RX_FRONTEND_ID);
248 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
250 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
253 * @brief Load the register value.
254 * Refer to "csi_rx_public.h" for details.
256 STORAGE_CLASS_CSI_RX_C hrt_data csi_rx_be_ctrl_reg_load(
257 const csi_rx_backend_ID_t ID,
258 const hrt_address reg)
260 assert(ID < N_CSI_RX_BACKEND_ID);
261 assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
262 return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
267 * @brief Store a value to the register.
268 * Refer to "ibuf_ctrl_public.h" for details.
270 STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_reg_store(
271 const csi_rx_backend_ID_t ID,
272 const hrt_address reg,
273 const hrt_data value)
275 assert(ID < N_CSI_RX_BACKEND_ID);
276 assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
278 ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
282 #endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */