drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_defs.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _css_receiver_2400_defs_h_
  16 #define _css_receiver_2400_defs_h_
  17
  18 #include "css_receiver_2400_common_defs.h"
  19
  20 #define CSS_RECEIVER_DATA_WIDTH                8
  21 #define CSS_RECEIVER_RX_TRIG                   4
  22 #define CSS_RECEIVER_RF_WORD                  32
  23 #define CSS_RECEIVER_IMG_PROC_RF_ADDR         10
  24 #define CSS_RECEIVER_CSI_RF_ADDR               4
  25 #define CSS_RECEIVER_DATA_OUT                 12
  26 #define CSS_RECEIVER_CHN_NO                    2
  27 #define CSS_RECEIVER_DWORD_CNT                11
  28 #define CSS_RECEIVER_FORMAT_TYP                5
  29 #define CSS_RECEIVER_HRESPONSE                 2
  30 #define CSS_RECEIVER_STATE_WIDTH               3
  31 #define CSS_RECEIVER_FIFO_DAT                 32
  32 #define CSS_RECEIVER_CNT_VAL                   2
  33 #define CSS_RECEIVER_PRED10_VAL               10
  34 #define CSS_RECEIVER_PRED12_VAL               12
  35 #define CSS_RECEIVER_CNT_WIDTH                 8
  36 #define CSS_RECEIVER_WORD_CNT                 16
  37 #define CSS_RECEIVER_PIXEL_LEN                 6
  38 #define CSS_RECEIVER_PIXEL_CNT                 5
  39 #define CSS_RECEIVER_COMP_8_BIT                8
  40 #define CSS_RECEIVER_COMP_7_BIT                7
  41 #define CSS_RECEIVER_COMP_6_BIT                6
  42
  43 #define CSI_CONFIG_WIDTH                       4
  44
  45 /* division of gen_short data, ch_id and fmt_type over streaming data interface */
  46 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB     0
  47 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB     + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH)
  48 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB    (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
  49 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB     (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
  50 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB    - 1)
  51 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB    (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH       - 1)
  52
  53 #define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4
  54 #define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT             4
  55
  56 #define hrt_css_receiver_2400_4_lane_port_offset  0x100
  57 #define hrt_css_receiver_2400_1_lane_port_offset  0x200
  58 #define hrt_css_receiver_2400_2_lane_port_offset  0x300
  59 #define hrt_css_receiver_2400_backend_port_offset 0x100
  60
  61 #define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX      0
  62 #define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX        1
  63 #define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX        2
  64 #define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX    3
  65 #define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX        4
  66 #define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX    7
  67 #define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX  8
  68 #define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX  9
  69 #define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX   10
  70 #define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX   11
  71 #define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX   12
  72 #define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX     13
  73 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX  14
  74 #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX       15
  75 #define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX         16
  76 #define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX      17
  77 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18
  78 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19
  79 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20
  80 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21
  81 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22
  82 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23
  83 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24
  84 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25
  85 #define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX            26
  86 #define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX       27
  87 #define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX            28
  88
  89 /* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
  90 #define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT                0
  91 #define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT               1
  92 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT       2
  93 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT        3
  94 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT             4
  95 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT        5
  96 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT            6
  97 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT         7
  98 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT      8
  99 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT  9
 100 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT               10
 101 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT                11
 102 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT        12
 103 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT        13
 104 #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT          14
 105 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT            15
 106 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT         16
 107
 108 #define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_                  "Fifo Overrun"
 109 #define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_                 "Reserved"
 110 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_         "Sleep mode entry"
 111 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_          "Sleep mode exit"
 112 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_               "Error high speed SOT"
 113 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_          "Error high speed sync SOT"
 114 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_              "Error control"
 115 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_           "Error correction double bit"
 116 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_        "Error correction single bit"
 117 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_    "No error"
 118 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_                  "Error cyclic redundancy check"
 119 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_                   "Error id"
 120 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_           "Error frame sync"
 121 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_           "Error frame data"
 122 #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_             "Data time-out"
 123 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_               "Error escape"
 124 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_            "Error line sync"
 125
 126 /* Bits for CSI2_DEVICE_READY register */
 127 #define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX                          0
 128 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX                2
 129 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX                     3
 130 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX                     4
 131 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX        5
 132 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX                  6
 133 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX                      7
 134
 135
 136 /* Bits for CSI2_FUNC_PROG register */
 137 #define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX    0
 138 #define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS   19
 139
 140 /* Bits for INIT_COUNT register */
 141 #define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX  0
 142 #define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16
 143
 144 /* Bits for COUNT registers */
 145 #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX     0
 146 #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS    8
 147 #define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX       0
 148 #define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS      8
 149
 150 /* Bits for RAW116_18_DATAID register */
 151 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX   0
 152 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS  6
 153 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX   8
 154 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS  6
 155
 156 /* Bits for COMP_FORMAT register, this selects the compression data format */
 157 #define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX  0
 158 #define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8
 159 #define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX  (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS)
 160 #define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8
 161
 162 /* Bits for COMP_PREDICT register, this selects the predictor algorithm */
 163 #define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0
 164 #define _HRT_CSS_RECEIVER_2400_PREDICT_1       1
 165 #define _HRT_CSS_RECEIVER_2400_PREDICT_2       2
 166
 167 /* Number of bits used for the delay registers */
 168 #define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8
 169
 170 /* Bits for COMP_SCHEME register, this  selects the compression scheme for a VC */
 171 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX  0
 172 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX  5
 173 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX  10
 174 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX  15
 175 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX  20
 176 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX  25
 177 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX  0
 178 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX  5
 179 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS  5
 180 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX   0
 181 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS  3
 182 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX  3
 183 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
 184
 185
 186 /* BITS for backend RAW16 and RAW 18 registers */
 187
 188 #define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX    0
 189 #define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS   6
 190 #define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX    6
 191 #define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS   2
 192 #define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX        8
 193 #define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS       1
 194
 195 #define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX    0
 196 #define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS   6
 197 #define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX    6
 198 #define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS   2
 199 #define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX        8
 200 #define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS       1
 201
 202 /* These hsync and vsync values are for HSS simulation only */
 203 #define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16)
 204 #define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17)
 205
 206 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH                 28
 207 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB              0
 208 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB             (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1)
 209 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT         (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1)
 210 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB             (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1)
 211 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB             (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1)
 212 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT         (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1)
 213 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT               (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1)
 214 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT               (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1)
 215
 216 // SH Backend Register IDs
 217 #define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX              0
 218 #define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX                     1
 219 #define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX                  2
 220 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX             3
 221 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX             4
 222 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX             5
 223 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX             6
 224 #define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX                      7
 225 #define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX             8
 226 #define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX             9
 227 #define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX              10
 228 #define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX              11
 229 #define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX               12
 230 #define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX                 13
 231 #define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX         14    /* Data State 0,1,2 config */
 232 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX       15    /* Pixel Extractor config for Data State 0 & Pix 0 */
 233 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX       16    /* Pixel Extractor config for Data State 0 & Pix 1 */
 234 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX       17    /* Pixel Extractor config for Data State 0 & Pix 2 */
 235 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX       18    /* Pixel Extractor config for Data State 0 & Pix 3 */
 236 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX       19    /* Pixel Extractor config for Data State 1 & Pix 0 */
 237 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX       20    /* Pixel Extractor config for Data State 1 & Pix 1 */
 238 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX       21    /* Pixel Extractor config for Data State 1 & Pix 2 */
 239 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX       22    /* Pixel Extractor config for Data State 1 & Pix 3 */
 240 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX       23    /* Pixel Extractor config for Data State 2 & Pix 0 */
 241 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX       24    /* Pixel Extractor config for Data State 2 & Pix 1 */
 242 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX       25    /* Pixel Extractor config for Data State 2 & Pix 2 */
 243 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX       26    /* Pixel Extractor config for Data State 2 & Pix 3 */
 244 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX      27    /* Pixel Valid & EoP config for Pix 0,1,2,3 */
 245
 246 #define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS                   28
 247
 248 #define _HRT_CSS_RECEIVER_2400_BE_SRST_HE                          0
 249 #define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF                         1
 250 #define _HRT_CSS_RECEIVER_2400_BE_SRST_PF                          2
 251 #define _HRT_CSS_RECEIVER_2400_BE_SRST_SM                          3
 252 #define _HRT_CSS_RECEIVER_2400_BE_SRST_PD                          4
 253 #define _HRT_CSS_RECEIVER_2400_BE_SRST_SD                          5
 254 #define _HRT_CSS_RECEIVER_2400_BE_SRST_OT                          6
 255 #define _HRT_CSS_RECEIVER_2400_BE_SRST_BC                          7
 256 #define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH                       8
 257
 258 #endif /* _css_receiver_2400_defs_h_ */