1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Access to message bus through three registers
4 * in CUNIT(0:0:0) PCI configuration space.
5 * MSGBUS_CTRL_REG(0xD0):
6 * 31:24 = message bus opcode
7 * 23:16 = message bus port
8 * 15:8 = message bus address, low 8 bits.
9 * 7:4 = message bus byte enables
10 * MSGBUS_CTRL_EXT_REG(0xD8):
11 * 31:8 = message bus address, high 24 bits.
12 * MSGBUS_DATA_REG(0xD4):
13 * hold the data for write or read
15 #define PCI_ROOT_MSGBUS_CTRL_REG 0xD0
16 #define PCI_ROOT_MSGBUS_DATA_REG 0xD4
17 #define PCI_ROOT_MSGBUS_CTRL_EXT_REG 0xD8
18 #define PCI_ROOT_MSGBUS_READ 0x10
19 #define PCI_ROOT_MSGBUS_WRITE 0x11
20 #define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0
22 /* In BYT platform for all internal PCI devices d3 delay
23 * of 3 ms is sufficient. Default value of 10 ms is overkill.
25 #define INTERNAL_PCI_PM_D3_WAIT 3
27 #define ISP_SUB_CLASS 0x80
28 #define SUB_CLASS_MASK 0xFF00
30 u32 intel_mid_msgbus_read32_raw(u32 cmd);
31 u32 intel_mid_msgbus_read32(u8 port, u32 addr);
32 void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);
33 void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
34 u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext);
35 void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data);
36 u32 intel_mid_soc_stepping(void);
37 int intel_mid_dw_i2c_acquire_ownership(void);
38 int intel_mid_dw_i2c_release_ownership(void);