drivers/staging/media/atomisp/i2c/gc0310.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Support for GalaxyCore GC0310 VGA camera sensor.
   4  *
   5  * Copyright (c) 2013 Intel Corporation. All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License version
   9  * 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  */
  18
  19 #ifndef __GC0310_H__
  20 #define __GC0310_H__
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/i2c.h>
  24 #include <linux/acpi.h>
  25 #include <linux/delay.h>
  26 #include <linux/videodev2.h>
  27 #include <linux/spinlock.h>
  28 #include <media/v4l2-subdev.h>
  29 #include <media/v4l2-device.h>
  30 #include <media/v4l2-ctrls.h>
  31 #include <linux/v4l2-mediabus.h>
  32 #include <media/media-entity.h>
  33
  34 #include "../include/linux/atomisp_platform.h"
  35
  36 /* Defines for register writes and register array processing */
  37 #define I2C_MSG_LENGTH          1
  38 #define I2C_RETRY_COUNT         5
  39
  40 #define GC0310_FOCAL_LENGTH_NUM 278     /*2.78mm*/
  41 #define GC0310_FOCAL_LENGTH_DEM 100
  42 #define GC0310_F_NUMBER_DEFAULT_NUM     26
  43 #define GC0310_F_NUMBER_DEM     10
  44
  45 #define MAX_FMTS                1
  46
  47 /*
  48  * focal length bits definition:
  49  * bits 31-16: numerator, bits 15-0: denominator
  50  */
  51 #define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064
  52
  53 /*
  54  * current f-number bits definition:
  55  * bits 31-16: numerator, bits 15-0: denominator
  56  */
  57 #define GC0310_F_NUMBER_DEFAULT 0x1a000a
  58
  59 /*
  60  * f-number range bits definition:
  61  * bits 31-24: max f-number numerator
  62  * bits 23-16: max f-number denominator
  63  * bits 15-8: min f-number numerator
  64  * bits 7-0: min f-number denominator
  65  */
  66 #define GC0310_F_NUMBER_RANGE 0x1a0a1a0a
  67 #define GC0310_ID       0xa310
  68
  69 #define GC0310_RESET_RELATED            0xFE
  70 #define GC0310_REGISTER_PAGE_0          0x0
  71 #define GC0310_REGISTER_PAGE_3          0x3
  72
  73 #define GC0310_FINE_INTG_TIME_MIN 0
  74 #define GC0310_FINE_INTG_TIME_MAX_MARGIN 0
  75 #define GC0310_COARSE_INTG_TIME_MIN 1
  76 #define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6
  77
  78 /*
  79  * GC0310 System control registers
  80  */
  81 #define GC0310_SW_STREAM                        0x10
  82
  83 #define GC0310_SC_CMMN_CHIP_ID_H                0xf0
  84 #define GC0310_SC_CMMN_CHIP_ID_L                0xf1
  85
  86 #define GC0310_AEC_PK_EXPO_H                    0x03
  87 #define GC0310_AEC_PK_EXPO_L                    0x04
  88 #define GC0310_AGC_ADJ                  0x48
  89 #define GC0310_DGC_ADJ                  0x71
  90 #if 0
  91 #define GC0310_GROUP_ACCESS                     0x3208
  92 #endif
  93
  94 #define GC0310_H_CROP_START_H                   0x09
  95 #define GC0310_H_CROP_START_L                   0x0A
  96 #define GC0310_V_CROP_START_H                   0x0B
  97 #define GC0310_V_CROP_START_L                   0x0C
  98 #define GC0310_H_OUTSIZE_H                      0x0F
  99 #define GC0310_H_OUTSIZE_L                      0x10
 100 #define GC0310_V_OUTSIZE_H                      0x0D
 101 #define GC0310_V_OUTSIZE_L                      0x0E
 102 #define GC0310_H_BLANKING_H                     0x05
 103 #define GC0310_H_BLANKING_L                     0x06
 104 #define GC0310_V_BLANKING_H                     0x07
 105 #define GC0310_V_BLANKING_L                     0x08
 106 #define GC0310_SH_DELAY                 0x11
 107
 108 #define GC0310_START_STREAMING                  0x94 /* 8-bit enable */
 109 #define GC0310_STOP_STREAMING                   0x0 /* 8-bit disable */
 110
 111 #define GC0310_BIN_FACTOR_MAX                   3
 112
 113 struct regval_list {
 114         u16 reg_num;
 115         u8 value;
 116 };
 117
 118 struct gc0310_resolution {
 119         u8 *desc;
 120         const struct gc0310_reg *regs;
 121         int res;
 122         int width;
 123         int height;
 124         int fps;
 125         int pix_clk_freq;
 126         u32 skip_frames;
 127         u16 pixels_per_line;
 128         u16 lines_per_frame;
 129         u8 bin_factor_x;
 130         u8 bin_factor_y;
 131         u8 bin_mode;
 132         bool used;
 133 };
 134
 135 struct gc0310_format {
 136         u8 *desc;
 137         u32 pixelformat;
 138         struct gc0310_reg *regs;
 139 };
 140
 141 /*
 142  * gc0310 device structure.
 143  */
 144 struct gc0310_device {
 145         struct v4l2_subdev sd;
 146         struct media_pad pad;
 147         struct v4l2_mbus_framefmt format;
 148         struct mutex input_lock;
 149         struct v4l2_ctrl_handler ctrl_handler;
 150
 151         struct camera_sensor_platform_data *platform_data;
 152         int vt_pix_clk_freq_mhz;
 153         struct gc0310_resolution *res;
 154         u8 type;
 155 };
 156
 157 enum gc0310_tok_type {
 158         GC0310_8BIT  = 0x0001,
 159         GC0310_TOK_TERM   = 0xf000,     /* terminating token for reg list */
 160         GC0310_TOK_DELAY  = 0xfe00,     /* delay token for reg list */
 161         GC0310_TOK_MASK = 0xfff0
 162 };
 163
 164 /**
 165  * struct gc0310_reg - MI sensor  register format
 166  * @type: type of the register
 167  * @reg: 16-bit offset to register
 168  * @val: 8/16/32-bit register value
 169  *
 170  * Define a structure for sensor register initialization values
 171  */
 172 struct gc0310_reg {
 173         enum gc0310_tok_type type;
 174         u8 reg;
 175         u8 val; /* @set value for read/mod/write, @mask */
 176 };
 177
 178 #define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
 179
 180 #define GC0310_MAX_WRITE_BUF_SIZE       30
 181
 182 struct gc0310_write_buffer {
 183         u8 addr;
 184         u8 data[GC0310_MAX_WRITE_BUF_SIZE];
 185 };
 186
 187 struct gc0310_write_ctrl {
 188         int index;
 189         struct gc0310_write_buffer buffer;
 190 };
 191
 192 /*
 193  * Register settings for various resolution
 194  */
 195 static const struct gc0310_reg gc0310_reset_register[] = {
 196 /////////////////////////////////////////////////
 197 /////////////////       system reg      /////////////////
 198 /////////////////////////////////////////////////
 199         {GC0310_8BIT, 0xfe, 0xf0},
 200         {GC0310_8BIT, 0xfe, 0xf0},
 201         {GC0310_8BIT, 0xfe, 0x00},
 202
 203         {GC0310_8BIT, 0xfc, 0x0e}, //4e
 204         {GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate
 205         {GC0310_8BIT, 0xf2, 0x80}, //sync output
 206         {GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output
 207         {GC0310_8BIT, 0xf7, 0x33}, //f9
 208         {GC0310_8BIT, 0xf8, 0x05}, //00
 209         {GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f
 210         {GC0310_8BIT, 0xfa, 0x11},
 211
 212 /////////////////////////////////////////////////
 213 ///////////////////   MIPI       ////////////////////
 214 /////////////////////////////////////////////////
 215         {GC0310_8BIT, 0xfe, 0x03},
 216         {GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane
 217         {GC0310_8BIT, 0x02, 0x22}, // 0x33
 218         {GC0310_8BIT, 0x03, 0x94},
 219         {GC0310_8BIT, 0x04, 0x01}, // fifo_prog
 220         {GC0310_8BIT, 0x05, 0x00}, //fifo_prog
 221         {GC0310_8BIT, 0x06, 0x80}, //b0  //YUV ISP data
 222         {GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422
 223         {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0]  //
 224         {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
 225         {GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready
 226         {GC0310_8BIT, 0x17, 0x01},
 227         {GC0310_8BIT, 0x40, 0x08},
 228         {GC0310_8BIT, 0x41, 0x00},
 229         {GC0310_8BIT, 0x42, 0x00},
 230         {GC0310_8BIT, 0x43, 0x00},
 231         {GC0310_8BIT, 0x21, 0x02}, // 0x01
 232         {GC0310_8BIT, 0x22, 0x02}, // 0x01
 233         {GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06
 234         {GC0310_8BIT, 0x29, 0x00},
 235         {GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de
 236         {GC0310_8BIT, 0x2B, 0x02},
 237
 238         {GC0310_8BIT, 0xfe, 0x00},
 239
 240 /////////////////////////////////////////////////
 241 /////////////////       CISCTL reg      /////////////////
 242 /////////////////////////////////////////////////
 243         {GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01
 244         {GC0310_8BIT, 0x01, 0x0f}, //06
 245         {GC0310_8BIT, 0x02, 0x04},
 246         {GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF
 247         {GC0310_8BIT, 0x03, 0x01}, // 0x03 //04
 248         {GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58
 249         {GC0310_8BIT, 0x05, 0x00},
 250         {GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB
 251         {GC0310_8BIT, 0x07, 0x00},
 252         {GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB
 253         {GC0310_8BIT, 0x09, 0x00}, //row start
 254         {GC0310_8BIT, 0x0a, 0x00}, //
 255         {GC0310_8BIT, 0x0b, 0x00}, //col start
 256         {GC0310_8BIT, 0x0c, 0x00},
 257         {GC0310_8BIT, 0x0d, 0x01}, //height
 258         {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
 259         {GC0310_8BIT, 0x0f, 0x02}, //width
 260         {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
 261         {GC0310_8BIT, 0x17, 0x14},
 262         {GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset
 263         {GC0310_8BIT, 0x19, 0x14}, //AD pipeline
 264         {GC0310_8BIT, 0x1b, 0x48},
 265         {GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias
 266         {GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow
 267         {GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15
 268         {GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh
 269         {GC0310_8BIT, 0x22, 0xb0},
 270         {GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r
 271         {GC0310_8BIT, 0x24, 0x16}, //15
 272         {GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range
 273
 274 /////////////////////////////////////////////////
 275 ////////////////////   BLK       ////////////////////
 276 /////////////////////////////////////////////////
 277         {GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en
 278         {GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value
 279         {GC0310_8BIT, 0x29, 0x00}, //global offset
 280         {GC0310_8BIT, 0x33, 0x18}, //offset_ratio
 281         {GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio
 282         {GC0310_8BIT, 0x2a, 0x00},
 283         {GC0310_8BIT, 0x2b, 0x00},
 284         {GC0310_8BIT, 0x2c, 0x00},
 285         {GC0310_8BIT, 0x2d, 0x00},
 286         {GC0310_8BIT, 0x2e, 0x00},
 287         {GC0310_8BIT, 0x2f, 0x00},
 288         {GC0310_8BIT, 0x30, 0x00},
 289         {GC0310_8BIT, 0x31, 0x00},
 290         {GC0310_8BIT, 0x47, 0x80}, //a7
 291         {GC0310_8BIT, 0x4e, 0x66}, //select_row
 292         {GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width
 293         {GC0310_8BIT, 0xa9, 0x80},
 294
 295 /////////////////////////////////////////////////
 296 //////////////////       ISP reg  ///////////////////
 297 /////////////////////////////////////////////////
 298         {GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48
 299         {GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en
 300         {GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en
 301         {GC0310_8BIT, 0x44, 0x18}, // 0x18 //02
 302         {GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync
 303         {GC0310_8BIT, 0x49, 0x03},
 304         {GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp
 305         {GC0310_8BIT, 0x50, 0x01}, //crop enable
 306         {GC0310_8BIT, 0x51, 0x00},
 307         {GC0310_8BIT, 0x52, 0x00},
 308         {GC0310_8BIT, 0x53, 0x00},
 309         {GC0310_8BIT, 0x54, 0x01},
 310         {GC0310_8BIT, 0x55, 0x01}, //crop window height
 311         {GC0310_8BIT, 0x56, 0xf0},
 312         {GC0310_8BIT, 0x57, 0x02}, //crop window width
 313         {GC0310_8BIT, 0x58, 0x90},
 314
 315 /////////////////////////////////////////////////
 316 ///////////////////   GAIN       ////////////////////
 317 /////////////////////////////////////////////////
 318         {GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain
 319         {GC0310_8BIT, 0x71, 0x20}, // pregain gain
 320         {GC0310_8BIT, 0x72, 0x40}, // post gain
 321         {GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0
 322         {GC0310_8BIT, 0x5b, 0xc9}, //c9
 323         {GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level
 324         {GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain
 325         {GC0310_8BIT, 0x78, 0x40}, // G gain
 326         {GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f
 327
 328         {GC0310_8BIT, 0x48, 0x00},
 329         {GC0310_8BIT, 0xfe, 0x01},
 330         {GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode
 331
 332         {GC0310_8BIT, 0x3e, 0x40},
 333         {GC0310_8BIT, 0x3f, 0x5c},
 334         {GC0310_8BIT, 0x40, 0x7b},
 335         {GC0310_8BIT, 0x41, 0xbd},
 336         {GC0310_8BIT, 0x42, 0xf6},
 337         {GC0310_8BIT, 0x43, 0x63},
 338         {GC0310_8BIT, 0x03, 0x60},
 339         {GC0310_8BIT, 0x44, 0x03},
 340
 341 /////////////////////////////////////////////////
 342 /////////////////       dark sun   //////////////////
 343 /////////////////////////////////////////////////
 344         {GC0310_8BIT, 0xfe, 0x01},
 345         {GC0310_8BIT, 0x45, 0xa4}, // 0xf7
 346         {GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun value th
 347         {GC0310_8BIT, 0x48, 0x03}, //sun mode
 348         {GC0310_8BIT, 0x4f, 0x60}, //sun_clamp
 349         {GC0310_8BIT, 0xfe, 0x00},
 350
 351         {GC0310_TOK_TERM, 0, 0},
 352 };
 353
 354 static struct gc0310_reg const gc0310_VGA_30fps[] = {
 355         {GC0310_8BIT, 0xfe, 0x00},
 356         {GC0310_8BIT, 0x0d, 0x01}, //height
 357         {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
 358         {GC0310_8BIT, 0x0f, 0x02}, //width
 359         {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
 360
 361         {GC0310_8BIT, 0x50, 0x01}, //crop enable
 362         {GC0310_8BIT, 0x51, 0x00},
 363         {GC0310_8BIT, 0x52, 0x00},
 364         {GC0310_8BIT, 0x53, 0x00},
 365         {GC0310_8BIT, 0x54, 0x01},
 366         {GC0310_8BIT, 0x55, 0x01}, //crop window height
 367         {GC0310_8BIT, 0x56, 0xf0},
 368         {GC0310_8BIT, 0x57, 0x02}, //crop window width
 369         {GC0310_8BIT, 0x58, 0x90},
 370
 371         {GC0310_8BIT, 0xfe, 0x03},
 372         {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0]  //
 373         {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
 374
 375         {GC0310_8BIT, 0xfe, 0x00},
 376
 377         {GC0310_TOK_TERM, 0, 0},
 378 };
 379
 380 static struct gc0310_resolution gc0310_res_preview[] = {
 381         {
 382                 .desc = "gc0310_VGA_30fps",
 383                 .width = 656, // 648,
 384                 .height = 496, // 488,
 385                 .fps = 30,
 386                 //.pix_clk_freq = 73,
 387                 .used = 0,
 388 #if 0
 389                 .pixels_per_line = 0x0314,
 390                 .lines_per_frame = 0x0213,
 391 #endif
 392                 .bin_factor_x = 1,
 393                 .bin_factor_y = 1,
 394                 .bin_mode = 0,
 395                 .skip_frames = 2,
 396                 .regs = gc0310_VGA_30fps,
 397         },
 398 };
 399
 400 #define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
 401
 402 static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
 403 static unsigned long N_RES = N_RES_PREVIEW;
 404 #endif